JPS6083392A - Method of producing printed circuit board - Google Patents
Method of producing printed circuit boardInfo
- Publication number
- JPS6083392A JPS6083392A JP19179483A JP19179483A JPS6083392A JP S6083392 A JPS6083392 A JP S6083392A JP 19179483 A JP19179483 A JP 19179483A JP 19179483 A JP19179483 A JP 19179483A JP S6083392 A JPS6083392 A JP S6083392A
- Authority
- JP
- Japan
- Prior art keywords
- board
- printed wiring
- cut
- circuit board
- printed circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
- Structure Of Printed Boards (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】 本発明は印刷配線板の製造り法に関するものである。[Detailed description of the invention] The present invention relates to a method for manufacturing printed wiring boards.
印刷配線板は、通常、端の部分にはスルーホールが設り
られていないが、特殊な用途には、基板をスルーホール
の箇所でｆ＆断して喘にスルーホールの一部を残したも
のが用いられることがある。Printed wiring boards usually do not have through-holes at the edges, but for special purposes, the board is cut off at the through-holes, leaving part of the through-holes. is sometimes used.
ところで、基板をスルーホールの箇所で裁断する場合、
従来はプレスを用いているが、基板に印刷された配線を
栴成する金属層がスルーホールの箇所での接着ノ〕が非
常に低いために、プレスの際にこの箇所の金属層の一部
が剥離する欠点があった。By the way, when cutting the board at the through-hole location,
Conventionally, a press is used, but because the metal layer that forms the wiring printed on the board has very low adhesion at the through-hole locations, some of the metal layer at these locations is removed during pressing. The problem was that it peeled off.
本発明は、上記の欠点を改良し、スルー小−ルでの裁断
の際の金ａ層の剥離を防止しうるＱ］刷配線板の製造方
法の提供を目的とするものである。The object of the present invention is to provide a method for manufacturing a Q] printed wiring board that can improve the above-mentioned drawbacks and prevent the gold A layer from peeling off during cutting with a small through-hole.
本発明は、上記の目的を達成するために、スルーホール
を有する基板に任意の印刷配線を設Ｃプだ後に、該基板
を該スルーボールの箇所で裁断する印刷配線板の製造方
法において、基板をスルーホールの箇所でＶカット方法
により裁断することを特徴とする印刷配線板の製造方法
を提供するものである。In order to achieve the above object, the present invention provides a method for manufacturing a printed wiring board, in which a circuit board having through holes is cut with arbitrary printed wiring after the board is cut at the through holes. The present invention provides a method for manufacturing a printed wiring board, characterized in that the printed wiring board is cut by a V-cut method at the through-hole locations.
以下、本発明を実施例に基づいて説明する。Hereinafter, the present invention will be explained based on examples.
第１図に示す通り、基板１としては、紙フエノール樹脂
積層板や紙エポキシ樹脂積層板宿を用いる。この基板１
にはスルーホール２が設けられでいる。そしてこの基板
１の表面及びスルー小−ル２の箇所にＣ０−４法やＡＰ
−ＩＩ法等のアデイテイブ法により銅メッキ層３を設【
ノる。銅メッキ層３を設けた後、第２図に示す通り、ス
ルーホール２の箇所で基板１をＶカットマシンにＪ：す
ａｌｆｉシて２１１１ａに分離する。As shown in FIG. 1, a paper phenol resin laminate or a paper epoxy resin laminate is used as the substrate 1. This board 1
A through hole 2 is provided in the. Then, apply the C0-4 method or AP to the surface of this board 1 and the small through hole 2.
- Copper plating layer 3 is established by additive method such as II method.
Noru. After providing the copper plating layer 3, as shown in FIG. 2, the substrate 1 is cut into pieces 2111a using a V-cut machine at the locations of the through holes 2.
すなわち、スルーホール２の箇所で基板１を裁断するの
に従来のプレス方法の代りに■カット方法を用いている
ため、裁断時に銅メッキＷＩ３に加わる力が小ざく、ス
ルーホール２に設りられた銅メッキ層３の剥離が防止さ
れる。That is, since the cutting method is used instead of the conventional pressing method to cut the board 1 at the through-hole 2, the force applied to the copper plating WI3 during cutting is small, and the This prevents the copper plating layer 3 from peeling off.
なお、上記の実施例においては、アディティブ法による
印刷配線板について；ホべたが、エツチドフォイル法に
よる印刷配線板についても同様に金属層の剥離が防止さ
れる。In the above embodiments, the printed wiring board produced by the additive method was described; however, peeling of the metal layer is similarly prevented in the printed wiring board produced by the etched foil method.
以上の通り、本発明によりスルーホール裁断時の金属層
の剥離が防止され信頼性の＾い印刷配線板の製造方法が
得られる。As described above, the present invention provides a method for manufacturing a printed wiring board that prevents peeling of the metal layer during through-hole cutting and is highly reliable.
第１図は本発明の実施例の裁断＋１ｆ＋の印刷配線板の
平面図、第２図は第１図の印柚配線板をＪ＆断した後の
平面図を示す。
１・・・基板、 ２・・・スルーホール、３・・・銅メ
ッキ層。
特許出願人 日立コンデンリ株式会社FIG. 1 is a plan view of a printed wiring board cut +1f+ according to an embodiment of the present invention, and FIG. 2 is a plan view of the printed wiring board of FIG. 1 after being cut by J&. 1... Board, 2... Through hole, 3... Copper plating layer. Patent applicant: Hitachi Kondenri Co., Ltd.
Claims (1)
設けた後、該基板を該スルーホールの箇所で裁断する印
刷配線板の製造方ｄ１において、基板をスルーホールの
箇所でＶカツト力法により裁断することを特徴とする印
刷配線板の製造方法。(1) In method d1 of manufacturing a printed wiring board, in which arbitrary printed wiring is provided on a board having through holes, and then the board is cut at the locations of the through holes, the board is cut at the locations of the through holes by the V-cutting force method. A method for manufacturing a printed wiring board, which includes cutting.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19179483A JPS6083392A (en) | 1983-10-14 | 1983-10-14 | Method of producing printed circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19179483A JPS6083392A (en) | 1983-10-14 | 1983-10-14 | Method of producing printed circuit board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6083392A true JPS6083392A (en) | 1985-05-11 |
Family
ID=16280645
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19179483A Pending JPS6083392A (en) | 1983-10-14 | 1983-10-14 | Method of producing printed circuit board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6083392A (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5753670B2 (en) * | 1973-08-24 | 1982-11-13 | ||
| JPS58123795A (en) * | 1982-01-19 | 1983-07-23 | アルプス電気株式会社 | Circuit board |
-
1983
- 1983-10-14 JP JP19179483A patent/JPS6083392A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5753670B2 (en) * | 1973-08-24 | 1982-11-13 | ||
| JPS58123795A (en) * | 1982-01-19 | 1983-07-23 | アルプス電気株式会社 | Circuit board |
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