JPS6081657A - Data control system - Google Patents

Abstract

PURPOSE:To rotate storage information to read/write data by dividing address counters designating addresses to a storage part and controlling the connection and forward/backward of respective counters. CONSTITUTION:The address counters are divided, a counter 11 outputs the 0-th and 1st bits of address bits and a counter 12 outputs the 2nd and 3rd bits. Selectors 13, 14 control the connection and forward/backward of both counters 11, 12. At the reading time in said constitution, a control part 15 turns off and S1 signal 16, turns on an S2 signal 17, turns both forward/backward control signals U/D1 21, U/D2 22 to a forward mode, and both counters 11, 12 are set up to ''0''. Consequently, addresses are controlled so as to be forwarded from ''0'' to ''15'' successively and outputted as reading data, so that data turned to the left by 90 deg. can be outputted. If both signals 21, 22 are turned to the backward mode similarly, data turned by 180 deg. are outputted to read/write the data.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a data control system that enables rotatable reading/writing of stored information in a storage means.

[Prior Art] Conventionally, a storage device has a configuration shown in the block diagram of FIG. In the figure, 1 is a memory, 2 is a selector that selects and outputs an address to the memory 1, 3 is a write address counter for the memory 1, 4 is a read address counter for the memory 1, and 5 is a control section.

With the above configuration, when rotating the storage information of the storage device, such as when rotating the display of the display device by 90° or 180°, to read/write, the central processing unit (not shown) controlling the storage device etc. convert the write information into a rotated state, write the write data 6 and the write address, set it in the address counter 3, and when reading, read out the rotated information by sequentially counting up the read address counter 4. Read out as information 7.

Alternatively, writing is controlled so that the write address counter 3 is sequentially counted and stored, the information is stored as is without rotation, and when reading, the address information to the read address counter 4 is rotated and read out.

However, in either case, extremely complicated address control was unavoidable.

[Purpose] The present invention aims to eliminate the above-mentioned drawbacks of the prior art, and the purpose of the present invention is to rotate and read/write stored information by dividing the address counter that specifies the address to the storage section, and dividing the address counter to specify the address to each storage section. The purpose of this invention is to propose a data control method that is possible only by connecting address counters and controlling acceleration and deceleration.

[Example] An embodiment of the present invention will be described below with reference to the drawings.

FIG. 2 is a block diagram of a storage device according to an embodiment of the present invention.

In the figure, 1 is a memory, 11 is a counter 1 which outputs the 0th bit and the bit 12 of the address bit, and 12 is a counter 2 and 13 which outputs the 2nd and 3rd bit of the address bit. 14 is a selector that controls the combination and increment of both counters, 3 is the A selector, and 14 is the B selector. 15 is a control section.

Here, for convenience of explanation, the address is assumed to be 4 bits, and the memory capacity of the memory 1 is assumed to be 16 words. The address arrangement of memory 1 is as shown in Figure 3. If data is not rotated between memory area addresses 0 and 15, the addresses are arranged as shown in Figure 4 (A). "A at address 0", "B at address i"°, P at address -1 "'15"
shall be stored.

The case where the data shown in FIG. 4(A) is rotated 90 degrees to the left and stored in the memory 1 as shown in FIG. 4(B) will be described below.

The control unit 15 shown in FIG. 2 turns on the S1 signal 16 and
C where the selector 13 is the carrier signal from the counter 2
A2 signal 20 to the clock input of counter 1 (11),
The S2 signal is turned off, the B selector 14 controls the clock signal 18 from the control 6815 to be input to the clock input of the counter 2 (12), and the U signal which is the return/deceleration control signal to the counter 1 (11) is inputted to the clock input of the counter 2 (12). The /D l signal 21 is set to acceleration mode, and the U/D 2 signal 22, which is a return/deceleration control signal to counter 2 (12), is set to deceleration mode. Then, each counter is set to "0°" in return mode and 3'' in deceleration mode.In other words, in this case, counter 1 (11) is set to "O" and counter 2 (12) is set to 3.
”.

As a result, the counter combination is such that counter 1 (it) becomes the upper counting position and counter 2 (12) becomes the lower counting position.
The clock signal 18 is sent to the counter 2 via the B selector 14.
(12) is input as the clock input of counter 1 (1
The carrier signal CA2 of the counter 2 (12) is input to the clock input of the counter 1). Therefore, counter 2 = 3, counter 1 = 0 → counter 2 = 2, counter 1 = 0 → ・Q
- Counter 2 = 0, counter l = 3, and the contents of counter 2 and counter 1 change.

Therefore, the address is (12) → (8) → (4) → (0)
→(13)→...It becomes excellent and the final address becomes (3). That is, the data is stored in the memory 1 as shown in FIG. 4(B). Therefore, during reading, the control section 15 uses the Sl signal 16
Off, S2 signal 17 on, U/D 1 signal 21 and U/
Both D2 signals 22 are set to acceleration mode, and both counters are set to “0”.
Data rotated 90 degrees to the left is output by setting the output signal and controlling the address so that it is accelerated sequentially from (0) to (15) and outputting it as read data.

In addition, in order to rotate 180 degrees and store it in the memory 1 as shown in FIG. 4(D), turn off the S1 signal 16 and turn on the S2 signal. is the upper level, and U/D l signal 21 and U/D l signal 21 and U/D
Both D2 signals 22 may be set to deceleration mode. In this case, both counter i' (ti) and counter 2 (12) are "
'3' is set.

In addition, in order to rotate 90 degrees to the right as shown in Fig. 4(C), turn on the Sl signal 16, turn off the S2 signal, set the counter connection so that the counter 1 (11) is the upper one, the counter 2 (12) is the lower one, and the U
It is sufficient to set the /Dl signal 21 to deceleration mode and the U/D2 signal 22 to acceleration mode, and set counter 1 (11) to '3' and counter 2 (12) to '0'.

The above settings are summarized in FIG. 5(A).

In the above explanation, the data was rotated and stored when writing to memory 1, but when writing,
As shown in A), data is stored without being rotated, and even if counter coupling and acceleration/deceleration control are performed at the time of reading, the data is output in a rotated state.

Control during reading is shown in FIG. 5 CB).

In the above description, the memory l has 16 words and the address bits have 4 bits, but the capacity of the memory can be increased by increasing the number of bits of the counter.

It is clear that even when only a specific area in the memory is to be rotated, this can be done by changing the storage address in the counter in correspondence with the address at the end of the area.

Also, by changing the division ratio of the counter, the area can be
It can be set freely like M.

[Effects] As explained above, according to the present invention, in order to rotate the stored information in the storage means, only the division of the address counter that specifies the address and the return/deceleration control of the address counter are required, and complicated address control is required. It is possible to provide a data control method that is possible without having to do anything.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an address control system of a conventional storage device, FIG. 2 is a block diagram of an address control system of a storage device according to an embodiment of the present invention, and FIG. 3 is a diagram showing an example of memory address arrangement. Figure 4 (A
) to (D) are diagrams showing the rotation state of memory storage data, Figure 5 (A) is a diagram showing address counter control when rotating data when writing to memory, and Figure 5 (B) is a diagram showing the rotation state of data stored in memory. FIG. 7 is a diagram illustrating control of an address counter when rotating data. In the figure, 1...memory, 2...selector, 3...
- Write address counter, 4... Read address counter, 5, 15... Control unit, 11... Counter 1.12... Counter 2.13... A selector,
14...B selector. 2nd cause Figure 3 Figure 4 (A) Figure 5 (A) Figure 5 (B)

Claims (1)

[Claims] In a data control system for rotating and reading/writing stored information in a storage means, a plurality of address designation means capable of counting acceleration/deceleration for designating read/write addresses of the storage means; 1. A data control system comprising: address control means that controls connections and acceleration/deceleration counts to enable rotatable reading/writing of information stored in the storage means.