JPS6081656A - Address converter - Google Patents

Abstract

PURPOSE:To form a part or the whole of a conversion table speedily by an address converting means by providing the address converting means with a control circuit, a counter circuit, etc. and outputting a control signal, a counted value signal, etc. to control address conversion. CONSTITUTION:In the initial state turning on a power supply to a CPU1, a reference table is formed in an RAM2, and even on the way of movement, the table is changed if necessary. Namely, a table is formed by a control signal, a counted value signal CN, etc. outputted from the control circuit 4, the counter circuit 9, etc. and the same data are written in the address of the RAM2. At the use of the table, a value addressed by an address signal US frm the CPU1 is applied as an address signal UA' of a main memory 3 as it is. Thus, the formation of the circuits 4, 9, etc. makes it possible to form a part or the whole of the address conversion table speedily and execute also initializing simultaneously.

Description

[Detailed description of the invention] [Technical field] The present invention relates to a memory address translation device.

[Prior Art] In recent years, even in personal computers, a program once compiled can be executed at any location in the main memory. This is because personal computers have a configuration that converts a program compiled with relative addresses into absolute memory addresses when the program is executed. It is well known that such a configuration further increases the processing power of personal computers and improves memory usage efficiency.

In general, improving processing power and improving memory usage efficiency are always regarded as technical issues, and in this regard, a memory management unit (MMU) has been provided. The MMU is on a bus that corresponds to the address of the processor and functions to optimally allocate physical space in main memory to the processor. Specifically, it is constituted by means for converting information of upper bits on the address bus.

FIG. 1 is a conceptual diagram for explaining this address translation operation. In order to simplify the explanation, a 4-bit address bus configuration is shown. In the figure, l is a central processor (CPU), and A0 to A3 constitute address signals on the address bus on the CPU1 side. A3 is the most significant bit and Ao is the least significant bit. 2 is a random access memory (RAM) and receives an input signal a as an address. +al and data output signal dO,d, are shown. Although not shown, appropriate data, that is, a conversion table, can be written into the RAM 2 under control from CPtJl. 3 is a main memory, and the address signal on its address bus is composed of Ao-A3'. As is clear from the figure, the upper two bits A of the address bus. , A1 is common to the CPUI side and the main memory 3 side, and the upper 2
Bits A2 * A3 undergo conversion in RAM2 and become the upper 2-bit address signal A2' on the main memory side.
.

It is given as A3'. In other words, it is address signal A on the CPU side. + A I + A 2 + A3 is the address signal AO + A I + A2 on the main memory side.
'.

It shows the configuration converted to A3'.

FIG. 2 is an explanatory diagram showing the contents of the conversion table stored in the RAM 2. Further, FIG. 3 is an explanatory diagram showing a comparison between the value after address conversion using the RAM of FIG. 2 and the original value. From the above, it can be seen that the address conversion is arbitrary according to the contents of the RAM 2, and how the address data is converted can be determined by rewriting the contents of the RAM 2 depending on the processing purpose.

Conventionally, this kind of writing and clearing of the RAM table has been done by processing a step-by-step program. Therefore, it takes a long time to create a RAM table, making it impossible to improve the real-time processing capacity of the processor as a whole.

[Objective] The present invention has been made in view of the drawbacks of the above-mentioned conventional techniques (i. It is about providing.

Another object of the present invention is to provide an address translation device that can initialize the translation table all at once when the device is powered on or during operation.

[Embodiment] In the above, an address translation device according to an embodiment of the present invention will be described in detail with reference to the drawings. FIG. 4 is a block diagram showing the configuration of an address translation device according to an embodiment. In the figure, parts having the same functions as those in FIG. 1 are given the same reference numerals. The signals given from the CPU 1 side are the data signal on the data bus, the address signals UA and LA on the address/hess, the clock signal CLK which is the source of the CPU machine cycle, and the CPU operating mode or special function. The decoded signal e, − formed by the execution of the instruction
It is e4. Here, address signal UA indicates a group of upper bits, and address signal LA indicates a group of lower bits. 2 is a RAM that stores the address translation table
, 3 is the main memory of the CPUI. Furthermore, 4 is a control circuit which outputs predetermined control signals 01-C9 in accordance with the clock signal CLK by inputting any of the decode signals e1-e4. 5 to 8 are 8/27 circuits that operate in a 3-state output mode to enable wire FOR of each output line. For example, to explain the 827 circuit 5, the buffer circuit 5 receives the control signal C.
It operates when the level of 2 is 1. In other words, the level 110 of the output address signal UAD is output in accordance with the level 110 of the input address signal UA. Furthermore, when the level of the control signal C2 is 0, it does not operate and the circuit for the output address signal UAD is kept at high impedance. 9 is a counter circuit incorporating a 3-state output buffer, and when the control signal CI is 0, the counter is forcibly reset, and its count value output CN
circuit is kept at high impedance. Further, when the control signal C1 becomes 1, counting is started using the clock signal CLK, and at the same time, the count value signal CN is output. When the count value of the counter reaches a predetermined value, a carry signal CA at a level of 0 is output, deactivating the input of the AND gate 10, and stopping the counting operation. 11 is a selector circuit whose details are shown in FIG. Here, for ease of explanation, a 4-bit circuit configuration is shown. One input of the selector circuit is the count value output CN, -C from the counter circuit 9.
It is N3. The other input is data signals D2 and D3 from the data bus. Here data signal D3
corresponds to the upper bit, and D2 corresponds to the next bit. Data signals D 2 + D 3 are transferred to latches 11, . . . by pulses of control signal C4. 112 respectively. A data selector 113 selects either the input signal group indicated by terminal A or the input signal group indicated by terminal B according to the level of control signal C5, and outputs signals 0° to 03. In the embodiment, when the level of the control signal C5 is O, the input signal of the terminal A group is selected and output, and when the level is 1, the input signal of the group of terminal A is selected and output.
When , the human input signal of the terminal B group is selected and output.

In the above configuration, the operation of the embodiment will be described below.

First, when the CPUI is in the normal instruction execution mode, the level of the decode signal e is 1, and the other decode signals are O. Under this state, control signals c2, C7+C8, and C9 are all 1, and the other control signals are 0. Here, control signal C3
Level 0 of energizes the chip select of RAM2. Furthermore, the level 1 of the control signal C9 prevents data from being written into the RAM2. Therefore, the upper address signal UA of the CPUI is given as the address input signal a of the RAM 2 via the input buffer 5. At this time, since the output circuit of the counter circuit 9 is in high impedance, it does not affect the address input signal a in any way. RAM2 outputs a data signal d corresponding to the address input signal a. At this time/
Since the output circuit of the buffer 6 is of high impedance, it does not affect the data signal d in any way. Therefore, the data signal d passes through the packer 8 as it is and becomes the upper address signal UA' of the main memory. On the other hand, the lower address signal LA of the CPUI passes through the buffer 7 and becomes the lower address signal LA of the main memory 3 as it is. In this way, in the normal mode, the address signals UA and LA from the CPU 1 where instructions are executed are the upper pins l-UA.
The main memory 3 is accessed only in the form converted to UA' by the conversion table in the RAM 2. If an appropriate conversion table is formed in the RAM 2, the CPUI will operate normally.

Now, in the initial state when the power is turned on to the CPU, RAM2
The first translation table must be written to . Furthermore, the table must be changed as necessary even during operation. These operations will be explained below. The first operation described here is the creation of a standard table such that the address space output by the CPU matches the physical address space of the main memory. In other words, when CPtJl or address 1 is output, absolute address 1 of main memory 3 is accessed, and CP
When the UI outputs address 1000, the absolute 10 of main memory 3
This is the creation of a table in which address 00 is accessed. In the execution cycle of the standard table creation instruction, the decode signal e2 is set to level 1. The other decode signal is O. Although not shown, an initial reset signal is output when the power is turned on to the CPU main body.
When this is deactivated, the decode signal e2 is activated to 1 (i) in the hardware configuration. In this state, the control signals C2, C7, and C8 are all 0,
The output circuits of buffers 5, 7.8 are kept at high impedance. In addition, the control signals C5 and C6 become 1, the data selector 113 in the selector circuit 11 selects and outputs the input signal of the group of terminal B, and the buffer 6 to 7 transfers the selected and output signal to the data bus of RAM2. It is in a state of conduction. Furthermore, when the level of the control signal C1 becomes 1, the forced reset of the counter circuit 9 is released.

At the same time, the built-in /Hera2f circuit operates and outputs the count signal CN. In this state, the counter circuit 9 counts up from O in response to the clock signal CLK. At this time, since the buffer 5 has no effect on the count value signal CN, the signal CN becomes the address input to the RAM 2 without changing its value. At the same time, the signal CN is connected to the terminal B of the selector circuit 11.
input into the group and output the selection as is. Further, a data signal of the count value is applied to the data bus of the RAM 2 via the buffer 6.

A timing chart for writing to RAM2 is shown in FIG. Here, address input signal a of RAM2
When counting up from O to 3, the pulse level 0 of the chip select signal c3 (C3) and the pulse level 0 of the write enable signal C9 (WE) are applied to the data signal of the count value. A state in which values 0 to 3 are sequentially written is shown. When the count value eventually reaches a predetermined value, the 0 level of the carry signal CA is output, deactivating the input of the AND game 10, and stopping the count-up. This predetermined value is made to match the capacity of RAM2. Furthermore, the carry signal CA is input to the control circuit 4 to notify the end of the write operation T, and the control circuit 4 inputs the CP
A status signal Sl indicating completion of execution is sent to the UI to enable execution of the next instruction.

In the table created in this way, the same data is written at the address of RAM2. Therefore, when the table is used, the same value as addressed by the address signal UA of the cPU is given as the address signal UA' of the main memory 3. There is a benefit in creating such a standard table, especially in the initial state of the CPU itself, and often during operation. In other words, normal programs are executed normally. Further, as described in the prior art, great effects can be obtained by simply adding the above-described functional configuration based on the decode signal e2 to an apparatus that creates a conversion table in a step-by-step method using a program. This is because no matter what translation table is formed, the machine can instantly return to the normal addressing state if necessary. In addition, if it is intended to change some data in the RAM 2 by a program in the embodiment, a buffer 12 is provided on the data/head from the CPUI side as shown in FIG. Activate buffer 12 and press R
It is sufficient to control the writing of data D to the address UA of AM2. Also, if the buffer 12 is controlled bidirectionally, R
The contents of AM2 can also be read out to the CPUI.

The second operation to be described next is the creation of a conversion table in the case where the address space output by the CPU and the physical address space of the main memory do not match. In the execution cycle of the conversion table creation command, level 1 is applied to the decode signal e3. The other decode signal is O. The subsequent operations are the same as those for creating the standard table described above, but one difference is that level 0 is given to the control signal C5. Therefore, the data selector 113 in the selector circuit 11 selectively outputs the input signal of the terminal A group. Looking at the input signals of the terminal A group in FIG. 5, the upper two bits are the outputs of the latches t't, tt2, and the lower two bits are the count value signal CNO of the counter circuit 9.

It is CN. Therefore, the upper two bits are fixed to a predetermined value when the table is created. For example, latches 11, . If both 112 and 112 hold the value O, the data of the upper two bits of the conversion table created in the RAM 2 will always be O even though the address is updated. When the conversion table created in this manner is used, a relationship as shown in FIG. 7 occurs between the CPU address space and the physical address space of the main memory. That is, when the upper 4 bits of the address space on the CPU'Ul side can take the value O-F, the value of the upper 4 bits of the physical address space on the main memory 3 side is always O-3. In this way, for example CP
The program compiled for address block A3 on the UI side is loaded as is into physical block M1 on the main memory side and executed.

Which memory block to convert to is easily set by the CPUI. The CPUI executes the latch setting command at an appropriate time. When the latch setting command is executed, level 1 is applied to the decoder signal e4. The control circuit 4 outputs the latch pulse of the control signal C4 at a predetermined timing, and controls the data signals of the CPU 1 (D3. Set D2 to latches 11□ and 112, respectively. Although the number of latches is two in the embodiment, it is not limited to this.

For example, if the number of latches is four, any one of the memory blocks of 1/16 the size of the main memory 3 shown in FIG. 7 can be selected.

Incidentally, such an address conversion device can be used not only to convert an address signal from a CPU, but also to convert an address signal from an I10 device. It can also be used to convert address signals sent to I10 devices.

[Effects] As described above, according to the present invention, an address conversion table can be created extremely quickly, so that simple and effective memory management can be performed even in real-time processing. Furthermore, the ability to initialize the conversion table all at once by executing a command is useful both when the device is powered on or during operation.

[Brief explanation of drawings]

FIG. 1 is a conceptual diagram explaining the address translation operation, FIG. 2 is an explanatory diagram showing the contents of address translation RAM, and FIG. 3 is an explanatory diagram showing a comparison between the value after address translation and the original value. FIG. 4 is a block diagram showing the configuration of an address translation device according to one embodiment, FIG. 5 is a circuit diagram showing details of the selector circuit, and FIG.
A timing chart showing writing to AM. FIG. 7 is an explanatory diagram showing one mode of address conversion. Here, 1... Central processor, 2... Random access memory, 3... Main memory, 4... Control circuit, 5-8... Buffer circuit, 9... Counter circuit, lO. . . . AND gate, 11 . . . selector circuit. Figure 1 Cause 2 Figure 5 Figure 11 Figure 6 Figure 7

Claims (2)

[Claims] (1) An address conversion device that converts address information, including a storage unit that stores an address conversion table, and a counter that provides both an address signal and a data signal for writing data when creating the conversion table to the storage unit. An address translation device comprising: means. (2) An address conversion device that converts address information, including a storage unit that stores an address conversion table, and a counter that provides both an address signal and a data signal for writing data to the storage unit when creating the conversion table. and means for replacing some or all bits of the data signal with a set value.