JPS6080326A - Agc circuit - Google Patents

Abstract

PURPOSE:To attain the control of an AGC circuit of radio communication equipment provided with a digital mode selection circuit by controlling a circuit switching a charge/discharge circuit of a capacitor for time constant with mode selecting information. CONSTITUTION:The mode selection information formed by an integrated value of a pulse integration counter 6 is inputted to a programmable counter 13 as frequency division information via a data bus 6b and a decoder 11. A pulse transmitted from a pulse generating circuit 12 to a counter 13 is frequency-divided in response to the frequency division information and inputted to a switching terminal 15a of a time constant circuit 15. On the other hand, a detected output generated by an AGC detection circuit 7 is fed from a collector of a transistor Q2 to an AGC line as an AGC voltage. Since the time constant circuit 15 is connected to the AGC line, the level of the AGC voltage is decided according to the time constant characteristic. Since the time constant characteristic is controlled by a frequency division characteristic, the AGC voltage corresponding to the mode is generated.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an AGC circuit, and more particularly to an AGC circuit applied to a wireless communication device in which mode switching means for switching received radio wave types is digital.

Conventionally, there are AGC circuits of various types such as peak value AGC and average value AGC, and in radio communication devices, peak value AGC is used in radio wave type SOB, and average value AGC is used in AM. To select the radio wave type, select the mode by operating the mode selection up button 9 and mode selection down button 10 provided on the operation panel 5. There are ways to generate information. In this system, mode selection information is obtained by outputting the integrated value of the pulse integrating counter 6 in parallel to the controlled circuit via the data interface 6a. Received signal f from antenna 1
l is the output signal f via the RF unit 1,000, intermediate frequency circuit 3, audio circuit 4, and terminal 4a. The signal is then sent to various circuits in subsequent stages. The AGC circuit includes an AGC detection circuit 7 and a time constant circuit 8. The integrated value of the pulse integration counter 6 is sent to a time constant circuit network consisting of resistors and capacitors including a wired logic circuit (not shown) formed by diodes, etc., to generate a time constant according to the mode. It has become.

In the above-mentioned AGC circuit, since the AGC detection circuit 7 and the time constant circuit 8 are analog quantities, when analog control members such as variable resistors are not provided on the operation panel 5, in other words, the pulse integration counter 6 It has the disadvantage that it cannot be controlled by a circuit that uses digital quantities as control information.

The present invention has been made in view of the above-mentioned points, and an object of the present invention is to provide an AGC circuit applicable to a computer-aided radio communication device provided with a digital mode selection circuit.

In the present invention, the integrated value of the multimeter integration counter forming the digital mode selection circuit is used as the mode selection information. A programmable counter is programmed using this mode selection information to divide the frequency of the pulses generated by the pulse generation circuit. This frequency-divided pulse is configured to control a switching circuit that switches a charging/discharging circuit of a time-determined rupture capacitor provided in a time constant circuit to obtain a desired time constant.

An embodiment of the AGC circuit according to the present invention will be described below with reference to FIG.

In FIG. 2, 6 is a Norse integration counter.

The pulse integration counter 6 is operated by a mode selection phase up button 9 and a mode selection down button 10 provided on the operation panel 5.
Addition pulse or subtraction A that often occurs during operation? Accumulate the pulse. To display the selected mode, mode selection information formed by the integrated value is displayed on a display (not shown). In addition, the mode selection information is stored on the data bus 6.
a to the controlled circuit.

The programmable counter 13 is the base pulse integration counter 6.
The mode selection information formed by the integrated value of
, the decoder 11 and the data bus 11a, and are input as branch information. The pulse sent from the pulse generation circuit 12 to the programmable counter 13 is frequency-divided according to the branch information and is outputted to the switching terminal 15a of the time constant circuit 15 via the inverter 14.

The time constant circuit 15 includes a time constant capacitor C1, a time constant resistor R1, and a switching transistor Q1. One end of the time constant capacitor c1 is connected to a reference potential point, and the other end is connected to the time constant terminal 15b together with one end of the time constant resistor R1. The time constant terminal 15b is x
It is connected to the AGC line and the controlled circuit via the -x' connection line. The switching transistor Q1 operates when the frequency-divided pulse outputted from the programmable counter 13 is input to the pace via the inverter 14 and the switching terminal 15a. Since the collector is connected to the other end of the time constant resistor R1, the bias voltage vb formed by the resistors R3 and R4 charges the time constant capacitor C1 in a charging circuit consisting of the emitter, collector, and resistor R1. The discharge circuit has time constant terminal 15b, x-x' connection 1m
, the collector and emitter of the amplifier transistor ←, the resistor R5, and the reference potential point.

Here, the detection output generated by the AGC detection circuit 7 is AG
It is supplied as a C voltage from the collector of the amplifier transistor Q2 to the AGC line. Since a time constant circuit 15 consisting of a time constant capacitor c1 and a time constant resistor R1 is connected to the AGC line, the level of the AGC voltage is determined according to the time constant characteristics of this time constant circuit 15, and the controlled circuit is controlled. be done. Since the time constant characteristic changes according to the frequency division pulse, an AGC voltage corresponding to the mode can be generated.

In the above-mentioned embodiment, the frequency division Noculus to the switching transistor Q1 is configured to change the period, but the frequency division i
? The width of the loops may be changed at the same time.

The AGC circuit according to the present invention includes a programmable counter that is programmed according to digital lifetime mode selection information, a switching means that operates based on the frequency division pulse outputted from the programmable counter, and a switching means that includes a charging/discharging circuit for a time constant capacitor. Since it has a configuration including a time constant circuit that is switched by , it has the advantage that the time constant characteristic is determined according to the pulse period and width.

Therefore, if the present invention is applied to an AGC circuit of a wireless communication device configured to control a transmitting/receiving circuit using digital control information, the interface between the circuits can be improved and the number of parts can be reduced.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a conventional AGC circuit, and FIG. 2 is a block diagram including a partial circuit diagram showing an embodiment of the AGC circuit according to the present invention. In the figure, 1 is an antenna, 2 is an RF unit, 3 is an intermediate frequency circuit, 4 is an audio circuit, 5 is an operation panel, 6 is a panel integration counter, 7 is an AGC detection circuit, 8-digit time constant circuit, 9 is a mode selection up wholesaler, 1
0 is a down loader for mode selection, 11 is a decoder, 12 is a pulse generation circuit, 13 is a programmable counter, 14 is an inverter, C1 is a time constant capacitor, R1 is a time constant resistor, R2-R5 is a resistor, Ql is a switch Q2 is an amplifier transistor. Patent applicant Yaesu Musen Co., Ltd. Figure 1 Figure 2

Claims (1)

[Claims] 1. The digital mode selection circuit that selects the radio wave type handled by the receiving circuit, the AGC detection circuit that generates the AGC voltage, and the charging and discharging time of the time constant capacitor related to the AGC voltage are output from the digital mode selection circuit. An AGC circuit comprising: a charge/discharge time changing means that changes according to mode selection information; a programmable counter that is programmed according to the mode selection information; and a switching device that operates with a divided pulse output from the programmable counter. and a time constant circuit in which the charging/discharging circuit of the time constant capacitor is switched by the switching means, and is configured to change the operating characteristics of the AGC voltage according to mode selection information. AG to do
C circuit.