JPS6079775A - Ohmic electrode - Google Patents

Ohmic electrode

Info

Publication number
JPS6079775A
JPS6079775A JP58187318A JP18731883A JPS6079775A JP S6079775 A JPS6079775 A JP S6079775A JP 58187318 A JP58187318 A JP 58187318A JP 18731883 A JP18731883 A JP 18731883A JP S6079775 A JPS6079775 A JP S6079775A
Authority
JP
Japan
Prior art keywords
film
electrode
patterns
etched
electrodes
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58187318A
Other languages
Japanese (ja)
Inventor
Yasumasa Imoto
井元 康雅
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP58187318A priority Critical patent/JPS6079775A/en
Publication of JPS6079775A publication Critical patent/JPS6079775A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45Ohmic electrodes
    • H01L29/456Ohmic electrodes on silicon

Abstract

PURPOSE:To form a pattern easily by using Ti, W and Au multilayer film electrodes as high-reliability electrodes for a P type semiconductor. CONSTITUTION:A Ti film 4 and a W film 5 are deposited on the P side 2 of a P-N junction wafer 1 through vacuum deposition, and alkali-resistant resist patterns 6 are formed. The whole is dipped in a KOH aqueous solution 7, and an AC power supply 9 is connected to the W film 5 and a Pt electrode 8 and the W film 5 is etched electrolytically. Only the W film 5 is etched through the etching, and the Ti film 4 is formed according to patterns while using the W film 5 as a mask. A dielectric insulating film 11 consisting of SiO2 or Si3N4 or the like is deposited, patterns are formed, and an Au film 10 is shaped.

Description

【発明の詳細な説明】 本発明は半導体素子のオーム除電極に関する。[Detailed description of the invention] The present invention relates to ohmic removal electrodes for semiconductor devices.

一般に、半導体素子は、電極付近での温度上昇による動
作特性の変化を防ぐために、熱伝導性の良いAu金によ
シミ極最外部層を形成している。
In general, semiconductor devices have a stain-extreme outermost layer made of Au gold, which has good thermal conductivity, in order to prevent changes in operating characteristics due to temperature rise near the electrodes.

特に、発光ダイオード、レーザーダイオードなどのよう
に注入電流密度が高く、温度上昇が著しいものではAu
層を電極最外部に設けることが重要である。ところて”
’、Auは半導体と反応し易いのでAuを半導体素子の
電極として用いる場合には、Auの半導体表面への拡散
を防ぐために、防護層となる金属層を半導体とオーム性
接触のとれる金属層とAu層との間に設けることが素子
の信頼性を向上させる有効である。
In particular, Au
It is important that the layer be placed on the outermost part of the electrode. Tokorote”
', Au easily reacts with semiconductors, so when using Au as an electrode of a semiconductor element, in order to prevent Au from diffusing to the semiconductor surface, the metal layer that will serve as a protective layer should be replaced with a metal layer that can make ohmic contact with the semiconductor. Providing it between the Au layer and the Au layer is effective in improving the reliability of the device.

従来、この防護層用の金属としてPt(白金)が知られ
ており、例えば発光ダイオード、レーザーダイオードの
p側電極として1“i(チタン)、Pi(白金)、Au
多層膜が高信傾オーミック°電極として知られている。
Conventionally, Pt (platinum) has been known as a metal for this protective layer, and for example, 1"i (titanium), Pi (platinum), Au
The multilayer film is known as a highly reliable ohmic electrode.

ところがPtはエツチングが難かしく、電極のパターン
形成が困難であった。そのため”yP!、Au多層膜゛
電極では、電流注入部を制限する場合にはレジストによ
るリフトオフ法、あるいは絶縁膜を半導体表面に部分的
に形成し、次に全面KT 1 、 P t 、 Au多
メノー腟を形成する方法が用いられてきた。しかし、前
者の方法ではフォトレジストによる半導体表面の汚染が
あシ、彼者の方法では絶縁膜の段差部でのT I 、 
P t 、 A u多層膜の切れが原因となってストレ
スによる電極の剥れなどを生じて信頼性が低下するとい
う欠点があった。
However, Pt is difficult to etch, making it difficult to form electrode patterns. Therefore, in the case of the "yP!, Au multilayer film" electrode, when limiting the current injection part, a lift-off method using a resist or an insulating film is partially formed on the semiconductor surface, and then the entire surface is coated with KT 1 , P t , Au multilayer film. A method of forming an agate vagina has been used. However, in the former method, the semiconductor surface is contaminated by the photoresist, and in their method, T I at the step part of the insulating film,
There was a drawback that the reliability was lowered due to stress-induced peeling of the electrode due to the breakage of the Pt, Au multilayer film.

本発明の目的は、仁れらの欠点を除去し、パターン形成
が容易でかつ信頼性が高いオーム性電極を提供すること
にある。
It is an object of the present invention to provide an ohmic electrode that eliminates the drawbacks of the above, is easy to pattern, and is highly reliable.

本発明のオーム性電極は、p型半導体上にチタン(TI
)、タングステンOV)および金(Au )の各層をこ
の順に積層した多層膜構造を有することを特徴とする。
The ohmic electrode of the present invention has titanium (TI) on a p-type semiconductor.
), tungsten OV), and gold (Au) in this order.

次に図面を参照して本発明の詳細な説明する。Next, the present invention will be described in detail with reference to the drawings.

第1図は本発明の一実施例の製造工程を説明する構成図
、第2図は本発明の実施例を含む半導体装置の断面図で
ある。本実施例を製造する場合、まず真空蒸着によJ)
pn接合ウェハー1のp側2にTi膜4及びWJ菖5を
堆積させ、耐アルカリ性レジストパターン6をW膜5上
に形成する。この耐アルカリ性レジストパターン6をマ
スクとして、W膜5とpt電匝8とを電解エツチング電
極としてKOH水溶液7で交流電源9によシ数ボルトの
電圧を印加してW膜5を電解エツチングする。二のv!
屏エツチングではW膜5のみがエツチングされ、pn接
合ウェハー1のp側2はTi膜4によシフ保護されp側
2が直接KOH水溶液7にさらされて侵されことはない
。また、W膜5が不均一に%解エツチングされて島状に
歿ってもTSSi2通じてWjJ5の成屏エツチングし
たい部分を完全に除去することができる。虹に、Tit
lf%4はWi@5をマスクとして弗酸系のエツチング
液によりパターン形成ができる。
FIG. 1 is a block diagram illustrating the manufacturing process of an embodiment of the present invention, and FIG. 2 is a sectional view of a semiconductor device including the embodiment of the present invention. When manufacturing this example, first J)
A Ti film 4 and a WJ iris 5 are deposited on the p side 2 of the pn junction wafer 1, and an alkali-resistant resist pattern 6 is formed on the W film 5. Using this alkali-resistant resist pattern 6 as a mask, the W film 5 is electrolytically etched by applying a voltage of several volts to the AC power supply 9 using the KOH aqueous solution 7 and the W film 5 and the PT cell 8 as electrolytic etching electrodes. Second v!
In the screen etching, only the W film 5 is etched, and the p-side 2 of the p-n junction wafer 1 is protected by the Ti film 4, so that the p-side 2 is not directly exposed to the KOH aqueous solution 7 and corroded. Further, even if the W film 5 is etched non-uniformly and becomes islands, the portion of WjJ5 to be etched can be completely removed through the TSSi2. Rainbow, Tit
lf%4 can be patterned using a hydrofluoric acid etching solution using Wi@5 as a mask.

なお、pn接合ウェハ1のn側3を保1ψする必要があ
るときは耐アルカリ性のレジストで保を虜すればよ(、
KOH水溶液はN a OH水溶液でもよい。
In addition, if it is necessary to protect the n side 3 of the pn junction wafer 1, use an alkali-resistant resist to protect it.
The KOH aqueous solution may be an NaOH aqueous solution.

この方法により、TiP4W膜5のパターン形成を行な
い、第2図に示すように、Sin、又はSi3N4など
から成る誘電体絶縁膜11を堆積し7、パターン形成し
たiAuル410を形成する。々お、Au膜10とρ多
電体絶縁膜11との接着力を強化させる為にAu膜10
と誘電体絶縁膜11との間にCr(クロム)層を設けて
もよい。
By this method, the TiP4W film 5 is patterned, and as shown in FIG. 2, a dielectric insulating film 11 made of Sin or Si3N4 is deposited 7, and a patterned iAu layer 410 is formed. In order to strengthen the adhesion between the Au film 10 and the ρ multi-electric insulating film 11, the Au film 10 is
A Cr (chromium) layer may be provided between the dielectric insulating film 11 and the dielectric insulating film 11 .

本実施・し0の特徴は、従来のp型半−Jフ体の高信頼
゛醒(水であるTi、Pt、Au多層膜電極ではげ1百
であったパターン形成を、T r 、 W、 A t+
多層膜電極を用いることによシ可能にしまたものである
The feature of this implementation is that the pattern formation of the conventional p-type half-J half body (which was 100% unbalanced in the water Ti, Pt, Au multilayer electrode), , A t+
This is also possible by using a multilayer electrode.

このWはptと同様にAuに対する防護効果を持ってい
るので46問性を損なうことケまない。更に、W膜をエ
ツチングする際半導体ウェハーを強アルカリ性のK 0
1J水溶液等にaずが、−極を形成する91則はTI肪
へによシ保護されているン≧め1悦1丞と半導体界面へ
半導体を侵すK O■1水溶液等が浸入することがない
。これは発光ダイオードやレーザーダイオードのように
p側電極の信頼性が素子の信頼携を決める上で重要な場
合特に有用である。
Since this W has a protective effect against Au like PT, it does not impair the 46-question nature. Furthermore, when etching the W film, the semiconductor wafer is exposed to strong alkaline K 0
The 91 rule that az forms a negative pole in a 1J aqueous solution, etc. is protected by the TI fat, and the KO1 aqueous solution, etc., which attacks the semiconductor, invades the semiconductor interface. There is no. This is particularly useful in cases such as light emitting diodes and laser diodes, where the reliability of the p-side electrode is important in determining the reliability of the device.

以上説明したように本発明によれば、p型#!−導体の
高信頼電極としてT i 、W、Au多層膜電極を用い
ることによシ、との゛電極に任意のパターンを形成する
ことが出来る。
As explained above, according to the present invention, p-type #! - By using a Ti, W, Au multilayer film electrode as a highly reliable conductor electrode, it is possible to form an arbitrary pattern on the electrode.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発ゆ」の実施例の製造工程を示す構成図、第
2図は本発明?実施例を含む半導体装置の断面図である
。図において 1・・・・・・pn接合ウェハー、2・・山・p側、3
・・・・・・n側、4・・・・・・Ti膜、5・・・・
・・W膜、6・・・・・・耐アルカリ性レジストパター
ン、7・・・・・・kO)1水溶液、8°゛°°°゛P
t電1迅、9・・・・・・又流゛電源、lO・・・・・
・Au膜、11・・・°・・+;ぢ電体絶縁膜、である
Figure 1 is a configuration diagram showing the manufacturing process of the embodiment of the present invention, and Figure 2 is a diagram showing the manufacturing process of the embodiment of the present invention. 1 is a cross-sectional view of a semiconductor device including an example. In the figure, 1...pn junction wafer, 2...mountain/p side, 3
......n side, 4...Ti film, 5...
... W film, 6... Alkali-resistant resist pattern, 7... kO) 1 aqueous solution, 8°゛°°°゛P
t Electric power 1 speed, 9... Also, flow power, lO...
・Au film, 11...°...+; dielectric insulating film.

Claims (1)

【特許請求の範囲】[Claims] p型半導体上にチタン、タングステンおよび金の各層を
この順に積層した多層膜構造を有することを%徴とする
オーム性電極。
An ohmic electrode characterized by having a multilayer structure in which titanium, tungsten, and gold layers are laminated in this order on a p-type semiconductor.
JP58187318A 1983-10-06 1983-10-06 Ohmic electrode Pending JPS6079775A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58187318A JPS6079775A (en) 1983-10-06 1983-10-06 Ohmic electrode

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58187318A JPS6079775A (en) 1983-10-06 1983-10-06 Ohmic electrode

Publications (1)

Publication Number Publication Date
JPS6079775A true JPS6079775A (en) 1985-05-07

Family

ID=16203903

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58187318A Pending JPS6079775A (en) 1983-10-06 1983-10-06 Ohmic electrode

Country Status (1)

Country Link
JP (1) JPS6079775A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20190028509A (en) * 2016-08-01 2019-03-18 가부시키가이샤 니혼 마이크로닉스 Secondary battery

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20190028509A (en) * 2016-08-01 2019-03-18 가부시키가이샤 니혼 마이크로닉스 Secondary battery
US10991933B2 (en) 2016-08-01 2021-04-27 Kabushiki Kaisha Nihon Micronics Secondary battery

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