JPS6079393A - Matrix multiplication circuit for graphic display - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

TECHNICAL FIELD The present invention relates to a matrix arithmetic circuit suitable for graphic displays.

(Prior Art) As shown in FIG. 1, a graphic display uses a matrix multiplier circuit C to enlarge, reduce, and enlarge graphic data transferred from a host computer A using a matrix multiplication circuit C in response to commands from an input device B such as a keyboard. Performs calculations for rotation, perspective transformation, and parallel translation, verifies that the clipping circuit does not protrude from the display area, and displays the window.
This is a device that converts data into coordinate values on a display screen using viewport conversion, generates data for interpolating between coordinate points using a straight line generation circuit E, stores the generated data in an image memory F, and then displays the data on a cathode ray tube G.

In this apparatus, when converting from figure Kl to figure 2 as shown in FIG. 2, it is necessary to perform conversion for one rotation and parallel movement.

That is, if the rotation transformation matrix is R1 and the translation transformation matrix is P, then affine transformation, that is, = [x,:', y;', , +, l matrix operations are performed on each coordinate point vO1V that constitutes 1 in the figure.
1 and V2 respectively.

This calculation first multiplies the rotation transformation matrix R and the translation transformation matrix P, or R×P, to obtain the transformation matrix W, and then this transformation matrix W and the coordinate data [x i , y i , zi , l].

By the way, normally, the data length of the rotation transformation matrix R and the pasting 11 movement transformation matrix P is 64 bits, so in the first calculation process described above, the data length is 64 bits x 64 bits.
Bit multiplication is performed and the solution is shortened to 64 bits by digit processing, and since it is a bit, a 64 bit x 32 bit multiplication is performed in the second calculation step.

Conventionally, these operations were performed using a 64-bit serial multiplier, so in order to multiply the transformation matrix W by the coordinate data (x, y, z, 1), 32 bits of zeros were added to the upper part of the coordinate data. By adding , the data is extended to 64 bits and the data length of the multiplicand and the multiplier are made equal, and 64 bits are added.
Multiplication was performed as data between bits.

Therefore, the respective effective data lengths are 32 bits and 64 bits.
Bit multiplication, in other words, even though the data length to be handled is 96 bits, 128 shift clocks are used for one operation, and an extra 32 bits of clocks are required, resulting in a large number of operations between the conversion matrix W and coordinate data. There was a problem that wasted time was generated in the calculation, which hindered high-speed processing.

(Objective) In view of such problems, the present invention shortens the calculation time for coordinate data and transformation matrix data by changing the beat configuration of the serial multiplier according to the bit length of the multiplicand. An object of the present invention is to provide a matrix multiplication circuit that can process image data at high speed.

(Structure

FIG. 3 is a block diagram of an apparatus showing an embodiment of the present invention, in which reference symbol l represents 16 matrix elements Un.
...A matrix storage memory that stores U4+, and is configured to output each element U11 of the matrix simultaneously in serial format starting from the lowest bit in response to the clock signal from counter 2. . A and B are multiplication circuits forming a set, which are characteristic parts of the present invention, and each set can be connected in cascade based on the input from the multiplexer controller 3, or can be used independently. IN serial multipliers 5a to 5d, 5e to 5h, 51 to 5, 5m
Adders 4a and 4b that add the respective outputs to 5p to 5p
and 4C14d.

FIGS. 4(a) and 4(b) are block diagrams of a device showing an embodiment of the multiplication circuits of the above-mentioned sets A and H, respectively,
Reference symbols 5a to 5h and 51 to 5P in the figure are 32-bit serial multipliers each having a cascade input terminal, a serial format input terminal Y, and a serial output terminal S. The first one has 2 input terminals, 1 select signal input terminal, and 1 output terminal.
multiplexers 6a to 6p, and the serial format input terminal Y has 2 input terminals, 1 select signal input terminal, and l
Second multiplexers 7a to 7p having output terminals are connected. This first multiplexer has one input terminal 9 grounded and the other input terminal connected to the output terminals of the other group of the same set, so that the two multipliers can be connected in cascade 64. In the second multiplexer, in the first set A, the first column Uu...LJ++ from the matrix storage memory 1 and each element of the matrix in the second column are connected so that a bit multiplicand can be handled. UIZ...U4L, and in the second group B, the third column U13...U43 and the fourth column U14...U
Each element matrix of @ is input, and for each set, one of the matrix elements in one column is selected and output. 8 is a shift counter to which a clock signal from a clock signal source, a shift number setting signal from a data bus 9, and a signal from an ant game 1-10, which will be described later, are input, and a shift number setting signal is input after inputting a start signal. Then, the device is configured to output Enable I and No. J until the set number of clock signals are output. Reference numeral 1o is the analog game 1 described above, which is configured to output a shift clock only during the period when the enable signal from the shift counter 8 is output. In addition,
Reference symbols 11a to 5i 11d in the figure represent adders 4, respectively.
This shows a 64-bit shift I register that temporarily stores the outputs from a to 4d.

Next, the operation of the device configured in this way will be explained based on the timing diagrams shown in FIGS. 5 and 6, taking as an example the case of converting from graphic 1 to graphic 2 (FIG. 2). .

As described above, prior to graphic conversion, multiplication between conversion matrices, 64 bits x 64 bits, is performed.

Therefore, when the load instruction is executed (FIG. 5), half of the data of the rotation transformation matrix H is output via the data bus 9, and the first group Gl of the first set A is filled with the elements constituting the first row. In other words, the multiplier 5a has the upper 32 bits of the element Ru in the first row and the first column, the multiplier 5b has the element RIZ in the first row and the second column, and the multiplier 5d has the element Ru in the first row. The element R1+ in the fourth column is placed as a multiplicand, and the lower 32 bits of the elements R+1, .

On the other hand, each multiplier 51 of the first group G3 of the second introduction B
...5KL has the element RB that forms the first row.
R1 contains the current upper 32 bits, and the second group G4 contains the lower 3 of the elements R+1...R14 that make up the first row.
2 hints are placed. When this loading is finished,
multiplexer controller) 3 to operate the multiplexers 6a to 6d and 7a of the first group G1 of the first set A.
~7d connects terminal A, second group multiplexers 6e~6h and 7e~7h connect terminal B, and second group first group G3 multiplexers 61~6 and 71
-7 sentences select terminal A, and multiplexers 6m-6p and 7m-7p of the second group G4 select terminal B.

That is, as shown in FIG. 7(a), the first group and second group of multipliers in each set are connected in cascade, and 6
A 4-bi, I-multiplier is formed and data of 64 hints is set as a multiplicand. At this time, when a clock pulse is input to the matrix storage memory l via the counter 2, the first set A multipliers 5a to 5h contain the elements of the first column of the translation transformation matrix P, that is, pH is output to the cascade-connected multipliers 5a and 5e, P4+ is simultaneously output from the least significant bit to the multipliers 5d and 5h, and R11X Fil is output from the multiplier 5e in synchronization with the shift clock pulse. RIZ X PZ from vessel 5f
I..., R14X P41 is output from the multiplier 5h, and the first row, first
Column element R++ ” P11+ R12・PZI +R
13・PB+ "R+4" Output P41. Also, in the second introduction B, the elements of the third column, that is, PI3 for multipliers 51 and 5m, and P3 for multiplier 5 and 5p.
are simultaneously output from the least significant bit, and the elements RII 11 PI3 + RIL in the first row and third column are output from the adder 4d.
Conflict Pz3 + R13II P33 + R) Now I
IP43 outputs. Each of these outputs is connected to a shift register llb connected to each adder 4b, 4d,
The data is subjected to digit processing by lid, rounded to predetermined bits, for example, the upper 64 bits, and stored in the matrix storage memory 1. Next, the second multiplexers 7a to 7p connected to all the multipliers 5a to 5p are switched, and as shown in FIG. Further, in the second introduction B, each element in the fourth column is output as a multiplier, and the same calculation is performed.

In this way, the row elements of the parallel translation transformation matrix are changed.By repeating the two series of calculation processes 8 times, the calculation of all the elements of the transformation matrix W is completed, and this is stored in the matrix storage memory 1. be done.

Once the conversion matrix W is stored in the memory, the multiplexer controller 3 is operated to select the terminal A by all the first and second multiplexers 6a to 6P and 7a to 7p, as shown in FIG. The cascade terminal K of each multiplier is grounded to form an independent 32-bit multiplier, and at the same time, each multiplication 'a5 a to 5d of the first group G1 of the first set A is The elements Wll to W+4 in one row are placed in the second group G2.
The elements W, l to Wz4 in the rows, and the elements W? in the third and fourth rows in the groups G3 and G4 of the second set B, respectively. 1
~W Ha, w4. - Create a state where W4% can be input. If a load instruction is executed at this point (FIG. 6), the first multiplier 5a of each group.

5e, 5i, and 5m have X coordinate data, and the second multiplier 5
b, 5f, 5'j, 5n have y-coordinate data, third multiplier 5C15g, 5, 5o has 2-coordinate data, fourth
1 is placed in the multipliers 5d, 5h, 5p, and 5p.

In such a state jlX, when a clock pulse is input to the matrix storage memory l via the counter 2, the matrix elements are input from the least significant bit to the multipliers 5a to 5p.
Data about one coordinate point [X] is output from adders 4a to 4d at the 96th clock corresponding to the bit length of the transformation matrix W and the coordinate data.

y, z, 1] is output. In this way, each point vO1v
Affine transformation can be performed without wasting time by sequentially inputting the coordinate data of 1, .

(Effects) As explained above, according to the present invention, two multipliers are paired and can operate in a cascade connection or independently depending on the data length of the multiplicand. It does not require any extra locks for short calculations, and the multiplication between the transformation matrix and coordinate data, which accounts for most of the calculations in affine transformation, can be performed at high speed, which is the most important drawing speed for graphic displays. can be improved.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a device showing an example of a graphic display, FIG. 2 is an explanatory diagram showing an example of graphic conversion, and FIG. 3 is a block diagram of a device showing an example of graphic display. Figures 4a and 4b are block diagrams showing one embodiment of the multiplication circuit of the above device, Figures 55 and 6 are timing diagrams showing the operation of the same device, and Figures 7a, b and FIG. 8 is an explanatory diagram showing connection types 1d:i with the above device, respectively. Applicant Seiko Electronics Co., Ltd. Agent J “Built-in earth Keiji Nishikawa Katsuhiko Kimura Figure 7 (Cl) Figure 7 Cb)

Claims (1)

[Claims] A serial multiplication means in which a multiplicand is inputted via a data bus, serially inputting the multiplier one by one and performing multiplication, a multilinks storage means for storing and serially reading out the multiplier, and a multiplier for storing and serially reading out the multiplier. In a matrix multiplication circuit equipped with an addition means for adding the outputs from and converting them into matrix data, [No. 10 Serial multiplication means is set to the pitch I/length of the coordinate data, and the multiplication 111, H between the conversion matrices is performed. A matrix 7 power 9 circuit for a graphic display, characterized in that the matrix 7-9 circuits are connected in pairs to form a cascade, and are provided with synchronization means for making each one independent when multiplying a transformation matrix and coordinate data.