JPS6078361A - Pulse signal measuring device - Google Patents

Pulse signal measuring device

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Publication number
JPS6078361A
JPS6078361A JP18650183A JP18650183A JPS6078361A JP S6078361 A JPS6078361 A JP S6078361A JP 18650183 A JP18650183 A JP 18650183A JP 18650183 A JP18650183 A JP 18650183A JP S6078361 A JPS6078361 A JP S6078361A
Authority
JP
Japan
Prior art keywords
input waveform
waveform
pulse
level
measuring device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18650183A
Other languages
Japanese (ja)
Inventor
Masaji Soma
相馬 正次
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP18650183A priority Critical patent/JPS6078361A/en
Publication of JPS6078361A publication Critical patent/JPS6078361A/en
Pending legal-status Critical Current

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  • Measuring Frequencies, Analyzing Spectra (AREA)
  • Radar Systems Or Details Thereof (AREA)

Abstract

PURPOSE:To measure accurately a pulse width and a frequency by providing counters which measure high and low levels of an input waveform individually. CONSTITUTION:When the input waveform is in the high level, the number of clocks from a reference oscillator 1 is counted by a counter (CT)8a, and the value of the CT8a is loaded to a register (RG)10a when the operation of a CT8b is started. When the input waveform is in the low level, the number of clocks is counted by the CT8b, and the value of the CT8b is loaded to an RG10b when the CR8a is operated. A central operation processing part 12 sends high-level data from the RG10a to a memory part 13 during measurement of the low level and sends low-level data from the RG10b to the memory part 13 during measurement of the high level.

Description

【発明の詳細な説明】 [発明の技術分野] この発明は、不規則に変化するパルス信号のパルス幅と
周波数を測定するためのランダム信号に対するパルス信
号測定装置に関するものである。
DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a pulse signal measuring device for random signals for measuring the pulse width and frequency of irregularly changing pulse signals.

[従来技術] パルス・ドプラーレーダ装置は、目標(ターゲット)ま
での距離によって最適な送信出力のパルス幅2周期を決
めている。
[Prior Art] A pulse Doppler radar device determines the optimum pulse width of two periods of the transmission output depending on the distance to the target.

従って目標(ターゲット)までの距離が変化すると送信
出力のパルス幅9周期も変化する。このようなパルス・
ドプラーレーダ装置の能力評価の上でも、送信出力のパ
ルス幅9周期の変化方法を知る必要があった。
Therefore, when the distance to the target changes, the pulse width of the transmission output (9 cycles) also changes. Such a pulse
In order to evaluate the performance of the Doppler radar system, it was necessary to know how to change the nine-cycle pulse width of the transmission output.

従来、この種の信号を測定する器材として第1図に示す
ものがあった。
Conventionally, there has been an instrument shown in FIG. 1 for measuring this type of signal.

図において、(1)は基本クロックを発生する基準発振
器、(2)は基準発振器+11の基本クロックな分周器
で分周し、10秒、1秒、0.1秒などのゲートを開閉
する基準時間発生部、(3)は測定期間を制御するゲー
ト制御部、(4)は波形整形された入力信号から基準時
間内の信号のみを通過されるメインゲ−) 、 (5)
は入力信号波形のレベルを調整するアッテネータ、(6
)は入力信号波形のパルス整形回路。
In the figure, (1) is the reference oscillator that generates the basic clock, and (2) is the reference oscillator + 11 basic clock frequency divider, which opens and closes gates of 10 seconds, 1 second, 0.1 seconds, etc. (3) is a gate control unit that controls the measurement period; (4) is a main gate that passes only signals within the reference time from the waveform-shaped input signal; (5)
is an attenuator that adjusts the level of the input signal waveform, (6
) is a pulse shaping circuit for input signal waveform.

(7)はパルス整形回路(6)で波形整形した信号をメ
インゲート(4)でゲート化された波形のパルス幅9周
波数を計算し9表示する計測・表示部である。
(7) is a measurement/display unit that calculates and displays 9 pulse widths and 9 frequencies of the gated waveform of the signal waveform-shaped by the pulse shaping circuit (6) at the main gate (4).

次に動作について、各ポイン) (a)〜(d)の状態
を示す第2図を用いて説明する。第2図(a)の波形は
Next, the operation will be explained using FIG. 2 showing the states of each point (a) to (d). The waveform in Fig. 2(a) is.

基準発(辰器(1)より発生する基本クロックを示し。This shows the basic clock generated from the reference clock (Tatsuki (1)).

同図(b)は、入力波形を波形整形した波形である。FIG. 4B shows a waveform obtained by shaping the input waveform.

また同図(C)は、基準時間発生部(2)より指定され
た時間のゲート信号であり、(d)は波形整形されたパ
ルス波形(b)をゲート信号(c)でゲート化した計測
波形である。
In addition, (C) in the same figure is a gate signal at the time specified by the reference time generator (2), and (d) is a measurement in which the waveform-shaped pulse waveform (b) is gated with the gate signal (c). It is a waveform.

計測波形(a)は、計?1lt1−表示部(7)で、計
測波形(d)のパルス数nを数え、基準時間のゲート信
号(Q)のゲート巾tより。
Is the measured waveform (a) a total? 1lt1 - Count the number of pulses n of the measurement waveform (d) on the display section (7) and use the gate width t of the gate signal (Q) at the reference time.

f=0/l ・・・・・・・・・・・・・・・ (1)
で得られた周波数を計測・表示部に表示する。
f=0/l ・・・・・・・・・・・・・・・ (1)
The frequency obtained is displayed on the measurement/display section.

従来のパルス信号測定装置は、(1)式で示すごとく、
基準時間(1)で平均しているため、基準時間(t)内
でパルス巾9周期が変化してもその変化が計測[発明の
概要] この発明は、かかる欠点を改善する目的でなされたもの
で、入力波形がランダムに変化したとしても、パルス幅
を測定する回路と2次のパルス幅が立ち上がるまでの時
間を測定する回路を別々に付加し、計算機でそれらのデ
ータを読み取ることにより、正確にパルス幅9周波数を
測定するパルス信号測定装置を提供するものである。
The conventional pulse signal measurement device has the following equation, as shown in equation (1):
Since it is averaged over the reference time (1), even if the pulse width changes in 9 cycles within the reference time (t), the change is measured. Even if the input waveform changes randomly, by adding a separate circuit to measure the pulse width and a circuit to measure the time until the secondary pulse width rises, and reading those data with a computer, The present invention provides a pulse signal measuring device that accurately measures pulse width and nine frequencies.

[発明の実施例コ 以下9図面に従ってこの発明の一実施例について詳述す
る。第3図は、この発明のパルス信号測定装置、第4図
は、第3図の各ポイントにおけるタイミング図であり9
図において、(1)は基本クロックを発生する基準発振
器、 (8a)〜(8b)は、入力波形のHlgh 、
 Lowレベルの期間を測定するカウンター。
[Embodiment of the Invention] An embodiment of the invention will be described in detail below with reference to nine drawings. 3 is a pulse signal measuring device of the present invention, and FIG. 4 is a timing diagram at each point in FIG. 9.
In the figure, (1) is a reference oscillator that generates a basic clock, (8a) to (8b) are input waveform Hlgh,
A counter that measures the period of low level.

(9a)〜(9c)は、 Hlgh 、 LOWレベル
の測定期間終了タイミングを発生する測定制御回路、 
(10a)〜(1ab)は、カウンター(8a)〜(8
b)で測定した値を測定終了回路(9a)〜(9b)の
タイミングでロードし、保持するレジスタ、0υは計測
プログラムが格納されているプログラムメモリ部、(1
2はレジスタ(10a)〜(10b)のデータより周波
数等を演算・制御する中央演算処理部、(+3は中央演
算処理部f+3で測定・演算されたデータを保持するた
めのデータメモリ部(14a) 〜(’+ 4b)は、
レジスタ(I Da) 〜(10b)で保持されたデー
タを中央演算処理部a邊に読み込むためのバッファー、
 I+5m 、どちらのバッファー(14a)〜(14
b)を中央演算処理部(12に読み込ますかを制御する
デコーダ、である。
(9a) to (9c) are Hlgh, a measurement control circuit that generates a LOW level measurement period end timing;
(10a) to (1ab) are counters (8a) to (8
The value measured in step b) is loaded and held at the timing of the measurement end circuits (9a) to (9b), and 0υ is the program memory section where the measurement program is stored.
2 is a central processing unit that calculates and controls frequencies etc. from the data in registers (10a) to (10b); (+3 is a data memory unit (14a) that holds data measured and calculated by the central processing unit f+3; ) ~('+4b) is
A buffer for reading data held in registers (I Da) to (10b) into the central processing unit a;
I+5m, which buffers (14a) to (14
b) is a decoder that controls whether to read the data into the central processing unit (12).

次に動作について、第3図に示すブロック図の各ポイン
トのタイミング波形(イ)〜(ト)を第、4図に示し、
詳述する。第4図の波形(イ)は、基本発振器+11で
発生する基本クロックである。波形(ロ)は波形整形さ
れた入力波形であり、入力波形がT(ighレベルの時
、波形(ハ)が示すクロックの数をカウンター(8a)
で数え、カウンター(8b)が動作し始めた時。
Next, regarding the operation, timing waveforms (A) to (G) at each point in the block diagram shown in FIG. 3 are shown in FIGS.
Explain in detail. The waveform (a) in FIG. 4 is the basic clock generated by the basic oscillator +11. The waveform (b) is the input waveform that has been shaped, and when the input waveform is at T (high level), the number of clocks indicated by the waveform (c) is counted by the counter (8a).
When the counter (8b) starts operating.

波形(ト)の立上りで、カウンター(8a)の値をレジ
スタ(9a)にロードすると同時にカウンター(8a)
に“θ″をロードし、中央演算処理部+12に入力波形
H1ghレベル測定終了を知らせる。
At the rising edge of the waveform (G), the value of the counter (8a) is loaded into the register (9a), and at the same time the counter (8a)
"θ" is loaded into the central processing unit +12 to notify the end of input waveform H1gh level measurement.

次に入力波形のLOwレベルを測定するため、測定・制
御回路(9C)で反転された波形(ホ)のH1ghレベ
ルのクロック数を測定する。このLOWレベル叫定中に
H1ghレベルデータをプログラムメモリ部(lυで制
御されでいる中央演算処理部r112がデコーダttS
に命令してレジスタ(IQa)の内容をバッファー(1
4a)よりデータメモリ一部113に収納する。
Next, in order to measure the LOW level of the input waveform, the measurement/control circuit (9C) measures the number of clocks of the H1gh level of the inverted waveform (E). During this LOW level determination, the central processing unit r112, which is controlled by the program memory unit (lυ), transfers the H1gh level data to the decoder ttS.
The contents of the register (IQa) are transferred to the buffer (1
4a), the data is stored in the data memory part 113.

H1ghレベルの測定と同様に、 Lowレベルの測定
においても、(へ)に示すごとく、(ホ)のH1ghレ
ベルにおけるクロックの数だけ、カウンター(8b)で
数え、カウンター(8a)が動作し始めた時、に)の波
形がカウンター(8b)の1直をレジスタ(10b)に
ロードし9次の入力波形のIJOWレベル測定のために
カウンター(10b)に“0”をロードし、中央演算処
理部112に入力波形Lowレベル測定終了を知らせる
As in the measurement of the H1gh level, in the measurement of the Low level, as shown in (f), the counter (8b) counts the number of clocks at the H1gh level in (e), and then the counter (8a) starts operating. When the waveform of (in) is loaded, the 1st shift of the counter (8b) is loaded into the register (10b), "0" is loaded into the counter (10b) to measure the IJOW level of the 9th order input waveform, and the central processing unit 112 is notified of the end of input waveform low level measurement.

本Lovrレベル測定データは、 H1ghレベル測定
データと同様に、 Highレベル測定中にLowレベ
ル測定データをプログラムメモリ部(11)で制御され
ている中央演算処理部(1カがデコーダ(1りに命令し
てレジスタ(1ob)の内容をバッファー(14b)よ
りデータメモリ部(13に収納する。
Similar to the H1gh level measurement data, this Lovr level measurement data is processed by processing the Low level measurement data during the High level measurement using a central processing unit (one unit is a decoder) controlled by the program memory unit (11). Then, the contents of the register (1ob) are stored in the data memory section (13) from the buffer (14b).

またプログラムメモリ部口])のプログラムを変更する
ことによって全ての入力波形特性を記憶するか、異った
パルス幅1周波数等のみ記憶するかを容易に変更出来る
Furthermore, by changing the program in the program memory section, it is possible to easily change whether all input waveform characteristics are to be stored or whether only a different pulse width, one frequency, etc. are to be stored.

[発明の効果] 以上のようIC,この発明に係るパルス信号測定装置で
は、入力波形のH1ghレベルを測定中、 Lowレベ
ルデータを処理し、 Lowレベルを測定中。
[Effects of the Invention] As described above, in the IC and the pulse signal measuring device according to the present invention, while measuring the H1gh level of the input waveform, processing the Low level data and measuring the Low level.

H1ghレベルデータを処理することによって、入力波
形がランダムに変化しても、パルス幅2周波数を測定す
ることが出来る効果がある。
By processing the H1gh level data, it is possible to measure the pulse width and frequency even if the input waveform changes randomly.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は、従来のパルス信号測定装置を示すブロック図
、第2図は、第1図の各ポイントにおけるタイミング図
、第3図は、この発明のパルス信号測定装置を示すブロ
ック図、第4図は、第3図の各ポイントにおけるタイミ
ング図である。 図において、(1)は基準発振器、(2)は基準時間発
生部、(3)はゲート制御部、(4)はメインゲート、
(5)はアッテネータ、(6)はパルス整形回路、(7
)は計測・表示部1 (8a) 、 (8b)はカウン
ター(9a) 、 (9b) 、 (9c)は測定制御
回路、 (10a) 、 (10b)はレジスタ、(n
)はプログラムメモリ部、(12は中央演算処理部、峙
はデータメモリ部、 (14a) 、 (14b)はバ
ッファー、(1つはデコーダである。 なお9図中同一あるいは、相当部分には同一符号を付し
て示しである。 代理人大岩増雄
FIG. 1 is a block diagram showing a conventional pulse signal measuring device, FIG. 2 is a timing diagram at each point in FIG. 1, FIG. 3 is a block diagram showing a pulse signal measuring device of the present invention, and FIG. The figure is a timing diagram at each point in FIG. 3. In the figure, (1) is a reference oscillator, (2) is a reference time generator, (3) is a gate control unit, (4) is a main gate,
(5) is an attenuator, (6) is a pulse shaping circuit, (7
) is the measurement/display unit 1 (8a), (8b) is the counter (9a), (9b), (9c) is the measurement control circuit, (10a), (10b) is the register, (n
) is a program memory section, (12 is a central processing unit, opposite is a data memory section, (14a) and (14b) are buffers, and (1 is a decoder.) Note that the same or equivalent parts in Figure 9 are the same. It is indicated with a code. Agent Masuo Oiwa

Claims (1)

【特許請求の範囲】[Claims] 基本時間としての基準発振器と、所定の測定時間を発生
する基準時間発生部と、入力波形をパルス化するパルス
整形回路と、上記測定時間内のみパルス波形を通過する
メインゲートと、そのメインゲートを通過したパルスよ
り入力波形のパルス幅9周波数を計測・表示する計測・
表示部とから構成され、上記入力波形のパルス幅1周波
数を測定するパルス信号測定装置において、上記入力波
形のハイ(High)+ロー(LOW)レベルを別々に
計測するカウンターを設け、それによって、上記入力波
形がランダムに変化しても上記入力波形のパルス幅、お
よび周波数が測定出来るようにしたことを特徴とするパ
ルス信号測定装置。
A reference oscillator as a basic time, a reference time generator that generates a predetermined measurement time, a pulse shaping circuit that converts the input waveform into pulses, a main gate that passes the pulse waveform only during the measurement time, and the main gate. Measurement and display that measure and display the pulse width and 9 frequencies of the input waveform from the passed pulses.
In the pulse signal measuring device that measures the pulse width and one frequency of the input waveform, the pulse signal measuring device is configured to include a display section and a counter that separately measures the high and low levels of the input waveform, thereby: A pulse signal measuring device characterized in that the pulse width and frequency of the input waveform can be measured even if the input waveform changes randomly.
JP18650183A 1983-10-05 1983-10-05 Pulse signal measuring device Pending JPS6078361A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18650183A JPS6078361A (en) 1983-10-05 1983-10-05 Pulse signal measuring device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18650183A JPS6078361A (en) 1983-10-05 1983-10-05 Pulse signal measuring device

Publications (1)

Publication Number Publication Date
JPS6078361A true JPS6078361A (en) 1985-05-04

Family

ID=16189592

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18650183A Pending JPS6078361A (en) 1983-10-05 1983-10-05 Pulse signal measuring device

Country Status (1)

Country Link
JP (1) JPS6078361A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0332835U (en) * 1989-07-31 1991-03-29
KR100455733B1 (en) * 1997-11-15 2004-12-17 주식회사 하이닉스반도체 Pulse width dividing cycle detection circuit for accurately detecting pulse width of section where two or more signals are overlapped

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0332835U (en) * 1989-07-31 1991-03-29
KR100455733B1 (en) * 1997-11-15 2004-12-17 주식회사 하이닉스반도체 Pulse width dividing cycle detection circuit for accurately detecting pulse width of section where two or more signals are overlapped

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