SU1451640A2 - Device for measuring delay time - Google Patents

Abstract

The invention relates to a pulse technique and can be used to measure the delay time of the gating signals of the nanosecond range and is an additional to the as. No. 1000999. The purpose of the invention is to improve the measurement accuracy. In the device for measuring the delay time, the target is achieved by the introduction of an AND block. The device also contains a controlled pulse generator 1, a pulse generator 2, a time shift formation unit 3, a delay time extension unit 4, a time interval formation unit 5, an information processing and recording unit 6, a coincidence unit 7, a control unit 8, a signal generation unit 9 , the investigated element 10. 3 Il. S (L 01 and 14)

Description

The invention relates to a pulse technique and can be used to measure the delay time of signals for nanosecond stroking; P1 of one range. -

Aim-1: zobrgteni - increase measurement accuracy.

Fig. 1 is a block diagram of a device for measuring silicon tip; FIG. 2 timing charts explaining the operation of the device for measuring the delay time | FIG. FIG. 3 shows the block of the tracking unit and the block coinciding 1 °

Time measuring device

The delays (Fig. 1) contain an ihvravl-hapertor of 1mpulsosis, a generator of 2 pulses, a time shift shaping unit 3, a delay time extension unit 4, a time interval shaping unit 5, a processing and recording information block b block 7 coincidence block 3 8, control j, signal generation unit 9., Probe element 10 and tracking unit 11.

The output of the controlled generator I is connected to the combined first inputs of blocks 3. 7 and 11, 1 output of the generator 2 is connected to the combined second inputs of blocks 3, 7 and 1 and the clock input of the processing and recording unit 6 of information S control input which is connected to the output of the time interval formation unit 5 and the resolution input of the control unit 8 yn-t; the output of which is connected to the reset inputs of the formation unit 3 for the time shift of the unit 4 for extension of the delay time of the signal generation unit 9 and the information input of which is connected to the output of the element under study 10 whose inputs are connected to the outputs of the shapers of the input signal and the strobe signal of block 9e; the directing input of which is connected to the first output of block 3 and the first 4 input of block 4 ,, the second the input of which is connected to the second output of the block 3 by the input of the following blocks: block 9, the output of the coincidence unit 7 is connected to the start input of the block 8 by a third input of the tracking unit 11 whose output is connected to the third input of the coincidence block 7

The coincidence block 7 contains an AND-flip-flop 12 and an element K 13, the output of which is connected to the R-input of the flip-flop 12,

The C and D inputs of which are the first and second inputs of the joint block 7, the direct output of the D flip-flop 12 is the output of the block 7, the third input of which is connected to the first input of the AND element 13, the second input of which is connected to inverse output of D-flip-flop 12.

The tracking unit 11 (FIG. 3) contains an inverter 14 and a D-flip-flop 5, the D- and C inputs of which are respectively the first and second inputs of the block whose third input is the input of the inverter 14, the output of which is connected to the R-input of the D-trigger - IS, whose direct output is the output of the tracking unit 11.

The control generator 1 pulses is implemented in the form of a crystal oscillator with a smooth frequency control. The time shift shaping unit 3 contains two independent binary counters and a resolution trigger, the delay time extension unit 4 consists of two HesaBHCtmbix binary counters. The time interval shaping unit 5 is designed as a trigger 5 forming a direct carbon pulse 3 whose beginning coincides with the front Z edge of the pulse. at the first exit, de block 4, the extension of the delay time 5 and the end with the leading edge of the tf pulse at the second output of the same block. The information processing and recording unit 6 contains a binary | practical counter G, a buffer register, elements of the decoders and an indicator for visually observing the value of the measured delay time and the state of the output information of the element 10 being examined.

The control unit 8 contains a resolution trigger and a stop element. The signal shaping unit 9 is designed as a gating signal generator with a steep peer, a front edge — TOMj of a signal maker with a small internal-4 matching signal, and a steep front edge and an element of the Shv-forts signal;

The device for measuring time is delayed and operates as follows. A smooth frequency adjustment allows setting the frequency of the signal of the controlled pulse generator equal to or less than the frequency of the signal following the output of the pulse generator 2. In this case, the maximum difference between the periods of these signals is several times smaller than the magnitude of the periods of these signals. The rectangular pulses from the outputs of the controlled generator 1 and generator 2 are fed to the first and second inputs of the tracking unit 11 and the matching unit 7, respectively.

When the leading edges of the generators 1 and 2 coincide, the coincidence unit 7 generates a start signal, which is fed to the start input of block 8. The front edge of this signal generates a control signal for the stop circuit of control unit 8, and the rear edge sets the enable trigger of the control unit to the lock state further passage of the start signal to the input of the stop element of the control unit 8. The control signal at the output of control block 8, formed by the stop element of this block, sets in zero states the counters of the time shift formation unit 3, the delay time extension unit 4, the information processing and recording unit 6, translates the stop element of the signal generation unit 9 into the descending mode and sets the trigger for enabling the time shifting block 3 to the open state, allowing the passage of pulses from the output, 5 ° to one side, the moment of coincidence

 The match determined by block 7 of the match is not characterized by hysteresis and ut.

O o at the moment the block

generates a start signal, after

The outputs of the controlled generator 1 and generator 2 are fed to the inputs of binary counters of the same block 3, in which the number of roll counting pulses is equal to N. If T is the period of the signal of which block 11 is set to the waiting pulse generator 2, and Tc mode, a-block 7 - in blocking mode, + ftt is the period of the controlled signal.

The expression (1) can be written in the time of 45 LT, N (Tc + & t) - N-Tp (2)

The pulses from the outputs of block 3 are fed to the block 9 of signal generation, where the input signal and gQ gating signal with steep leading edges are formed for the test element 10, the time shift between which is equal to 4T, after which the signal formation stop element

pulse generator 1, then the time shift between the beginning of the pulses at the outputs of the block 3 of the formation of a time shift after the meters are completely filled

dhh () & t.

(one)

where At is the increment of the period of the signal of the generator I after its adjustment;

ujt is the hysteresis of the coincidence of the leading edges of the pulses of the generators 1 and 2 .. To cancel the term At in expression (1), an DI tracking unit is used, the output signal of which

block 9 is transferred to the closed state, which prohibits further passage of pulses from the outputs of block 3 to form a time shift to the signal conditioners of block 9. The signals generated are fed to 1451640

controls the start-up blocking of the coincidence unit 7. Fig. 2 shows that the time interval between the leading edges of the signals of the generators 1 (Fig. 2a) and 2 (Fig. 26) periodically decreases, i.e. there is a periodic approximation in time of the leading fronts (intervals ut ,, & t, j,

  2). The tracking unit 11 determines the time t. (Fig.26), in which. the leading edge of the signal of the generator 2 coincides with a high logical level of the signal of the generator

J. After the fadement of the moment t. block 1} is set to blocking mode. In this case, the leading edge of the signal from the generator 1 coincides with the low logical level of the generator signal

Pa 2. The indicated coincidence (Fig. 2b) continues until time point t.

CO oP U

determining the coincidence of the leading edges of the signals of the generators I and 2. Therefore, the AND block of the tracking determines the time t, after which the leading edge of the signal of the generator I approaches the leading edge of the signal of the generator 2. At time t, the output 11 produces a high logic level starting block 7 matches. Since after the time tc, the leading edges of the signals of the generators 1 and 2 approach fipyr to the friend by the emitter and ut.

O o at the moment the block

generates a start signal, after

which block 11 is set to standby mode, and block 7 is set to block mode.,

block 9 is transferred to the closed state, prohibiting further passage of pulses from the outputs of block 3 to form a time shift to the signal conditioners of block 9. The generated signals arrive at the corresponding input and strobe buses of the element under study 10, which is overloaded at the beginning of the differential input signal. The front edge of this signal when adjusting the pulse frequency of the controlled oscillator 1 is delayed in comparison with the leading edge of the gating signal by the value of dT, which depends on the n-growth of the period t of the signal of the generator 1 after adjusting its parts. If, at the same time, the delay time of the gating signal of the test element 10 is longer than the generated time shift CiTv between the leading edges of the drop

Yes. the input signal and the signal of the strobe, the gating component of the element 10 will fix the signal corresponding to the input differential formed by block 9. Otherwise, the gating component captures the signal corresponding to the zero initial input level, since the gating signal appears earlier at the output of the gating component than the difference in input signal. reaches the logic voltage level, i.e. such a level that the gating component of the test element 10 is already used as or respectively. The signal recorded by the component, after gating after its appearance at the output of the element 10, is decrypted, written into the buffer register of the information processing and recording block b and outputted to the indicators same block 6 for visual observation. The small internal resistance of the input unit shaper of block 9 reduces the influence of the input capacitance of element 10 on the time the input signal reaches a logical voltage level. The influence exerted is also reduced by the fact that element 10 is overexcited by an input signal with a steep leading edge at the beginning of its differential . In this case, the time shift DTx at the output of block 3 is equal to the delay time of the gating signal of the test element 10 at the moment of the beginning of a change in the state of its output information, which indicates that the gating component locks the beginning of the differential signal. Impulses, time shift between the leading fronts of which are DT from the outputs

block 3 forming a time shift arrives at the inputs of binary counters of block 4 extending the delay time, in which the number of stacked counting pulses is equal and equal to M "Time shift between the beginnings of the pulses at the outputs of the counters after they are completely filled.

0

to be

thirty

35

20 40 45 50 55

mlt ,, .- (3)

At the exit 5 of the formation. time interval this time shift is u-tu. transformed into a rectangular pulse width iT, |. The front edge of this Ht-dummy opens the input for the arrival of counting pulses from the generator 2 output to the binary-decimal counter of the processing and recording information block 6. The rear edge of the pulse at the output of the time interval formation block 5 closes the passage of the counting pulses on the binary 25 decimal block 25 of the block bz writes information from this counter to the buffer register of the information processing and recording block b., The resolution trigger of the time shift block 3 translates into s: the closed state and the resolution trigger of the control unit 8 are in the standby mode. The information on the buffer register of the block b is decrypted and displayed on the indicators of the same block b for a visual representation — the measured delay time of the gating signal. When determining the block 11 7 moment t

moment t. begins

and block

.- „.ici-iri.-v-. - new cycle mat

measurements. The number ;, recorded on the binary-decimal counter of the processing and recording information block b:

 DT.TC

(four)

The time shift of the LT is the equivalent of the measured time delay of the gating signal in the gating component of the gated integrated circuit of the test. If you choose the ratio M / T. 10 then. the measured delay time is expressed in nanoseconds.

Thus, the use of the tracking unit 11 in the known device allows to reduce to zero the hysteresis of coincidence of the leading edges of the signals of the generators 1 and 2. Since the hysteresis is a source of error, the block 11 contributes to

the accuracy of measurements of the delay time of gating signals in the components of gating integrated circuits.

Claims (1)

Invention Formula G Device for measuring the delay time by auth.St. No. 1000999, characterized in that, with 516408 To ensure accuracy, a tracking unit is entered into it, the first input of which is connected to the output of the controlled pulse generator, the second input of the tracking unit is connected to the output of the pulse generator, the third input of the tracking unit is connected to the output of the coincidence unit, the third input of which is connected to 10 output tracking unit. II I C / 7. I. Fiyo.2