JPS6077537A - Transmission and reception system for digital transmission - Google Patents

Abstract

PURPOSE:To obtain a local generation pattern accurate at all times even at the state before training of an equalizer independently of chip/ring connection of a line by specifying the total number of ''1s'' in a frame synchronizing signal always to an even number of an odd number. CONSTITUTION:A switch 5 is changed over and connected respectively to contacts 6-8 at the transmission of a frame signal 1, a balance bit 4 and a training pattern 3, and each signal is transmitted to a line via a unipolar/bipolar converter 9. An output signal 1 of a frame synchronizing signal generating circuit 10 is fed also to an FF12 in this case, the FF12 is inverted at each ''1'' in the signal 1 and the bit 4 is transmitted after the signal 1, allowing to make the total number of ''1s'' always specific to an even number or an odd number. The signal via an equalizer 15 is outputted via an identifier 16 at the reception side and also only the polarity of the 1st bit of a frame synchronizing signal to decide the polarity of the local generation pattern by the generator 21.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a transmitting/receiving system for digital transmission, and more specifically to a transmission/reception system for digital transmission, for example, a transmission/reception system such as a bipolar code.

This invention relates to transmission and reception for digital baseband wired transmission systems using codes with negative polarity, in particular frame synchronization signal generation and training signal formation.

[Background of the invention]

In the digital baseband wired transmission system, a ternary alternating code is used to cancel out the DC component of the transmission signal and reduce code amount interference deterioration due to line DC cutoff. For example, in the most commonly used bipolar code, logic "1"
corresponds to two signals, +1" and 6-1", and each time 61" is input, "+1" and "-1" are output alternately to the line. Note that '0" is transmitted as is. Ru.

On the other hand, a waveform equalizer is installed at the receiving end of the line to compensate for waveform distortion caused by line transmission, but when an automatic equalizer is used as this equalizer, it is necessary to improve the convergence of the equalizer. , training will be conducted. This training means that when a call occurs, before transmitting normal data, the sending side sends out a specific signal bang for training determined in advance, and the receiving side sends out a specific signal bang (hereinafter referred to as (referred to as a locally generated bang),
This is a method of estimating the state of transmission degradation by comparing the input signal degraded by line transmission with this locally generated bang. This locally generated pattern is the same as the transmitted signal.
It must be a value pattern, and its polarity must be the same as the transmitted signal. However, when connecting the line to equipment on the transmitting side and receiving side, if the polarity of the line (generally called tip/ring or A line/B line) is incorrectly connected, the polarity of the line output signal and locally generated pattern will be reversed. Normal training will not take place.

To solve this problem, a possible method is to insert a simple frame synchronization signal in front of the original training pattern, check the polarity of this frame synchronization signal, and control the polarity of the locally generated pattern. But inside? In the state before receiving equalizer training, it is impossible to accurately identify the degraded received waveform, so the frame synchronization signal cannot be accurately determined, and there is a high possibility that the polarity of the training pattern will be incorrectly determined.

Furthermore, there is a method to determine the polarity of the input signal by setting a continuous section of "'0" appropriately in front of the frame synchronization signal so that only the first pit of the frame synchronization signal can be determined without the influence of code amount interference. Generally, a multi-frame signal, a monitoring signal, etc. are inserted into the frame synchronization signal, so the number of logic "1m" in the frame synchronization signal becomes undefined, and the first logic 61" of the subsequent training signal is 6+1#.
It is not possible to determine whether it starts from 1 or from '-1'. Therefore, it is not possible to determine the correct polarity of the locally generated pattern by simply monitoring the first pit of the frame synchronization signal.

[Purpose of the invention]

The present invention solves the above-mentioned problems of the conventional method, and even if the tip/ring of the line is incorrectly connected or any signal is inserted into the frame synchronization signal, the locally generated pattern for training the correct polarity can be obtained. It provides the means.

[Summary of the invention]

In order to achieve the above object, the present invention provides logic 61'' in a frame synchronization signal inserted before a training pattern.
If the total number of is always specified as either an even number or an odd number, then K
Therefore, a frame signal is created in the transmitter such that the polarity of the subsequent training pattern can be determined immediately by determining the polarity of the first pit of the frame signal, and the receiver generates a frame signal that is not affected by code amount interference. The polarity of the locally generated pattern is determined by determining only the polarity of the first pit.

[Embodiments of the invention]

The present invention will be explained in detail below using examples.

FIG. 1 shows a part of a transmission signal in an embodiment of the transmission/reception system according to the present invention. In the figure, 1 indicates the frame synchronization signal insertion position. As shown in the figure, in front of the frame synchronization signal 1, a continuous section 2 of °'0" of a certain period is provided,
Clarifying the start time of frame synchronization signal 1,
The first pit of the signal is prevented from receiving interference from the forward code, and even if the equalizer does not perform normal waveform equalization, at least the polarity information of the first pit can be accurately determined. Information bits such as a multi-frame synchronization signal and a monitoring signal are added to the frame synchronization signal 1, and the number of logic "1"s in the frame synchronization signal 1 is generally undefined. Therefore, the polarity of the subsequent training pattern 3 is inverted depending on whether the logic "11" is an odd number or an even number, so a balance bit 4 is inserted between the frame synchronization signal 1 and the training pattern 3. This balance bit 4 is inserted to ensure that the individual peaks of logic @1'' in the section from the start of frame synchronization signal 1 to training pattern 3 are always even or odd numbers, and the first pit of frame synchronization signal 1 If the polarity of the training pattern 3 is known, the polarity of the training pattern 3 can be immediately determined.

FIG. 2 shows an embodiment of a transmitter circuit that generates the signals shown in FIG.
When transmitting the balanced bit, connect to contact 6, while transmitting balanced bit 4, connect to contact 7,
While the training pattern 3 is being transmitted, it is connected to the contact 8. The signal passing through this switch is sent to the line via a unipolar/bipolar converter 9. The frame synchronization signal 1 is generated by the synchronization signal generation circuit 10.
Multi-frame information, monitoring information, etc. are input to the terminal 11 through the terminal 11. Frame synchronization signal generation circuit 10
The output signal of is supplied to contact 6 and at the same time to 7 lip-flop 12. The output of the flip-flop 12 becomes '1' every time a logic '1' appears in the frame synchronization signal 1.
For example, when there is an even number of "1", the output is always "0", and when there is an odd number, the output is always "1".
Therefore, by continuously outputting the balanced bit 4 after the frame synchronization signal 1, the total number of '1's can always be an even number or an odd number.

The selection of an even number or an odd number is arbitrarily set depending on whether the output of the flip-flop 12 is taken as Q or Q. After outputting the output signal of the flip-flop 12 to the line as a balanced bit 4, the training bump generation circuit 13 sends a regular training button 3 to the line.

On the other hand, the receiving circuit is shown in FIG. The line output signal is input to the input terminal 14, becomes a digital signal via the equalizer 15 and the discriminator 16, and is output from the terminal 17. The switch 18 is used to switch the equalizer between the normal operation mode and the training mode; when connected to the terminal 19, it is in the normal operation mode in which it self-corrects using the data after identification, and when it is connected to the terminal 20, it is in the normal operation mode. Local bang generator 2
The training mode is entered using the locally generated bang generated by step 1. This switch 18 is connected to the 20 side during a main call, and is connected to the 19 side after training.

The output of the locally generated bang generator 21 is supplied to the equalizer 15 via the polarity switch 22. The polarity switch 22 is set to either normal, reverse, or reverse depending on the direction of the first transient of the discriminator 16 (the transient generated by the first bit of the frame synchronization signal). On the other hand, the discriminator 16
The first transient of is delayed by the frame sync signal and balance bit duration by delay 1cil path 23 and applied as a start signal to bang generator 21. By the above description, it becomes possible to generate a locally generated pattern of correct polarity at a regular time.

As shown above, by applying the present invention, it is possible to obtain accurate local generation patterns without worrying about the tip/ring connection of the line, and even before the equistopper is trained. , system reliability and utility can be significantly improved.

[Brief explanation of the drawing]

FIG. 1 is a signal configuration diagram showing a part of a transmission signal in one embodiment of the present invention, FIG. 2 is a transmission circuit configuration diagram in one embodiment of the present invention, and FIG. It is a receiver circuit block diagram. DESCRIPTION OF SYMBOLS 1... Frame synchronization JtJ] signal, 3... Training button, 4... Balance bit, 10... Frame synchronization signal generator, 12... 7 lips, 13...
...Training pattern/generator, 15--Automatic equalizer, 16--Discriminator, 21--Locally generated bang generator, 22--Polarity switch, ¥J 1 Fig. Z Fig. 3 diagram

Claims (1)

[Claims] On the transmitting side, after sending the frame synchronization signal, it sends a balanced bit, and the total number of logic ``'1#'' in both is always an even or odd number regardless of the frame synchronization signal, and then a training button is sent and received. A transmitting/receiving system for digital transmission characterized in that the polarity of the locally generated pattern is determined after determining the polarity of the first bit of the frame synchronization signal.