JPS5859651A - Digital signal transmitting method - Google Patents

Abstract

PURPOSE:To easily discriminate the polarity of a received digital signal, by inserting a bit which is prescribed to one value of a binary value in a digital signal, and also is capable of discriminating the polarity by relation to other bit, and detecting its bit by the receiving side. CONSTITUTION:A binary value of digital data is modulated so as to have a corresponding relation to the polarity of a signal, and its digital signal is transmitted. Into its signal, a bit which is prescribed to one value in a binary value, and also is capable of discriminating its value by relation to other bit is inserted. This digital data is provided to a word sink extracting circuit 2 of the receiving side, a work sink signal is outputted from an output terminal 3, and a bit clock signal of data and a serial data signal are outputted from output terminals 4, 5. Subsequently, the bit which has been inserted by the signal from the terminal 3 and an output of an S-P converter 6 is detected by a polarity detecting circuit part 20, and the polarity of the received digital signal is discriminated by an EXOR circuit 9, and is outputted from an output terminal 13.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of transmitting a digital signal in which binary data has a correspondence relationship with the polarity of the signal, and in particular, it relates to a method of transmitting a digital signal in which binary data has a correspondence relationship with the polarity of the signal. In general, modulation methods for converting digital binary data into electrical signals include RZ (Return to Ze).
ro), N RZ (Non Return to
Zero), NRZ I (Non Return)
n to Zero I), FM (Freque
ncy Modulation), MFM
(Modified Frequency Module
ation ), P E (Phase Encod
ing), etc., are known, and each has its own characteristics. Here, in the modulated signals such as RZ and NRZ, the signal polarity corresponds to the data binary values rlJ and rOJ, so if the signal polarity is reversed at the time of reception, the data binary values are also reversed. It becomes something that has been done. This is likely to occur, for example, when transmitting digital signals using the EIA standard R8-422 signal transmission line, or when using a transducer or the like at the receiving end.
This is one of the drawbacks of modulation methods such as RZ. However, especially in the NRZ modulation method, the maximum repetition frequency is approximately 1/2 compared to other FM, MFM modulation methods, etc.
It is advantageous for long distance transmission or high speed data transfer.

The present invention has been made in view of the conventional situation, and when transmitting/receiving (or recording/reproducing) a digital signal in which the binary data and the polarity of the signal correspond, the polarity of the signal itself is reversed. An object of the present invention is to provide a digital signal transmission method that enables so-called polarity-free signal transmission, which can restore the correspondence between a digital signal and original data even if the data is changed.

''That is, according to the digital signal transmission method according to the present invention, 2 such as "l" JOJ to represent digital data.
In a method of transmitting a digital signal modulated such that the value and the polarity of the signal have a certain correspondence with each other, the digital signal includes a bit that is predefined as one of the two values and that is different from the other bit. A bit that can determine the polarity based on the relationship is inserted, and by detecting this bit on the receiving side, the polarity inversion state of the received digital signal itself is determined, and depending on the output of this determination, the polarity of the digital signal and the polarity of the above-mentioned digital data are determined. It is characterized by restoring the correspondence with values.

Therefore, by applying the method of the present invention when transmitting digital data using, for example, an NRZ modulated digital signal, even if the polarity of the signal itself is reversed during transmission or at the time of transmission/reception (or during recording/reproduction). , it is possible to determine the polarity inversion state of the signal on the receiving side (or the reproducing side), and the original digital data can be accurately restored from the received digital signal (or the reproduced digital signal), so-called Polarity Free.
Not only can signal transmission be performed, but also effects such as long-distance transmission, high-speed data transfer, and high-density recording, which are the features of the NRZ modulation described above, can be obtained at the same time.The following describes preferred embodiments of the present invention. This will be explained with reference to the drawings.

Now, as the digital data mentioned above, PCM data (Pulse Code Mo.
Duration Data), one word corresponds to one sampling data of an analog audio signal. This l word is composed of 32 bits as shown in FIG. 1B, for example, and MSB (Most 51gn
20 bits from 1ficant Bit) are used for the PCM data of the one sampled data.

In order to serially transmit such digital data using a pair of signal transmission lines, it is necessary to also include a synchronization signal in the digital signal, and in this example, 30 to 32
The third bit is used as a synchronization signal (synchronization signal within data). Further, a plurality of such words, for example, 256 words as shown in FIG. 1F, are grouped together to form an l block.

That is, FIG. 1 is a diagram for explaining an example of the format of a digital signal used in the digital signal transmission method according to the present invention, and FIG. B constitutes the l word3
Figure 1 C shows the actual format of the l word, Figure 1 Di shows an example of a concrete digital signal near the synchronization signal, and Figure 1 F/fi shows multiple words (for example, 256 words). This shows an example of the format within a block configured by .

In FIG. 1, the period Tws of the word sync signal A
tri, is equal to the sampling period of the PCM audio signal, and is 22.698 μsec when the sampling frequency is 44.056 kHz. The unit time T of data bits is the word sync period Tws f
Of these 32 bits in one word, 20 pits from the first bit MSB are used for the sampling data, and the remaining 21 to 28 bits are used for the sampling data.
The first 8 bits are control bits, the 29th bit is a block flag bit, and 30, 31.3
The second three bits are used as a word sync signal (WSD) K in data and data, and this WSD is a signal in a format different from that of data. For example, as shown in Figure 1C, the 29th pick from the MSB) (2
9SB)'tU, unit time T(DNRZ (Non
The next 3 bits are divided into two, and the inverted (negative) data and non-inverted (affirmed) data of the 29th bit data are sequentially converted into an NRZ signal with a unit time of 1.5 T. The above-mentioned WSD signal is obtained by arranging the signals. Therefore, the data rlJJOJ is changed to the signal “H” (high level) l L l (low level)
When corresponding to each, the 29th bit data is "
0", K"H', "L" shown in Figure 1 DK.
When the 29th bit is rlJ, the WsD signal is in the order of "TV", and the WsD signal is in the order of "L" and "H" as shown in Fig. 1E.
It becomes an SD signal.

By the way, the 29th bit is used as a block flag bit, and as shown in FIG.
In the first word of the 56 words, 72 bits of this block are set to "l", and each of the 29th bits of the remaining 255 words are set to "0".
The structure of the above block is completely clarified.The 8 bits from 21st to 28th bits of the first word in one block are used as control bits, and the 21st to 28th bits of each of the remaining 255 words are used as user bits. It is used as

In this way, a block flag bit is provided for each word of l-word multi-bit digital data (for example, 25 bits).
6) For digital signals that have been divided into blocks, the block flag bit is the data value rlJ.
. The polarity of signals obtained consecutively (for example, 1HII L
-> corresponds to the above "0", and it can be determined that the polarity of only one signal obtained corresponds to the above "l". Therefore, even if the polarity of the digital signal itself is reversed during transmission or reception, the polarity of the received signal, for example "H", '
It is possible to define the correspondence between L'' and fFirlJ and rOJ of the above data, and it is possible to accurately restore the entire original digital data.

Figure 2 shows the polarity of such a received signal and the polarity of the original data.
An example of the circuit configuration of a receiving side equipped with a function to determine the correspondence relationship with the value and correct it to the original correspondence relationship is shown. If the polarity of the digital signal during transmission is reversed at the receiving end, etc., the input digital signal to input terminal 1 is positive (for example, "H', "L") and the original digital data is The correspondence relationship with the binary value (7t, for example, ri4.ro) is reversed (7' (for example, "lJ corresponds to 9L1)".

The input digital signal supplied to the input terminal 1 in FIG. A bit clock signal is taken out from the output terminal 5, and a serial data signal is taken out from the output terminal 5. The serial data signal from the output terminal 5 of the word sync extraction circuit 2 is transferred to a serial-to-parallel converter (S-P) using a shift register, for example.
(converter) 6, which becomes a parallel data signal for every l word, and is sent to a latch circuit T consisting of a parallel flip-flop.
sent to. These S-P converter 6 and latch circuit 7 are connected to the output terminal 4 of the word sync extraction circuit 2.
A pit clock signal is being sent from. The circuit section in this launch circuit 7''! is operated by the word sync signal of the input digital signal and the corresponding clock signal 1, but after the data is latched in this launch circuit T, the reception side internal clock signal or word 7
No. 7291 (supplied to input terminals 11 and 12, respectively) to a circuit that operates, for example, a parallel-to-serial converter (ps converter) 8, and processes clock timing signals used on the receiving side. The op-s converter 8 synchronizes the parallel data of each word from the launch circuit 7 with the internal clock of the receiving side.
Then, it is converted into serial data in a format convenient for signal processing in the receiving device, and then sent to an exclusive OR circuit (E
xOR circuit) 9 to the output terminal 13.

This ExOR circuit 9 operates when the output signal from the polarity detection circuit section (or data value discrimination circuit section) 20 is wH@.
The polarity of the output signal from the p-s converter 8 is inverted (1H
1 to IL" and 1L1'e"H") to the output terminal 13. That is, the polarity detection circuit section 20 sequentially detects the 2'9th bit of each word, for example. The polarity that appears only once in 256 words is “1”.
”, and by using the fact that two or more consecutive words with the same polarity correspond to “0”, we can find the correct correspondence (
For example, when "H" and "L" correspond to "1" and "0" respectively), send "L"! rlJ
(corresponding to) When "H-" k is sent to the ExOR circuit 9. Various circuit configurations can be considered for such a polarity detection circuit section 20, but for example, in FIG. 2, the following configuration is used. is used. That is, 2 in the l word above
In order to detect the 9th bit, only the 29th bit data signal of the parallel data signal from the S-P converter 6 is extracted and sent to the polarity detection circuit section 20.

This 29th bit data signal is input to the polarity detection input terminal, one input terminal of the ExOR circuit 22, one input terminal of the NOR circuit 23, and the data input terminal of the second D-type flip-flop 24, respectively. Supplied. A word sync signal from the output terminal 3 of the word sync extraction circuit 2 is supplied to the clock input terminal of the first D-type flip 70 tube 21. The output from this D-type flip-flop 21 is sent to the other input terminal of the ExOR circuit 22, and the output from this ExOR circuit 22 is sent to the other input terminal VC of the NOR circuit 23.

The output of this NOR circuit 23 is sent to one input terminal of a NAND circuit 25, and the other input terminal of this NAND circuit 25 receives a signal obtained by inverting the word sync signal from the output terminal 3 by an inverter 26. Sent. This N
The output of the AND circuit 25 is sent to the second input terminal of the second D-type flip-flop 24. The output of this D-type flip-flop 24 is sent to the other input terminal of the ExQR circuit 9.

As for the operation of such a polarity detection circuit section 20, first, the third This will be explained with reference to the figures.

FIG. 3A shows the output terminal 3 of the word sync extraction circuit 2.
This shows a word sync signal obtained from 1 word, which is a pulse signal with a period Tw for 1 word. SP converter 6
29th bit data signal u from 'H'; 6frl
JK, "L'; AZrOJK (-), since they correspond correctly, 256 words (2
56Tw) Nikki l two only 1 minute becomes 1H'', remaining 2
As shown in the diagram for 55 words, only the time Tw from time t2 to time t becomes "Hl". This signal in the third diagram and the 29th bit data signal B are sent to the NOR circuit 23, and the NOR circuit 23 outputs a signal at time t1 as shown in Figure 3E. A signal such as 1L'' from 1J to 1J is output.Here, the impark 26 inverts the word sync signal A and outputs a signal as shown in FIG. 3F, so these signals By sending E and F to the NAND circuit 25, the NAND circuit 25 outputs a signal as shown in FIG. The period between times t1 and t3 in the word sync signal in Figure 3A is fixed at @H1, and the clock during this period is missing. The 29th bit data signal B is supplied,
Since the above clock is missing at the timing when this signal B becomes @H1, it is always 1 as shown in Figure 3H.
An output signal of L1 is obtained and this signal is supplied to the other input terminal of EXOP circuit 9. Therefore, when the output signal from the p-s converter 8 passes through the ExOR circuit 9, the polarity is not reversed and the output signal is sent to the output terminal 13 with "H" and "L" unchanged. Sent.

Next, when the correspondence relationship between the polarity of the received signal and the binary value of the original data is reversed, that is, for example, lHl of the received digital signal corresponds to "o" and 1L1 corresponds to "l". The operation in this case will be explained with reference to FIG.

The 41''9A-H correspond to the above-mentioned FIG. 3A-H, respectively, and the word sync signal from the output terminal 3 of the word sync extracting circuit 2 is on the upstream side of FIG. 4A. Now, "o" of the original data is l H1 of the data signal
Therefore, in the 29th bit data signal, one word out of the 256 words of the l block is l.
At L', the remaining 255 words become the IHL signal. FIG. 4BK shows the 29th bit data signal which becomes "Ll" between time t□ and t2. This data signal B is
delayed by the above-mentioned time Tw by the type flip-flop 21,
The signal shown in FIG. 4C is output. As shown in the ExOR circuit 22D of this signal C and the data signal B, the IH1 signal is output only between times t1 and t8. By sending this signal and the data signal B to the NOR circuit 23, the signal shown in FIG. 4E is generated. Since this signal E is always 14L1, the inverted word sync signal from the inverter 26 (@4 Figure F) is blocked by the I/1 NAND circuit 25, and the DfU flip-flop 24
The clock supplied to is fixed to 1H1 as shown in FIG. 4G. Therefore, the output of the D-adjustable flip-flop 24 is always w Hw as shown in FIG. 4H, and this is supplied to the other input terminal of the ExOR circuit 9. At this time, the output signal from the Jp-s converter 8 is t, ExOR
When passing through the circuit 9, the polarity of the signal is inverted, converting 'H1 to 1L' and IHl to M n H, respectively.

Therefore, the digital signal obtained from the output terminal 13 has a correct correspondence relationship such that 'H1 represents the original data "l" and 'L1 represents [oJ].

In other words, regardless of whether the polarity of the received digital signal itself supplied to the input terminal 1 of the circuit shown in FIG. For example, if there is a relationship such that 'H' and 'L' correspond to data 'l' and '0', the above-mentioned NRZ modulation signal etc. does not depend on polarity (Po1arity Free). Not only is it possible to transmit digital signals, but also advantages in long-distance transmission, high-speed data transfer, etc. can be enjoyed by using the NRZ modulated signal. In addition, the polarity detection circuit section 20 in FIG.
can be constructed easily and inexpensively by using, for example, about three commercially available TTLICs.

Furthermore, is the digital signal transmission in the present invention an actual signal transmission line? This includes not only transmission using a recording medium, but also recording and reproduction via a recording medium.
Of course, it is possible to record and play back digital signals that are free of charge.
J is predefined by using the fact that not only the block flag bit but also the 26th bit of the control bits is always set to "0" [2. Detect this 26th bit] The polarity detection (or data value discrimination) may be performed by Furthermore, it goes without saying that the digital signal format is not limited to the example shown in FIG. In addition, various changes are possible without departing from the gist of the present invention.

[Brief explanation of drawings]

FIG. 1 is a diagram for explaining an example of a digital signal format that can be used in the present invention, FIG. 2 is a block circuit diagram showing an example of a receiving side circuit configuration used to implement the present invention, and FIG. 4 is a time chart for explaining the operation of the circuit shown in FIG. 2 in different input states. 0 1... Input terminal 2... Word sync extraction circuit 9... ExOR circuit 13...Output terminal 20@...Cylinder column detection circuit section representative Patent attorney Koike Miwari 1) Sakae Mura - 3rd m 4th aa H... L□

Claims (1)

[Claims] In a method of transmitting a digital signal that is highly modulated so that the binary values of the digital data have a corresponding relationship with the polarity of the signal,
By inserting a bit in the digital signal that is predefined as one of the two values and whose value can be determined in relation to other bits, and detecting this bit on the receiving side, the received digital A digital signal transmission method comprising determining whether or not the polarity of the signal itself has been reversed, and restoring the correspondence between the polarity of the digital signal and the binary value of the digital gator according to the output of this determination.