JPS607739A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS607739A JPS607739A JP11552083A JP11552083A JPS607739A JP S607739 A JPS607739 A JP S607739A JP 11552083 A JP11552083 A JP 11552083A JP 11552083 A JP11552083 A JP 11552083A JP S607739 A JPS607739 A JP S607739A
- Authority
- JP
- Japan
- Prior art keywords
- cover
- desiccant
- cavity
- package
- glass
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
- H01L23/18—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device
- H01L23/26—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device including materials for absorbing or reacting with moisture or other undesired substances, e.g. getters
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16151—Cap comprising an aperture, e.g. for pressure control, encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
Abstract
Description
【発明の詳細な説明】
本発明は半導体装置の製造方法にかかり、特に、パッケ
ージ内湿度が超低湿度である半導体装置の製造方法に関
する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for manufacturing a semiconductor device in which the humidity inside the package is extremely low.
従来、パッケージ内を低湿度にする方法としては、第１
図に示す様な方法があった。つまり、セラミックキャン
プ１の内側にあらかじめデシカント２を塗布ならびに焼
結させておき、しかるのちに、素子４が実装済みである
パッケージ５と前記セラミックキャップ１とを低湿度雰
囲気のベルト炉等で、低融点ガラス３．３”を介して気
密封止するのであった。この場合、キャップ封止時に封
止用ガラス、セラミックキャップ、及びセラミックベー
ス内壁に付着していた水分が脱着し、パッケージ内に残
存する。しかし、これらの水分はキャップ封止の際、封
止温度が常温に近づくにつれてデシカント２に吸着され
る。したがって常温状態においてはパッケージ内は低湿
度に保たれている。Conventionally, the first method of reducing humidity inside the package was
There was a method as shown in the figure. That is, the desiccant 2 is applied and sintered on the inside of the ceramic camp 1 in advance, and then the package 5 on which the element 4 is already mounted and the ceramic cap 1 are heated in a belt furnace or the like in a low humidity atmosphere. Hermetic sealing was performed through a 3.3" melting point glass. In this case, when the cap was sealed, moisture adhering to the sealing glass, the ceramic cap, and the inner wall of the ceramic base was desorbed and remained inside the package. However, when sealing the cap, these moistures are adsorbed by the desiccant 2 as the sealing temperature approaches room temperature.Therefore, at room temperature, the inside of the package is kept at low humidity.
ところが、第１図に示す従来方法であると、製品の使用
温度が高温になると、パッケージ内湿度が高くなってし
まうという欠点を有している。たとえば製品温度が１０
０℃に近づいた場合、デシカントに吸着していた水分が
再び脱着し、パッケージ内湿度が高くなってしまう。こ
の様に、パッケージ内を低湿度に保つことを目的とした
従来方法であると、製品が高温になった場合、パッケー
ジ内湿度は高くなシ、リーク電流の増加や配線パターン
の腐食等の現象が発生するという欠点を有している。However, the conventional method shown in FIG. 1 has the disadvantage that when the product is used at a high temperature, the humidity inside the package increases. For example, the product temperature is 10
When the temperature approaches 0°C, the moisture adsorbed to the desiccant is desorbed again, increasing the humidity inside the package. In this way, with conventional methods aimed at keeping the inside of the package at low humidity, when the product gets hot, the humidity inside the package is not high, and phenomena such as increased leakage current and corrosion of wiring patterns occur. It has the disadvantage that it occurs.
以上述べた様な従来方法の欠点を解消し高温下において
もパッケージ内湿産を超低湿度に保つことができる、半
導体装置の製造方法を、本発明は提供するものである。The present invention provides a method for manufacturing a semiconductor device that eliminates the drawbacks of the conventional methods as described above and can maintain extremely low humidity inside the package even under high temperatures.
本発明の特徴は、デシカント付きキャップを封止した後
、パッケージ内において、デシカントが付着している部
分と、素子が実装されている部分を極部加熱によって遮
へいしてしまうことにある。A feature of the present invention is that after sealing the cap with a desiccant, the part to which the desiccant is attached and the part to which the element is mounted are shielded by extreme heating in the package.
以下、本発明の実施例を図明と共に説明する。Embodiments of the present invention will be described below with accompanying drawings.
まず第２因に示す様に、キャビティー６″ｆ：有しかつ
キャビティ内に貫通小穴７を有するセラミックキャップ
１のキャビティー内にデシカント２を塗布し、焼結させ
る。次に第３図に示す様に、セラミックキャップ１のキ
ャビティー６を透光性ガラス８にて封着する。透光性ガ
ラスにＢｓＯｓ、５ｒＯａを主成分としたガラスを用い
れば、７００〜８００℃の熱処理により、溶着が可能で
ある。この際、デシカントの焼結温度は８００〜８５０
℃程度であるから、デシカントへの影響はない。次に、
第４図に示す様に、セラミックキャップ１に封止用低融
点ガラス３ｆ：、グレーズし、焼成式せる。次に、第５
図に示す様に、素子４を実装済みであるパッケージ５と
セラミックキャップｌとを低融点ガラス３（３’）ｔ−
介して気密封止する。しかる後に、第６図に示す様にノ
ーブー光９を用いて、セラミックキャップ１の貫通小穴
７を溶着する。小穴の径が０．０５〜０．１０程度であ
れば、容易に溶着することができる。First, as shown in the second factor, a desiccant 2 is applied to the cavity of the ceramic cap 1 having a cavity 6''f and a small through hole 7 inside the cavity and sintered. Next, as shown in FIG. As shown, the cavity 6 of the ceramic cap 1 is sealed with a translucent glass 8. If a glass containing BsOs and 5rOa as the main components is used as the translucent glass, welding can be achieved by heat treatment at 700 to 800°C. In this case, the sintering temperature of the desiccant is 800 to 850.
℃, so there is no effect on the desiccant. next,
As shown in FIG. 4, the ceramic cap 1 is glazed with low melting point glass 3f for sealing and fired. Next, the fifth
As shown in the figure, a package 5 on which an element 4 has been mounted and a ceramic cap l are connected to a low melting point glass 3 (3') t-
Hermetically sealed through. Thereafter, as shown in FIG. 6, the small through hole 7 of the ceramic cap 1 is welded using the Nauvoo light 9. If the diameter of the small hole is about 0.05 to 0.10, welding can be easily performed.
以上述べた、本発明に基づく半導体装置の製造方法であ
れば、キャップ気密封止時に封止用ガラス、セラミック
キャップ及びセラミックベース内壁より脱着した水分を
吸着しているデシカントと、素子が実装されている部分
を遮へいしであるため、高温状態においても、常に素子
実装空間を低湿度に保つことができるという利点を有し
ている。本発明に基づぐ製造方法によれば、素子表面上
にポリイミドの様な物質があり、キャップ封止時に多量
の水分を発生する装置の場合、特に有効である。According to the method for manufacturing a semiconductor device according to the present invention as described above, the desiccant adsorbs moisture desorbed from the sealing glass, the ceramic cap, and the inner wall of the ceramic base when the cap is hermetically sealed, and the element is mounted. This has the advantage that the element mounting space can always be kept at low humidity even in high temperature conditions. The manufacturing method according to the present invention is particularly effective in the case of devices in which there is a substance such as polyimide on the element surface and a large amount of moisture is generated when the cap is sealed.
第１図は、パッケージ内を低湿度にする従来方法を示す
断面図である。第２図〜第６図は、本発明の実施例に基
づく、パッケージ内を低湿度にする方法の一実施を示す
断面図である。
なお図にお−て、ｌ・・・・・・セラミックキャップ、
２・・・・・・デシカント、３，３′・・・・・・封止
用低融点ガラス、４・・・・・・素子、５・・・・・・
素子実装済みパッケージ、６・・・・・・セラミックキ
ャップのキャビティー、７・・・・・・セラミックキャ
ップの貫通小穴、８・・・・・・透第 ５ 凶
自ら ろ 圧］FIG. 1 is a cross-sectional view showing a conventional method for reducing humidity inside a package. 2 to 6 are cross-sectional views illustrating one implementation of a method for reducing humidity within a package according to an embodiment of the present invention. In the figure, l...ceramic cap,
2...Desicant, 3,3'...Low melting point glass for sealing, 4...Element, 5...
Package with element mounted, 6... Cavity of ceramic cap, 7... Small through hole of ceramic cap, 8... Transparent.
Claims (1)
するセラミックキャップの該キャビティー内にデシカン
トラ塗布し焼結する工程と、前記セラミックキャップの
キャビティー透光性ガラスにて封着する工程と、前記セ
ラミックキャップのキャビティーのない面に封止用低融
点ガラスをグレーズし焼成する工程と、前記セラミック
キャップを素子搭載済みパッケージの封止部に該低融点
ガラスを介して気密封止する工程と、しかるのちに、前
記セラミックキャンプの小穴をレーザー光にて融着封止
する工程ヲ有することを特徴とする半導体装置の製造方
法。A step of applying a desiccant to the inside of the cavity of a ceramic cap having a cavity and having a small through hole in the cavity and sintering it; and a step of sealing the cavity of the ceramic cap with translucent glass; a step of glazing and firing a low-melting glass for sealing on the surface of the ceramic cap that does not have a cavity; and a step of hermetically sealing the ceramic cap to a sealing portion of a package with an element mounted thereon via the low-melting glass. . A method for manufacturing a semiconductor device, comprising the step of subsequently sealing the small holes of the ceramic camp with laser light.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11552083A JPS607739A (en) | 1983-06-27 | 1983-06-27 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11552083A JPS607739A (en) | 1983-06-27 | 1983-06-27 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS607739A true JPS607739A (en) | 1985-01-16 |
Family
ID=14664554
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11552083A Pending JPS607739A (en) | 1983-06-27 | 1983-06-27 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS607739A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5413965A (en) * | 1993-09-13 | 1995-05-09 | Motorola, Inc. | Method of making microelectronic device package containing a liquid |
| EP0720260A1 (en) * | 1994-12-27 | 1996-07-03 | Corning Incorporated | Getter housing for electronic packages |
| WO2014079560A3 (en) * | 2012-11-22 | 2016-04-21 | Tronics Microsystems S.A. | Wafer level package with getter |
| US20170028515A1 (en) * | 2015-07-30 | 2017-02-02 | Ford Global Technologies, Llc | Metal sheet laser welding clamp |
-
1983
- 1983-06-27 JP JP11552083A patent/JPS607739A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5413965A (en) * | 1993-09-13 | 1995-05-09 | Motorola, Inc. | Method of making microelectronic device package containing a liquid |
| EP0720260A1 (en) * | 1994-12-27 | 1996-07-03 | Corning Incorporated | Getter housing for electronic packages |
| WO2014079560A3 (en) * | 2012-11-22 | 2016-04-21 | Tronics Microsystems S.A. | Wafer level package with getter |
| US20170028515A1 (en) * | 2015-07-30 | 2017-02-02 | Ford Global Technologies, Llc | Metal sheet laser welding clamp |
| US9770790B2 (en) * | 2015-07-30 | 2017-09-26 | Ford Global Technologies, Llc | Metal sheet laser welding clamp |
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