JPS6076157A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS6076157A
JPS6076157A JP58184762A JP18476283A JPS6076157A JP S6076157 A JPS6076157 A JP S6076157A JP 58184762 A JP58184762 A JP 58184762A JP 18476283 A JP18476283 A JP 18476283A JP S6076157 A JPS6076157 A JP S6076157A
Authority
JP
Japan
Prior art keywords
polysilicon
resistance element
high resistance
oxide film
molybdenum
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58184762A
Other languages
Japanese (ja)
Inventor
Isao Sasaki
佐々木 勇男
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP58184762A priority Critical patent/JPS6076157A/en
Publication of JPS6076157A publication Critical patent/JPS6076157A/en
Pending legal-status Critical Current

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  • Semiconductor Memories (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE:To remove an indentation in the lateral direction of an impurity, to manufacture a polysilicon high resistance element and to shrink the high resistance element by attaching a high melting-point metallic layer or an silicide layer on polysilicon in electrode sections at both ends of the high resistance element. CONSTITUTION:Polysilicon is grown, phosphorus ions are implanted to the whole surface, a polysilicon wiring 6 is formed, the surface of the polysilicon wiring is oxidized through thermal oxidation, an silicon oxide film is formed, the oxide film 3 in a section as a high resistance element is removed, and the oxide film on the surface of the polysilicon wiring is removed. Mo is evaporated on the whole surface, the whole is thermally treated, and molybdenum not reacted is removed by an etcher forming an silicide layer 7 on the surface of polysilicon. The resistance of an electrode section is lowered because molybdenum silicide is shaped on the surface of molybdenum in the electrode section, and the length L2 of the high resistance element may be brought to length in the irreducible minimum of a demand for bringing resistance value to desired value because the formation of the electrode section has no effect on the effective length of the high resistance element.

Description

【発明の詳細な説明】 本発明は、半導体装置、とくにMO8スタテックメモリ
に使用される、ポリシリコン高抵抗素子の構造に関する
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a structure of a polysilicon high resistance element used in a semiconductor device, particularly an MO8 static memory.

従来から、MO8スタテックメモリで使用されている高
抵抗素子は、第1図に示す構造をしている。即ち高抵抗
素子となるポリシリコン配線部2を絶縁膜3でおおい、
その両端に不純物、例えばリンを高饋度にドープレ、電
極部4を形成している。しかしながらこの構造では、両
端の不純物が、製造上必要な高温処理のため、横方向に
おしこまれ、実効的な高抵抗素子の長さは、設計値L1
7よシ小さくなる。このため設計値のミニマムは不純物
がリンの場合10〜15μ必要でラシ、高集積化を進め
る上でのネックとなりている〇 本発明は、ポリシリコン高抵抗素子の両端の電極部を、
ポリシリコン上に、高融点金属層または、シリサイド層
を付着させることにより形成することを特徴としている
A high resistance element conventionally used in MO8 static memory has a structure shown in FIG. That is, the polysilicon wiring portion 2 which becomes a high resistance element is covered with an insulating film 3,
At both ends thereof, impurities such as phosphorus are highly doped to form electrode portions 4. However, in this structure, impurities at both ends are injected laterally due to the high-temperature treatment required for manufacturing, and the effective length of the high-resistance element is reduced to the design value L1.
7. It becomes smaller. For this reason, the minimum design value is 10 to 15μ when the impurity is phosphorus, which is a bottleneck in promoting higher integration.
It is characterized in that it is formed by depositing a high melting point metal layer or a silicide layer on polysilicon.

本発明によれば、従来例のような、不純物の横方向おし
こみがなく、設計値通9の実効的抵抗長をもつ、高抵抗
素子が作られ、かつ高抵抗素子の縮小化が可能になる。
According to the present invention, a high-resistance element can be manufactured that does not have impurities introduced in the lateral direction as in the conventional example, has an effective resistance length of 9 times the design value, and can be made smaller. .

以下実施例にもとづき、本発明を説明する第2図は本実
施例の断面図である。
The present invention will be explained below based on an example. FIG. 2 is a sectional view of this example.

ポリシリコンロは、目的の抵抗値が得られるようにリン
をイオン注入によシドープしである、ドーズ量は0〜1
 x I Ql’fi’でらシ、ポリシリコンの厚さは
4000Aである。高抵抗素子となるポリシリコンの表
面には、シリコン酸化膜3が形成され、電極部となるポ
リシリコンの表面には、モリブデンシリサイド層7が形
成されである。この構造を得るにはポリシリコン成長後
、全面にリンのイオン注入を行い、通常のフォトエツチ
ング法によシ、ポリシリコン配線6を形成し、次に熱酸
化により、ポリシリコン配線の表面を酸化し、約150
OAのシリコン酸化膜を形成する。再びフォトエツチン
グ法によシ、高抵抗素子となる部分の酸化膜3を除き、
前記のポリシリコン配線表面の酸化膜をとりさる。次に
Moを全面に蒸着し、600℃の熱処理を行い、ポリシ
リコン表面にシリサイド層7を形成する過酸化水素系の
エツチャーで、未反応のモリブデンをとりのぞけは、第
2図の構造が得られる。
Polysilicon is doped with phosphorus by ion implantation to obtain the desired resistance value, and the dose is 0 to 1.
x I Ql'fi', the thickness of the polysilicon is 4000A. A silicon oxide film 3 is formed on the surface of the polysilicon that will become the high resistance element, and a molybdenum silicide layer 7 is formed on the surface of the polysilicon that will become the electrode portion. To obtain this structure, after growing polysilicon, ion implantation of phosphorus is performed on the entire surface, a polysilicon wiring 6 is formed by the usual photoetching method, and then the surface of the polysilicon wiring is oxidized by thermal oxidation. About 150
Form an OA silicon oxide film. Using the photoetching method again, the oxide film 3 in the area that will become the high-resistance element is removed.
The oxide film on the surface of the polysilicon wiring is removed. Next, Mo is vapor-deposited on the entire surface, heat-treated at 600°C, and unreacted molybdenum is removed using a hydrogen peroxide-based etcher that forms a silicide layer 7 on the polysilicon surface, resulting in the structure shown in Figure 2. It will be done.

本実施例では、′ct1.極部ポリシリコン表面にモリ
ブデンシリサイドが形成されであることにより電極部の
抵抗が下げられている。また電極部の形成が高抵抗素子
の実効長に全く影響を及ぼさないので、高抵抗素子の長
さり、は、抵抗値が希望する値となるための必要最小限
の長さとすればよく1.1000程度の抵抗を得ようと
すれば、2μ程度の長さがあれば充分である。
In this embodiment, 'ct1. Since molybdenum silicide is formed on the surface of the extreme polysilicon, the resistance of the electrode portion is lowered. Furthermore, since the formation of the electrode portion has no effect on the effective length of the high-resistance element, the length of the high-resistance element can be set to the minimum length necessary to achieve the desired resistance value.1. If you want to obtain a resistance of about 1000, a length of about 2μ is sufficient.

以上のように本発明によれば、ポリシリコン高抵抗素子
の大きさを従来の半分以下にすることができ、ポリシリ
コン高抵抗素子を利用しているMOSスタテックメモリ
のセルサイズの縮小に大きな効果を発揮し、半導体メモ
リ素子の微細化に役立つ。
As described above, according to the present invention, the size of the polysilicon high-resistance element can be reduced to less than half of the conventional size, and it is possible to significantly reduce the cell size of MOS static memory using the polysilicon high-resistance element. It is effective and helps miniaturize semiconductor memory devices.

なお本実施例では、電極部ポリシリコン表面にモリブデ
ンシリサイド層を形成したが、他の金属のシリサイド層
もしくは高融点金属層でも全く同一の効果が得られる。
In this embodiment, a molybdenum silicide layer is formed on the surface of the polysilicon electrode portion, but the same effect can be obtained with a silicide layer of another metal or a high melting point metal layer.

また半導体素子にかかる高抵抗素子を組込むとき、低抵
抗のポリシリコン配線層が同時に必要とされる場合は、
高抵抗素子近傍以外のポリシリコン配線層には、高濃度
に不純物をドープし、表面に形成されたシリサイド層と
ともに、ポリシリコ/配線層も電気伝導に寄与させるこ
とができるようにすることも可能でめる。
In addition, when incorporating high resistance elements into a semiconductor device, if a low resistance polysilicon wiring layer is also required,
It is also possible to dope impurities at a high concentration in the polysilicon wiring layer except in the vicinity of the high-resistance element, so that the polysilicon/wiring layer can contribute to electrical conduction along with the silicide layer formed on the surface. Melt.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来のポリ7リコン高抵抗素子の断面図、第2
図は本発明によるポリシリコン高抵抗素子の断面図。 尚、図において、l・・・・・・絶縁膜、2・・・・・
・高抵抗ポリシリコン、3・・・・・・酸化シリコン膜
、4・・・・・・高濃度リンドープポリシリコン、5・
・・・・・引き出し電極、6・・・・・・高抵抗ポリシ
リコン、7・・・・・・モリブデンシリサイドである。 躬 1 図 82図
Figure 1 is a cross-sectional view of a conventional poly7 silicon high resistance element, Figure 2
The figure is a cross-sectional view of a polysilicon high resistance element according to the present invention. In the figure, l... insulating film, 2...
・High resistance polysilicon, 3... Silicon oxide film, 4... High concentration phosphorus doped polysilicon, 5.
. . . Extraction electrode, 6 . . . High resistance polysilicon, 7 . . . Molybdenum silicide. 1 Figure 82

Claims (2)

【特許請求の範囲】[Claims] (1) 多結晶シリコン配線に於て、高抵抗素子として
使われる部分を除いて、ポリシリコン配線の表面に高融
点金属層、またはクリサイド層が形成されておることを
特徴とする半導体装置。
(1) A semiconductor device characterized in that, in the polycrystalline silicon wiring, a high melting point metal layer or a crystalcide layer is formed on the surface of the polysilicon wiring except for the portion used as a high resistance element.
(2)多結晶シリコン配線が、高濃度に不純物がドープ
された部分と、低濃度にドープされた部分、またはノン
ドープの部分からなることを特徴とする特許請求の範囲
(1)記載の半導体装置。
(2) A semiconductor device according to claim (1), characterized in that the polycrystalline silicon wiring comprises a heavily doped portion, a lightly doped portion, or a non-doped portion. .
JP58184762A 1983-10-03 1983-10-03 Semiconductor device Pending JPS6076157A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58184762A JPS6076157A (en) 1983-10-03 1983-10-03 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58184762A JPS6076157A (en) 1983-10-03 1983-10-03 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS6076157A true JPS6076157A (en) 1985-04-30

Family

ID=16158879

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58184762A Pending JPS6076157A (en) 1983-10-03 1983-10-03 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS6076157A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60263455A (en) * 1984-06-04 1985-12-26 インタ−ナシヨナル ビジネス マシ−ンズ コ−ポレ−シヨン Polysilicon structure
JPH028054U (en) * 1988-06-30 1990-01-18
JPH0491282U (en) * 1990-12-26 1992-08-10
US5670820A (en) * 1987-05-01 1997-09-23 Inmos Limited Semiconductor element incorporating a resistive device
US6020418A (en) * 1991-05-23 2000-02-01 Cytech Technology Corp. Microdispersions of hydroxamated polymers
WO2004105135A1 (en) * 2003-05-19 2004-12-02 Advanced Micro Devices, Inc. Method of forming resistive structures

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60263455A (en) * 1984-06-04 1985-12-26 インタ−ナシヨナル ビジネス マシ−ンズ コ−ポレ−シヨン Polysilicon structure
US5670820A (en) * 1987-05-01 1997-09-23 Inmos Limited Semiconductor element incorporating a resistive device
JPH028054U (en) * 1988-06-30 1990-01-18
JPH0491282U (en) * 1990-12-26 1992-08-10
US6020418A (en) * 1991-05-23 2000-02-01 Cytech Technology Corp. Microdispersions of hydroxamated polymers
WO2004105135A1 (en) * 2003-05-19 2004-12-02 Advanced Micro Devices, Inc. Method of forming resistive structures
GB2417830A (en) * 2003-05-19 2006-03-08 Advanced Micro Devices Inc Method of forming resistive structures
GB2417830B (en) * 2003-05-19 2007-04-25 Advanced Micro Devices Inc Method of forming resistive structures

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