JPS6075143A - Synchronizing circuit system - Google Patents

Abstract

PURPOSE:To prevent a synchronizing pattern from being detected in error by avoiding the synchronizing pattern from being inputted to a synchronism detection circuit except at the reception time. CONSTITUTION:A gate circuit 11 is opened at a reception timing and a reception signal is inputted to a serial-parallel converting section 16 via an equalizer 12 and a unipolar/bipolar converting circuit 13. A reception timing signal is given to the converting section 16 and when this signal is given, a high-order bit of the output of the converting section 16 is inputted to the synchronism detection circuit 7. A frame synchronism signal being an output of the synchronism detection circuit 7 is given to a register 17 to read the parallel output.

Description

TECHNICAL FIELD OF THE INVENTION The present invention relates to data transmission technology, and more particularly to a synchronous circuit system that prevents malfunctions of synchronous circuits in terminal circuits of digital transmission lines.

Conventional technology and problems The terminal part of the digital transmission line in the data transmission line is
Generally, it is configured as shown in FIG.
connected to. The transmission terminal 2 includes a gate circuit for cutting off the reception input during transmission, an equalizer for equalizing the reception signal, and the like.

Transmission terminal 2 is further connected to line terminal B, and line terminal 3
In the system, received data is serial-parallel converted to decompose frames, and transmitted signals are parallel-serial converted to assemble frames. Further, the signal processing section 4 performs predetermined signal processing under the control of the microprocessor 5, and the input/output signals of the signal processing section 40 are connected to the tetator highway or the terminal device via the interface section 6 that performs the required interface. .

Further, a synchronization detection circuit 7 is connected to the line terminal 6, and the synchronization detection circuit 7 detects a synchronization pattern from the received signal and generates a synchronization signal, and this synchronization signal is used to frame the received data frame at the line terminal 6. Used to synchronize.

In this case, the equalizer at the transmission terminal 2 generally performs signal equalization by changing the degree of amplification according to the peak value of the received signal. That is, in the equalizer, control is performed to lower the amplification degree when the input signal level is low, and to increase the amplification degree when the input signal level is low. Therefore, when the power of the other party's terminal is turned off, or when the terminal is disconnected from the line, the amplification level is maximized, and the noise causes the synchronization detection circuit to erroneously detect the synchronization pattern, causing the line termination to malfunction. Sometimes.

In addition, if the received signal is connected from transformer 1 to the equalizer via the gate circuit, crosstalk may occur due to the transmitted data if the performance of the gate circuit or equalizer is not sufficient, and as mentioned above, the gain of the equalizer is maximized. crosstalk may cause false detection of synchronization patterns.

Purpose of the Invention The present invention is intended to solve the problems of the prior art, and its purpose is to provide a synchronization circuit that does not cause false detection of synchronization patterns due to reception noise or crosstalk of transmitted data. The goal is to provide a method.

Embodiment of the Invention FIG. 2 shows the configuration of an embodiment of the synchronous circuit system of the present invention.
3 and the synchronization detection circuit 7. In the figure, 11 is a gate circuit, 12 is an equalizer,
16 is a bipolar/unipolar conversion circuit, 14 is a digital PLL circuit, 15 is an elastic memory, 16 is a serial/parallel converter, 17 is a register, 18 is a synchronous pattern detection circuit, 19 is a forward protection circuit, 20 is a backward protection circuit, 21
2 is a flip-flop, 22 is a parallel-to-serial converter, 26 is a unipolar/bipolar converter circuit, and 24 is an inverter.

In FIG. 2, transmission and reception are performed alternately at fixed time intervals according to the transmission timing signal and reception timing (i), respectively. Gate circuit 11 T!.

It is opened by the reception timing signal and inputs the reception signal to the equalizer 12. The equalizer 12 performs amplitude equalization by changing its amplification degree according to the received signal level. The bipolar/unipolar conversion circuit 13 converts the received data, which is an equalized bipolar signal, into a unipolar signal. The digital PLL circuit 14 reproduces a clock from the unipolar signal output and outputs it as a reception clock RCLK. The elastic memory 15 performs signal timing by reading the unipolar signal output using the reception clock RCLK and reading it using the internal clock CLK. The serial/parallel converter 16 is composed of a shift register and reads the output of the elastic memory 15 in series using an internal clock CLK to generate a parallel output. The register 17 holds the parallel output of the serial/parallel converter 16, reads it in response to a synchronization signal, and outputs the received signal frame by frame to a signal processing section (not shown). 1
Reference numeral 8 denotes a synchronization pattern detection section which inputs the synchronization pattern added to the upper bits of the received frame from the serial/parallel conversion section 16, compares it with the synchronization pattern held internally, and detects - = outputs a detection signal, and when they do not match, outputs an undetected signal. The forward protection circuit 19 performs appropriate forward protection and sets the flip-flop 21 in response to the transition from the undetected signal to the detected signal \, and the backward protection circuit 20 performs appropriate forward protection in response to the transition from the detected signal to the undetected signal \. Reset flip-flop 21 with appropriate backward protection. The Q output of the flip-flop 21 is used as a synchronizing signal to read the data frame in the register 17.

On the other hand, the parallel-to-serial converter 22 is composed of a shift register, receives the transmission data in parallel, adds a synchronization pattern to its upper bits and holds the data, and outputs the contents in series according to the transmission timing. This signal is a unipolar signal, and the unipolar/bipolar conversion circuit 23 converts it into a bipolar signal and outputs it as a transmission signal via the transformer 1 to the transmission line.

In the circuit shown in FIG. 2, the serial-to-parallel converter 16 is given the reception timing (i) as a reset signal via the inverter 24. Therefore, the serial-to-parallel converter 16 stops operating outside the reception time. , the synchronization pattern is not output to the synchronization detection circuit 18. Therefore, the synchronization pattern detection circuit 18 does not generate a detection signal, and the forward protection circuit 19
．． No synchronizing signal is generated through the backward protection circuit 20° flip-flop 21. Therefore, since the received frame is not read from the register 17, erroneous received data will not be output.

In this way, in the circuit shown in FIG. 2, the synchronization pattern is not output from the serial/parallel converter 16 to the synchronization pattern detection circuit 18 except during reception, so it is not possible to output the synchronization pattern when the other terminal is powered off or when the terminal is disconnected from the line. Even when the amplification degree of the equalizer is at its maximum, the synchronization pattern will not be erroneously detected and malfunction will not occur due to noise or crosstalk based on transmitted data.

FIG. 6 shows the configuration of another embodiment of the synchronous circuit system of the present invention. In this figure, the same parts as in FIG. 2 are indicated using the same numbers, and 25 is a gate.

In FIG. 6, gate 25 is open when receiving a reception timing signal and is closed otherwise. Therefore, at times other than the reception time, no synchronization pattern is input to the synchronization detection circuit 18 and no synchronization signal is generated.

Therefore, in the case of the circuit shown in Figure 6, even when the power of the other terminal is turned off or the terminal is disconnected from the line and the equalizer is at maximum amplification, the synchronization pattern will be affected by noise or crosstalk based on the transmitted data. There is no possibility of false detection and malfunction. Note that instead of providing the gate 25 controlled by the reception timing signal in the circuit of FIG. 6, the synchronization pattern detection circuit may be made operable when the reception timing signal is applied.

As described in detail, the synchronization circuit system of the present invention is capable of detecting signals other than the reception time by stopping the operation of the shift register that disassembles the received frame or by cutting off the input to the synchronization detection circuit. Since the synchronization detection circuit is designed so that the synchronization pattern is not input, if the amplification of the equalizer at the transmission end increases when the other end's power is turned off or the terminal is disconnected from the line, it will be detected due to noise or transmitted data. A-stoke does not cause erroneous detection of synchronization patterns, and therefore high performance is not required for the gate circuit for capturing the received signal at the transmission end and the equalizer for equalizing the received signal, making it economical. A termination circuit can be configured.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the configuration of the terminal end of a digital transmission line, and FIGS. 2 and 3 are block diagrams each showing the configuration of an embodiment of the synchronous circuit system of the present invention. DESCRIPTION OF SYMBOLS 1... Transformer, 2... Transmission termination, 6... Line termination, 4... Signal processing part, 5... Microprocessor, 6... Interface part, 7... Synchronization detection circuit,
11... Gate circuit (G), 12... Equalizer (
EQL), 13...Bipolar/unipolar conversion circuit (B/U), 14...Digital PLL circuit (D
PLL), 15... Elastic memory (ES), 1
6... Serial-to-parallel converter (S→P), 17... Register (REG), 18... Synchronous pattern detection circuit, 19.
...Front protection circuit, 20...Rear protection circuit, 21...
- Flip-prop (FF), 22... Parallel-serial replacement unit (p-+s), 25... Unipolar/bipolar conversion circuit (U/B), 24... Inverter, 25...
Gate patent applicant Fujitsu Limited agent Patent attorney Gobe Tamamushi (1 other person)

Claims (1)

[Claims] A transmission terminal that sends and receives data to and from a partner terminal and equalizes received signals; a line terminal that disassembles transmitted frames to extract data and assembles frames to be transmitted based on input data; In a two-wire time-division direction control data transmission termination circuit comprising a synchronization detection circuit that receives a synchronization pattern in a disassembled received frame and generates a reception synchronization signal, the synchronization detection circuit and ＼A synchronous circuit system characterized by providing a means to prevent a synchronous pattern from being input.