JPS607510A - Interface circuit - Google Patents

Abstract

PURPOSE:To prevent the transmission of wrong signals and to improve the reliability of an interface circuit by counting the time during which the power supply voltage reaches a prescribed level and delivering a state signal from the 1st means when the counted time elapses. CONSTITUTION:A controller 1 of a microprocessor, etc. is connected to the input terminal of a gate IC1 consisting of a TTL IC, and the IC1 is connected to a power supply VCC. The output terminal of the IC1 is connected to the base of a transistor TR1 via a resistance R1, and a resistance R2 and a capacitor C1 are connected in parallel between the emitter and the base of the TR1. The output of the TR1 is connected to an integrated circuit IC2 via a resistance R3 and a transmission circuit 2. Therefore the TR1 is kept nonconductive for a delay time due to a time constant of the C1 and the R1 respectively until the power supply voltage reaches the action securing level of the IC1 at the time of application of the VCC.

Description

DETAILED DESCRIPTION OF THE INVENTION (More details) The present invention relates to an interface circuit that transmits status signals such as a power-on completion signal.

(Prior art) Conventionally, this type of interface circuit is composed of a gate 1 made of a digital collection circuit such as a transistor ◆transistor logic (TTL) and a resistor. The output from 17 was transmitted as a transmission signal to the next stage equipment.

In general, when an integrated circuit such as a TTL is powered on, the output of the integrated circuit remains at its human power level for a predetermined period of time until it reaches the heavy pressure level of the IE source or the guaranteed operating range. It is not guaranteed and is uncertain.

Therefore, when the power is turned on, the output signal from the TTL integration circuit in the interface circuit that transmits the power-on completion signal is in an undefined state until the power supply has sufficiently risen. The circuit converts the signal to 'il'1. There were times when I just accepted it as Gen-in Completed 4'4.

As a result, the next-stage device determines that the contents of No. 100 of the ink face are valid, and interfaces 41-B'.

This caused the inconvenience of starting to analyze the contents of the document.

(Purpose) Therefore, the first object of the present invention is to eliminate the above-mentioned drawbacks and completely eliminate the transmission of erroneous signals that occur during the transition period from power-on to steady state. 41. ,i
-, lj only.

(Example) Hereinafter, the present invention will be described in detail with reference to the drawings.

E+', +1 Figure 1 shows an example of the configuration of the interface circuit of the present invention, where 1 is a control device for a microprocessor 19, and this control device 1 is composed of, for example, an open collector TTL integrated circuit. Connect H1 to the input terminal of gate ICI. The power terminal of the TTL 71 product circuit ICI is connected to the power supply Vcc and its ground bH
, : Ground the H child. Further, its output terminal is connected to the base of a PNP type transistor TRI via a resistor R1.

1 between the emitter and base of the transistor TRI,
A resistor R2 and a capacitor c1 are connected to each other.

The emitter of the transistor TRI is connected to the source V CC and the collector is connected to the resistor R3. - The resistors R1 and R2 described above determine the base current of the transistor TRI, and the resistor R3 The collector current of capacitor c1 and resistor R is limited.
Transistor TRI starts operating after a delay time determined by a modifier constant of 1, and TTL starts operating after the delay time has elapsed.
1, corresponding to outputs 1-4 from the integrated circuit ICI.

The signal is extracted from transistor TRI.

The collector output of transistor TRI is transmitted to resistor R4 via resistor R3 and transmission circuit 2. One end of the resistor R4 is connected, for example, to the input terminal of the TTL integrated circuit IC2 for controlling hysteresis characteristics, and its 4m end is grounded.

The earth terminal of the TTL integrated circuit IC2 is grounded, its power supply terminal is connected to the power supply Vcc, and its output terminal is connected to a next-stage device (not shown).

Here, from turning on the power supply VCC, the above-mentioned N IL n'
, rltil, since a sufficient base current is not supplied to the transistor TRI, the transistor TR,I is in a non-conductive state, and after the delay time has elapsed, the transistor TRI becomes conductive.

Here, the time constant of the capacitor C1 and the resistor R1 is set so that the delay time is the time required for the power supply level to the TTL integrated circuit ICI to reach the operation guaranteed level') i! shall be held. Therefore, during the period from when the power is turned on until the power supply voltage reaches the operation guaranteed level of the TTL integrated circuit ICI, the TTL integrated circuit I,' (no matter whether the output of the circuit ICI is at a low level or a high level) , I. Ranjisk TRI becomes non-conductive, and the TTL integrated circuit IC
The input of No. 2 remains at a low level "L".

Next, after the power supply Vcc is turned on, when the source voltage rises to an intermediate voltage level (for example, a specified value), a signal corresponding to the power-on completion signal from the control device 1 is manually transmitted to the TTL integrated circuit ICI. This TTL collection J
11 controls the output of the circuit 101. If this TTL integrated circuit [+ is an open collector type, TTL
When the input (+i) of the integrated circuit ICI is at a high level "H", its output is in an open state, and the transistor T
Since the emitter potential and base potential of RI are equal,
Transistor TRI becomes non-conductive. Therefore, T.T.
The input of L integrated circuit IC2 is low level "L".

On the other hand, the input signal of the TTL integrated circuit ICI is low level.
When the current is "L", the current i flows in the output direction of the integrated j; .

As described above, in this example, the period 1 tree until the power supply voltage level reaches the operation guaranteed level of the TTL 5jii circuit when the power supply Vcc is turned on is 3'7' of the power supply' voltage,
No matter how long or short the 1 time is, no matter what state the output of the TTL LSSM circuit ICI is, the transistor T
RI becomes non-conductive unconditionally. Therefore, TTL'l:
: Product circuit 1 (Since the input of R2 is always at a low level ゛L'', TTL collection JA 1126 ICI]l:Ij
Rikishin Ricaso (7s! 7 TTL', 'J, h'r
It is not transmitted to circuit IC2. And 'l;
When the voltage of the Jh bar Vcc rises sufficiently and the pressure level reaches the operation guaranteed level of the TTL integrated circuit IC1, the TTL integrated circuit 101 receives a power-on completion signal from the control device 1, etc. The state of 'j'j7. (Controlled by No. A, the status signal can be reliably transmitted to the TTL integrated circuit IC2.

Incidentally, in place of the TTL two-product circuit C1 in this example, an L-Ransisk circuit may be used. In addition, resistor R1 and other devices, '(41*':', floating capacitance, '
1: Supply of TTL collector circuit ICl- by etc.
't'
When the supply to RI is sufficiently extended by π, the capacitor C
Of course, it is also possible to omit 1: 12i. Also, it is a no-brainer that a diode can be inserted in parallel to the resistor R2.

Furthermore, without using the capacitor CI, the power supply 'FLJf
Power supply type 1,'
Between the emitter and pace of transistor TRI when lE V c is sufficiently S't', -J2? The tZ voltage may be, for example, 0.7V, and the transistor TRI may be in the 4-channel state. Furthermore, it goes without saying that the transistor TRI may be constructed of a Darlington discontinuous transistor without using the capacitor CI. If a transistor is used in Turlington contact, the power supply voltage Vc
For example, 2. Since the Darlington connected transistor does not conduct during the period until it becomes OV, the output of the TTL integrated circuit ICI only needs to be determined during that period.

(Effect) - As explained, according to the present invention, 'Ili:
The transmission of #j':4 C6, which occurs during the vortex period from when #j;- is turned on to the steady state, can be stopped for 1it-1, and the power supply is in the steady state. Since input completion signals and other statuses such as yp i + and 'r can be reliably transmitted to the interface, an extremely reliable interface can be constructed.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an example of the configuration of an ink face circuit according to the present invention. 1...Control equipment scrap, 2...Transmission circuit, IC:1,102...TTL integrated circuit, TRI...
Transistor, R1-R4...resistance, CI...capacitor, Vcc...power supply.

Claims (1)

[Claims] A first means for outputting the status 5), and a timer for outputting the power source'1c pressure until it reaches the specified level, and after the elapse of the time, the h'th means returns to the state 411.
and second means for applying a signal of 1°J''.