JPS6073786A - Vector data processing device - Google Patents

Abstract

PURPOSE:To execute a load instruction without decreasing hardware by accessing a main memory device by one out of the pipelines in the uncontinuous access and by making respective access pipelines independent in the access whose data continues. CONSTITUTION:When there are (1) VLD (data continuous), (2) VLD (-ditto-), (3) VLD (data uncontinuous), (4) VLD (data continuous) and (5) VLD (-ditto-) as vector load instructions (VLD) lines, the address needed to execute the instructions (1) is made at the address pipeline 17-A and the address needed to execute the instruction (2) is generated by the same address pipeline 17-B. After both addresses end, the address needed to execute the instruction (3) is generated by the same pipeline 17-A-17-D. There, the address needed to execute the instruction (4) is generated by the pipeline 17-A and the address needed to execute the instruction (5) is generated by the pipeline 17-B.

Description

[Detailed description of the invention]

[Invention Q) Technical field] The present invention provides that when main memory σ) block access is performed, one address generation control section controls one address generation section, and when performing block access to the main memory The present invention relates to a vector time data processing device in which one address generation control section controls a plurality of address generation sections when performing an access. C. Prior Art and Problems] A vector data processing device includes a vector register, a vector arithmetic unit, two access pipelines, an instruction processing unit, and the like. The vector operation vibe line performs double-precision, single-precision, and fixed-point operations in the same way as scalar arithmetic units. Double-precision data, single-precision data, and fixed foot small point data are defined on the vector register I in the format shown in FIG. Therefore, a transfer from main memory to a vector register or a write from a vector register to main memory is 4
This is done in B (byte) width or 8B units. Furthermore,
The load/store transfer speed must match the calculation speed. In other words, as shown in Figure 2, by writing vector-loaded data to a vector register and chaining it with the vector operation pipeline, the arithmetic unit operates in 1τ/4 operations. ,access·
The pipeline throughput is also 1τ/4 operation. In addition, when accessing the main memory control unit, 4
Since it handles B or 8B instructions, block access to the main memory can be performed when the distance is 4B to 8B when handling 4B data 4, and when the distance is 8B when handling 8Bf-1. It became possible. The throughput with the main memory is greater than or equal to the throughput with the vector register, making it possible to achieve a throughput commensurate with the calculation speed. If the distance is large, each of the two access pipelines needs four access pipelines to satisfy the above throughput. A total of eight address pipelines are required. Providing eight address pipelines increases the amount of hardware. [Object of the Invention] The present invention is based on the above consideration. To provide a vector data processing device capable of executing vector load instructions, vector store instructions, etc. with nonuniform block access without increasing the amount of hardware and without decreasing throughput. The purpose is to [Structure of the Invention] Therefore, the vector data processing device of the present invention independently performs transfer between the main storage device and the vector register using one or more data buses, an address generation unit, and an address generation unit. In a vector data processing device having a plurality of operable access pipe fins, when referring to data on the main memory, each access pipeline independently processes an address generator when the data to be referenced is accessed consecutively. and the address bus to issue accesses to the main memory, and in accesses where data is discontinuous, one of the multiple access pipelines handles the address generation unit and the address bus. The main storage device is accessed by managing the main memory. [Embodiments of the Invention] The present invention will be described below with reference to the drawings. FIG. 3 is a diagram showing an overview of a vector data processing device to which the present invention is applied, and FIG.
FIG. 5 is a diagram showing the configuration of an embodiment of the address section of the access pipeline. FIG. 6 is a diagram showing the configuration of the address generation section of one embodiment. FIG. FIG. 8 is a diagram showing the configuration of one embodiment of the main part of the address generation control section, and is a diagram for explaining the present invention in detail. In FIG. 3, l is the main memory and 2 is ν on the main memory.
, 3 is an instruction processing unit, and 4-A and 4-B are of an ACK configuration and can perform block access. The main storage control device 2 mediates data transfer between the main storage device 1 and the access request source device. The instruction processing unit 3 includes an access pipeline and a vector arithmetic unit.

It is used to issue commands to (not shown). When transmitting a command to the access e-vibration lines 4-A and 4-B, the command processing unit 3 sends an activation signal, a vector length, and a base address. Send the stance and opcode to the access pipeline. The access pipeline 4-A is. It stores vector working data to the main memory and loads vector data from the main memory.Reading data from the vector register - Vector
Writing data to a register. Performs alignment processing, address generation, and sending requests, request addresses, and opcodes to the main memory control unit. Access pipeline 4-B has the same functionality as 4-A. Vector register 415 stores vector data consisting of a plurality of elements. Although only one vector register is shown in the figure, real points can be read from the vector register, and four vector registers can be written to the vector register at a time. FIG. 4 shows the structure of one embodiment of the access pipeline. In FIG. 4, 6 is a priority control circuit 1, 7 is an address section, 8 is an align control section, 9 is an align circuit, 10 is an 800 circuit, and 11 and 12 are control signals i, respectively. The main memory control device 2 has a priority control circuit 6, and when main memory access requests conflict, four main memory access pipelines are connected to one main memory access pipeline 4-A according to priority. A data bus DB is connected to the main memory controller 2.
Four data buses DB are also connected between the access pipeline 4-B and the access pipeline 4-B. The data bus is 8B wide. The access pipeline 4-A includes an address section 7. It has an align control section 8 and an align circuit 9. When it is desired to access the main memory device 1, the address unit 7 sends a request, an operation code, and a request address to the main memory controller 2 via the control signal line 11. The align control section 8 controls the align circuit 9 according to a control signal from the main memory control device 2 . Four data buses (bus number 8B) are connected between the align circuit 9 and the vector register 5.

[There is. As described above, the access pipeline 4-B has the same configuration as the access pipeline 4-A. FIG. 5 shows the structure of one embodiment of the address section. In FIG. 5, 13-A and 13-B are address generation control sections, 14 and 14' are address generation sections, and BA is a base control section.
address, D is distance, VL is vector length, op
c is an operation code, and STA is an address generation control unit 13-A.
The activation signal STB is the address generation control unit 13-
The activation signals for B are shown respectively. When the address generation control section 13-A receives the base address BA, the source D, the vector length VL, the operation code OPC, and the start signal STA from the instruction processing section 3, it performs control for address generation. Address generation control section 13-
A checks the distance D and, if block fist access is possible, uses the address pipeline 17 as described below.
-A', block access w is performed, and if block e access is not possible, the address
Pipelines 17-A, 17-B, 17-C, 17
-D is controlled to generate an address. The address generation control unit 13-B receives the base address B from the instruction control unit 3.
A, distance D, vector length VL, opcode OP
It operates only when block access is possible when it receives C and activation signal, and the address and
A block 0 address is generated under pipeline 17-B'Y control. FIG. 6 shows the structure of one embodiment of the address generation section. In FIG. 6, 15-A and 15-B are adders;
1ft-A and 16-B are address conversion circuits, BARA and BARB are base address registers, DRA and DR
B is a distance register 4° LARA and LARD are logical address registers, RQA and RQB are request address registers J, and RQQA and RQQB are request queue buffers. PA and PB are boats, G is input gate, 17 people or 1
7B each indicates an address pipeline. The 210jF unit 15-A generates a logical address based on the contents of the base 9 address register BARA and the distance register JDRA. This logical address is set in logical address register LARA, the contents of logical address register LA0RA are translated into a real address by address translation circuit 16-A, and this real address is set in request address register RQAK. The request address output from the request-address register RQA is input to the request queue register RQQA. Request queue buffer 7
The request address output from RQQA is baud)
It consists of a priority part via a PA. Address vibe line 17-Ill 7-C, 17-
D has a similar configuration to 17-A. The address generation control unit 13-A controls block a/x
Y If performed, address pipeline 17-AV control is performed. In this case, the adder 15-A first outputs the base address BA'2. This is set in the base address register BARA. Below, base e address register BARA K 4
D1 - Set in one address register BARA. If block access is not possible, the address generation control unit 13-A controls the address generation control unit 17-A, 1
7-B, 17-C, and 17-D. Adder 15-A first outputs base address BA'. This is set in base address register BARA. Hereafter, the base address BA plus the ID is output. This is set in the base-address□ register BARB. below,
Base address. Register BARB plus 4D is output - this value is then set in the base address register BAIRJI. The adder of address pipeline 17-C first adds 2D to the base address BA, and σ
), and the adder of the address library y17-D first outputs the base address B2A multiplied by 3D. The subsequent processing is the same as that of address pipelines 17-A and 17-B. Figures 7(a) and 7(b) show part 1 of the main part of the address generation control section.
It is a figure showing an example composition. In FIGS. 7(a) and (b), 18A to 24A are registers, 18B to 2
4B is also a register, 25A and 25B are subtracters, 26-A and 26-B are decoders, 27 is a data continuity detection circuit, 2
8-A and 28-B are end detection circuits, 29 to 34 are A
ND circuits, 35 to 36 and 40 are OR circuits, and 37 to 39 are NOT circuits, respectively. First, explanation will be given from FIG.
It is sent to the main memory control device 2 as an RQ. register 23
-A holds the remaining vector length. Subtractor 2
5-A is a register 23-A each time an address is generated.
Subtract a constant from the contents of A. When the remaining vector length becomes zero, the end detection circuit 28-A turns PiPEBUSY A-
The P number PE signal is set to logic "0". The register 424-A holds the operation code OPC. register 24
The opcode held in -A is decoded by decoder 26-A, and the decoding result is stored in register 21-A.
and 22-A'(!-) to the main memory controller 2. The circuit on the B side is the same as the circuit on the A side. The data continuity detection circuit 27 is based on the contents of the distance register DRA. This circuit 27 outputs logic "mrlJ'&" when it detects data continuity (block cannot be accessed), and outputs logic "0" when data continuity [block - access is possible]. If the end detection circuit 28-A outputs logic [1] and the data continuity detection circuit 27 outputs logic [1], pLpg.
The BUSY n-ptpg signal becomes logic "L" - and when the end detection circuit 28-B outputs logic rlJ and the data continuity detection circuit 27 outputs logic rOJ, the PjPE BUSY B-PiPE signal becomes Logic "1"
”. When the data continuity detection circuit 27 is outputting the logic "L", the decoding result of the decoder 26-A is set in the register 421-H, and when the data continuity detection circuit is outputting the logic rOJ*, the decoding result of the decoder 26-A is set to the register 421-H. B
The decoding result is set in register 21-B. The contents of register 21-B are sent to main memory control device 2 via register J22-BY. The transmission of commands from the instruction processing unit 3 to the access pipeline 4-A is controlled by the PLPE EUSY A-PjPE signal, and similarly the transmission of commands from the instruction processing unit 3 to the access pipeline 4-B is controlled by the PIPEBUSY B-P.
Controlled by the iPB signal. piPE BUSY
When the A-PZPE signal is logic "1", the address generation control unit 13-A is in the BUSY state, and similarly, the K
PiPE BUSY B-When the PiPE signal is logic "1", the address generation control section 13-B is set to the BU8Y state. Therefore, for access when data is continuous, the 2nd PE BUSY A-PiPE signal and the
The iPE BUOY B-PIPE signal is generated independently by the corresponding access pipeline, and if the data is discontinuous, the PtPE BUOY A-PiPE signal and pipE BUSY B-PIPE signal are both i#U[1]. Then, Q access e from the instruction processing unit 3
Inputting instructions to pipeline 4-B is prohibited. When the register 18-A is detected as a start signal STA in the v-shill 18-A, the register 18-A is cleared. At the same time, the subtraction process by the subtractor 25-A and the holding of the operation code by the register 24-A are stopped so that the next instruction can be input. A similar operation is performed for the B-side θ) circuit. FIG. 7 1) shows the address pipeline 17-A. This is a part that controls the input gate, pace address register, distance φ register, etc. of each of 17-B and 17-C and 117-D. In some cases, the address pipeline 17-B is controlled by the address generation control unit 13-B, and the address pipeline 17-A is controlled by the address generation control unit 13-B. Part 13-A °C
controlled. When the signal (2) is "1" in 1a, the address pipeline 17-A. 17-fL 17-C and 17-D are all controlled by the at least one generation control section 13-A. Note that the circuit that generates the control signal is not shown in the seventh part, -). FIG. 8 is a diagram explaining the present invention in detail. Suppose we have a vector instruction sequence like the one below. ■ VLD (data 4I continuous) ■ VLD (same as above) ■ VLD (data discontinuous) ■ VLDt data continuous) ■ VLD (same as above) Note that VLD represents a vector load instruction. (U) The addresses necessary for executing the command are created by the address pipeline 17-A. At the same time, the address necessary to execute the instruction (2) is generated by the address pipeline 17-B. After the generation of an address for executing the instruction (2) and the generation of an address for executing the instruction (2) have both been completed, the address required to execute the instruction (2) is transferred to the address pipeline 17-A, 17-B, 17-C, 1
Generated by 7-D. Addresses necessary for executing the instruction (2) are generated by the address pipeline 17-H. [Effects of the Invention] As is clear from the above description, according to the present invention, vector loading can be performed without increasing the hardware load and relatively reducing throughput even when accessing data is discontinuous. It can execute instructions, vector store instructions, etc.

[Brief explanation of drawings]

Figure 1 shows the storage format of double-precision, single-precision, and fixed-point data in vector registers. Figure 2 shows the preferred way to load vector data to improve the execution performance of a vector data processing device. A diagram showing
FIG. 3 is a diagram showing an overview of a vector data processing device to which the present invention is applied, and FIG.
FIG. 5 is a diagram showing the configuration of an embodiment of the address section of the access pipeline, and FIG. 6 is a diagram showing the configuration of the address generation section of the embodiment. FIG. 7 is a diagram showing the configuration of one embodiment of the main part of the address generation control section, and FIG. 8 is a diagram illustrating the present invention in detail. 1... Main memory device, 2... Main memory control device, 3...
・Instruction processing section, 4-A and 4-B...Access pipeline, 5...Vector register% 6...Priority control circuit, 7...Address section, 8...Align control section , 9... Align circuit, 10... EC
C circuit, 11 and 12...control signal line, 13-A and 13
9-B...Address generation control unit, 14 and 14'...Address generation unit, BA...Pace address, D...
Distance, VL...Vector length, opc...Operation code, STA...Start signal for address generation control section 13-A, STB...Address generation control section 13
Activation signal for -B, 15-A and 15-B...adder, 16-A and 16-B...address conversion circuit, BA
RA and BARB...base address register x4.
DR), and DRB...Distance V9xi, LA
RA and LARB...logical address register 4. RQA
and RQB...request address register, RQ
QA and RQQB...11 quest queue e-buffer, PA! :PB...boat, Q...entering game),
17-A to 17-B...Address pipeline. Patent Applicant: Fujitsu Ltd. Representative Patent Attorney Yotsubu Kyotani 0 Years Old 1 Figure Z Diagram

Claims (1)

[Claims] In a vector data processing device having a plurality of independently operable access pipelines that perform transfer between a main memory and a vector register using one or more data buses, an address generation unit, and an address own bus, During continuous access to data that refers to data on the main memory, each access pipeline independently manages the address generation unit and address bus to issue accesses to the main memory and access the data. In the case of discontinuous accesses, any one of the plurality of access pipelines manages the address generator and the address bus to access the main memory. vector data processing device.