JPS6072372A - Picture signal supplying device - Google Patents

Abstract

PURPOSE:To reduce peripheral circuits and make the constitution of the device simple and miniaturize the device by providing a device that selects whether the operation is from a reading device or from a writing device and reducing the number of line memories. CONSTITUTION:Line memories 41a, 41b having capacity for two lines respectively are provided in a picture signal supplying device. Picture signals are received in a line memory controlling section 42 from data lines 43a, 43b, and necessary picture signals of the circle are supplied from output lines 44a-44c to a picture signal processing device 45. Write clock and read clock are outputted from the controlling section 42 to a write address generating section 49 and a read address generating section 51 through write and read clock lines 46, 47. The write address and read address generated by respective generating section 49, 51 are added to an address selector 53. Write operation or read operation is selected by a selector 53 to reduce the number of line memories and simplify the constitution of the device.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention is directed to an image signal processing device for supplying image signals to an image signal processing device that requires 8247 minutes of image signals, such as an encoding and compression device for a facsimile IJ device. This invention relates to improvement of a signal supply device.

[Technical background of the invention]

The conventional signal supply device for supplying both signals to the image signal processing device J, which requires 8247 worth of image signals, had a line meso for N or more images (one accumulation).

FIG. 1 is a state transition diagram of the line memory when tJ1, N23 and 1.7. Three lines of image signals used for image signal processing are read out from three line memories, and during this time the next image signal is loaded into another line memory.

State A of the first residence 1 is 3 line memories + 1 to fp3
This shows that the image signals for three lines are read out from , and the next two signals are written into line memory +4 at the same time. In this way, when the reading and loading of both signals are completed, the state moves to state J3, and the image signals for 3 lines are read out from the 3 line memories +2 to ≠ 4, and at the same time the line memory Add the next image signal to ÷1. From then on, states C, D,
The state changes to A, B, C, D, etc.

FIG. 2 shows a dual signal supply device for supplying both signals as described above.

In the configuration 11A of FIG. 1, the line memory control unit 1 performs address selection) +li112 a -1, 2b
With e12e, 3 line memories 4ay4b+4
c and the three address selectors 5a, 5b, 5c are switched to read operation, and the address select line 12
At step d, the line memory 4d and address selector 5d are switched to write operation. Furthermore, the line memory control section 1 provides a read clock to the read address generation section 2 via the read clock line 9, and provides a write clock to the write address generation section 3 via the write clock line 7.

As a result, the line memories 4a, 4b, 4c have memory address lines 11a, 1lb, 11e, respectively.
The addresses generated by the read address generation unit 2 are applied from the address selectors 5a, 5b, and 5c. Therefore, both signals stored in the line memories 4a, 4b, and 4c are outputted to the image signal processing device 6 in accordance with the address generated by the read address generation section 2.

On the other hand, the line memory 4d has a memory address line lid.
, the address generated by the write address generation section 3 is given via the address selector 5d. At this time, the line memory control section 1 applies a write pulse to the line memory 4d via the write timing line 13d.

As a result, the write address generator 3 of the line memory 4d
The image signal input via the image signal input line 14 is written to the address generated in .

In this way, the line memory control unit 1 outputs a write clock through the write clock line 7, a read clock through the read clock line 9, and sequentially increments the address. , line memo! When all the image signals in J 4a, 4b, and 4c have been read out and new image signals have been written to all addresses in the line memory 4d, the write address generation section 3 indicates the write end line 8. The read address generating section 2 outputs a read end signal through the read end line 10. Upon receiving these two operation completion signals, the line memory control unit 1 changes the state from state A to state B in FIG. 1, and the line memories 4b, 4c,
4d and address selector 5b.

Switch the signals of address select lines 12b, 12c, and 12d so that lines 5c and 5d perform read operations,
Further, the signal on the address select line 12a is switched so that the line memory 4a and address selector 5a perform a write operation. Similarly, the line memory control unit 1
Control is performed so that the state changes in the cycle shown in FIG.

[Problems with background technology]

However, according to both of the above signal supply devices, N line memories are required for storing and reading out image signals. was necessary. For this reason, the total number of line memories is N or more, and the number of peripheral circuits of the line memories increases, resulting in a disadvantage that the configuration becomes larger and more complicated.

[Purpose of the invention]

The present invention has been made in view of the drawbacks of the conventional image signal supply device as described above, and its purpose is to reduce the number of line memories, thereby reducing the number of peripheral circuits, and to miniaturize and simplify the configuration. An object of the present invention is to provide an image signal supply device that can be

[Summary of the invention]

Therefore, in the present invention, in both signal processing apparatuses that supply image signals to both signal processing apparatuses that require image signals for N247, a plurality of M line memories of N or less that can store image signals for a plurality of lines are provided. and reading means for simultaneously reading out both item numbers from one line area of each of the M line memories, and the above □ pieces. , i72. There are a lot of 2 □ pieces in the middle of the day. ,stomach.

The M line memories are provided with writing means for simultaneously writing 71 image signals into an area for one line of each memory, and selection means for selecting operation by the reading means or writing means. One after another mode! E or 111. The above purpose has been achieved by setting the mode to include mode.

[Embodiments of the invention]

FIG. 3 shows two lines that can store two lines of image signals to an image signal processing device that requires both signals of three lines (N=3).
FIG. 12 is a diagram showing the state transition of line memories when a picture number δ is supplied by a picture number 43 supplying device equipped with (M=2) line memories.

In the same figure, the line memory 10 is the line memory Φ1. in FIG. It corresponds to liner 3 and corresponds to liner 4. Also, line memory + 10 area for 1 line ÷ 1
0B is the line memory area in Figure 1, and the area for one line is also ◆10b is the line memory + in Figure 1
Corresponds to 3.

The area for one line of the line memorina 20÷20& is the first
Similarly, the area +20b for one line corresponds to the line memory +2 in the figure, and the area +20b for one line corresponds to the line memory +4 in the figure.

State A in FIG. 3 is the line memory Φ10. +20 1 line area ÷ 10a, ÷ 10b, indicates that an image signal is read from 20a and at the same time the next image signal is written to 1 line memory +20 1 line area +20b. In this way, when the reading and writing of the image signal is completed, a transition is made to the state S, and the line memory +10.
+20 one line area 10b, +20a, +20
The image signal is output from b, and at the same time, the line memory +10
The next image signal is written in the area corresponding to one line divided by 10a.

Thereafter, the state is changed to state C, D, A, B, C, D, . . . .

FIG. 4 is a professional diagram of the image signal processing device that transitions the state of the line memory as described above and supplies the image signal to both signal processing devices, and FIG. 5 is an operation timing diagram of this device. It is.

In FIG. 4, line memories 411 and 41b each have a capacity for two lines. Reference numeral 42 denotes a line memory control unit. The line memory control unit 42 receives image signals from the line memories 41&, 41b via data lines/43a, 43b, latches them, and outputs polished image signals to an output line 44. It is output to the image signal processing device 45 via a, 44 b, and 44 c.

The line memory control unit 42 also controls the write clock line 46
A write clock b as shown in FIG. 49 indicates a write address generation section;
The write address generator 49 outputs a write clock eta via the write address line 50 via the write clock line 46e.

Reference numeral 51 indicates a read address generation section, and when the read address generation section 51 receives a readout address f through the readout line 47, it outputs the readout address f as shown in FIG. 5f to the readout address line 52. Output via. Reference numeral 53 indicates an address selector, and the address selector 53 receives a select signal g as shown in FIG.
When this is high level, read address line 52
When the select signal g is at low level, the output address f is selected and outputted to the address line 55, and when the select signal g is at a low level, the write address e of the write address line 500 is selected and outputted to the address line 55.

The line memories 41a and 41b include an address line 55.
The write address or read address is given by
A select signal g is applied to the memories 41a and 41b via the most significant address lines 56a and 56b. 57b
A writing pulse is applied via the image signal sending source 58, and an image signal is applied serially from an image signal sending source (not shown) via the image signal sending source 58.

The line memory control unit 42 is a line memory 41a.

41b until the readout of the image signal of one line area or the store loading of both Shingei is completed, the highest address line 56
Fix the highest address that will last through a and 56b,
This address is then translated or fixed again in the line memory 41°a so that the state A described in FIG. 3 can be realized.

6) Cut 41b. In this case, the time to fix the highest address again is at the write address generator 49.
From 1 = read end signal given via write end line 59 and read address generator 51, read end l1T460
This is when the line memory control unit 42 receives the read end signal, which can be seen via the line memory controller 42. In addition, the line memory control unit 42 outputs [7] via the address selector 54.
When the selected signal is low level, the line memory 41
11. In order to write an image signal to one line of area of 41b, a write pulse is output to one of write timing 1p57g and 57b in synchronization with the timing of write clock b as shown in Figure 5. Strengthen. When the line memory control unit 42 receives the above write end signal and read end signal,
Of the write timing lines 57a and 57b, a write pulse is output to a write timing line that has not outputted a write pulse up to that point.
Control is performed so that writing can be performed from state to state.

In this way, this embodiment is composed of two line memos J41a and 41b that can store image signals for two lines, a line memory control section 42, and a read address generation section 51.
It consists of a reading means for simultaneously reading out both signals from an area for one line of each of the line memories 41a and 41b, a line memory control section 42, and a write address generation section 49. Area 1
writing means for writing an image signal into an area corresponding to one line;
An image signal ++ supply device 17 is constituted by an address selector 53 for selecting whether to operate by the reading means or not to operate by the writing means, and a selection means consisting of a line memory system t11 and 42. Then, by the select signal g outputted by the line memory control section 42 serving as the selection means, the line memories 41 A, 4 l B are simultaneously set to read mode or write mode (in write mode, line memory 41&,
.

The operation will be described below with reference to FIGS. 4 and 5. now,
The line memories 41a and 41b are made to correspond to the line memories $10 and 120 in FIG.
The area of the line memory ≠ 10 + 10& is made to correspond to the area of the line memory ≠ 10 + 10 &, and the address lower than half of the address of the line memory 41a (the highest address is the area 10b of the address of 10') Correspondingly, the area of addresses higher than half of the addresses of the line memory 41b is set as the area of one line of the line memory 2o 20a.
The line memory 41. An area of an address lower than half of the address of b is made to correspond to an area of one line of line memory divided by 20=lI=20b.

Then, in the state AK in FIG. Output. Then, fl of the read address f is outputted to the read address line 52 of the subsequent address generation section 51Fi. Next, the line memory control unit 42 outputs a pulse b of the write clock b via the write clock line 46. Then, the pull-in address generating section 49 outputs 01 of the u1-load address e to the write address line 50. In synchronization with the rise of the pulse bl,
The line memory control unit 42 outputs the select signal g to the address select line 54 at a high level.

The read address of line 52 is sent to address line 55.
In addition, the line memories 41 to 41b are set to read mode. With this, an electric area corresponding to the area for one line +10a in Figure 3 of the line memory 41a and an area for one line +10a in Figure 3 of the line memory 41b are created.
Image signals are outputted from the areas corresponding to , and are applied to the line memory control unit 42 via data lines 43 & 43b, respectively.

The line memory control unit 42 converts this into the pulse e1 of FIG. 5C.
At the timing of the falling edge of , the latch (indicated by the diagonal line in the fifth diagram) is latched, and the uppermost address lines 56a, 56
Outputs 0# at the rising edge 9 of the b-Hebals C1. As a result, when the line memories 41a and 41b are in the reading mode, the area corresponding to the area 10b for one line in FIG. 3 of the line memory 41a and the line memo Q4
An image signal is output from the area corresponding to the area amount 20b for one line in FIG.
3&, 43b to the line memory control unit 42.

The line memory control unit 42 outputs the already latched image in synchronization with the rising edge of the pulse d of the read clock d (indicated by the diagonal line in Figure 5). An image signal corresponding to the image signal read out in state A in FIG. 3 is extracted from the signal and output to the output line 44a.

It outputs to the image signal processing device 45 via 44b and 44c. Further, the read address generation section 51 receives the pulse dmt- of the read clock d, and the read address line 52
f of read address f to f! Output. The line memory control unit 42 sets the select signal g to a low level in synchronization with the rise of the pulse d2 of the read clock d. By this, the line memory 41a.

41b is placed in the write mode, and the address selector 53 outputs the write address on the write address line 50 to the address line 55. For this reason, line memory 4
Area Φ10 for one line in FIG. 3 for each of 1a and 41b
It becomes possible to write the image signal in the area corresponding to the clock pulse b and +20b, but the line memory control unit 42 writes the write pulse only to the write timing line 57b in synchronization with the clock pulse b of the write clock b. give. As a result, line memory 4
An image signal is written via the image signal input line 58 to the address of the address line 55 in the area corresponding to the area φ20b for one line in FIG. 3 of 1b.

Furthermore, at the same time as the rising edge of pulse b of write clock pulse b, the write address generator 49i passes through the write address generator 49i and outputs the write address e (De2) to the write address line 50. In synchronization with the rise of the pulse b of the input clock b, the line memory control unit 42 sets the left signal g to a high level.Then, the read mode and the write mode are repeated as described above.

From the areas of the line memories 41g and 41b corresponding to the 12-inch areas S10a, φ10b, and S20a in FIG.
all,. Both signals are read out. 1,4yl-f:IJ4
When the image signal is written in the entire area corresponding to the area for one line divided by 20b in FIG. Then, a write end signal is output from the write address generating section 49 via a write end line 59. The line memory control section 42 receives these two signals and makes a transition from the operation in state A to the operation in state B' in FIG. That is, the method of giving the address output to the highest address M56a, 56b is changed, a write pulse is given to the write timing line 57m, and the data lines 43a, 43b
The extraction method for extracting three image signals from among the image signals given by the image signal is changed.

Thereafter, in the same manner, states C and D shown in FIG.

The operation is repeated so that the state changes from A to B to C to D, and so on.

As described above, according to this embodiment, the number of line memories is reduced compared to the conventional image signal supply device shown in FIG. 2, thereby simplifying the peripheral circuitry and wiring.

Also, the timing shown in Figure 5 B! , in the conventional device shown in FIG. 2, if there is no starting or writing error, in this embodiment, the line memo, 41a, 41b is written according to the timing shown in FIG. 5, b and below.
can be accessed at regular intervals and can be read and written in exactly the same cycle as before.

In the embodiment, the number of line memories is 2, and each memory is for 2 lines, but 1/8247V
The object of the present invention can be achieved if the image signal requiring the ili signal is provided to the image processing device with the number of line memories being N or less.

Furthermore, although parts of both signals read from the line memory are deleted and provided to both signal processing devices, the present invention is not limited to this.

Furthermore, it is also possible to simultaneously write the image signal into an area corresponding to one line in each of a plurality of line memories, for example two or three out of four line memories.

〔Effect of the invention〕

As explained above, according to the present invention, the number of stray line memories is reduced. By doing so, it is possible to reduce the number of peripheral circuits and realize a p* image signal supply device with a compact configuration.

[Brief explanation of drawings]

Rabbit: 1 Figure 1 is a diagram showing the transition of the line memory access state due to conventional signal supply and setting, Figure 2 is a diagram of the conventional image signal supply device, and Figure 3 is the access state of the present invention. FIG. 4 is a diagram showing the transition period of the image signal supply device according to an embodiment of the present invention, and FIG. 5 is a timing diagram for explaining the operation of the image signal supply device of FIG. 4. . 41a, 41b...°Line memory 42...
... Line memory control section 45 ... Image signal processing device 49 ... Write address generation section 51 ... Read address generation section 53 ... Address selector substitute Person Patent Attorney Noriyuki Chika01 or 1 person) Figure 1 Figure 2

Claims (3)

[Claims] (1) Supply both signals to an image signal processing device that requires both signals for 8247 minutes ii! The i+compensation-bow supply device stores image signals for multiple lines, and simultaneously outputs both signals from an area of one line in each of the M plural line memories and the M' line memories within N or less. a reading means for reading data; a writing means for writing both signals into an area for one line of each of at most M-1 2,000-line memories among the M line memories; 4n:i
The M line memo IJ'e read mode or sleep mode is set. (2) Provide two □Ijimemories that can store both signals for two lines;
After performing the output mode for two cycles, the writing mode is performed for one cycle by the writing means, and by repeating this operation thereafter, image signals for three lines are supplied to the image signal processing device. An image signal supply device according to claim α). (3) Each one of the M line memories is read by the reading means.
The image signal according to claim (1), characterized in that the image signal simultaneously outputted by 1c% and h from the line area is supplied to the image signal processing device as is or after being partially deleted. □Feeding device.