JPS6070749A - Power chip package - Google Patents

Abstract

SEMICONDUCTOR CHIP PACKAGES HAVING SOLDER LAYERS OF ENHANCED DURABILITY Solder layers in a semiconductor chip package, which electrically interconnect conductors used to gain electrical access to the electrodes on the semiconductor chip, are subjected to a transverse compressive force in excess of about 2 pounds per square inch. The semiconductor chip package can thereby undergo a marked increase in the number of cycles of heating and cooling before it falls due to increased thermal resistance arising from structural degradation of the solder layers.

Description

DETAILED DESCRIPTION OF THE INVENTION Background of the Invention The present invention utilizes solder layers to electrically interconnect conductors used to gain electrical access to electrodes provided on a semiconductor chip. Related to packages for semiconductor chips such as:

More specifically, the invention relates to a package containing such a solder layer for a power semiconductor chip or a signal semiconductor chip.

“Signal” semiconductor chips like those used in digital clocks (
(discussed later), "power" semiconductor chips (hereinafter simply referred to as power chips), during operation, typically
Generates more than watts of waste heat. This heat must be removed so that the chip does not become overheated and damaged. In order to remove waste heat from the power chip, a typical power chip package in the past has a metal substrate on which the power chip is thermally mounted, i.e., has a high thermal conductivity. The substrate is mounted on a metal heat sink, typically having a larger surface area than the metal substrate, for rapid heat dissipation.Power To provide electrical access to the chip, a metal core wire is connected via a solder layer to an integrally formed electrode provided on the upper side of the power chip, for example.

If there are further electrodes integrally formed on the top surface of the power chip, they are also connected to respective further conductors via respective solder layers. If the power chip is mounted on a metal substrate via a dielectric plate to electrically isolate the chip, the electrode integrally formed on the underside of the power chip should be attached via a solder layer in the same way. Conversely, the metal substrate itself can act as an electrical conductor if a power chip is directly connected to it.

The typical operating cycle of a conventional power chip package includes heating (while conducting) and cooling (while non-conducting), during which the solder layers of the package are subject to mechanical stress. It will be done. This is because metal substrates (typically made of copper) tend to expand and contract to a greater degree with heat than power chips (typically silicon). Therefore, after repeated thermal cycling of a power chip package, the solder layer becomes structurally degraded and therefore becomes less efficient in transporting waste heat away from the power chip. As the power chip package continues to undergo thermal cycling, the solder layer
It deteriorates to the point where waste heat can no longer be properly carried away from the power chip, resulting in overheating and damage to the power chip.

Signal semiconductor chips (hereinafter simply referred to as signal chips) typically undergo thermal cycling during use.

Signal chips are sometimes used in aircraft, for example, near the fuselage. On the ground, the temperature of such a signal chip is about 10
It can reach 0°C, whereas at altitudes of 70,000
At 0 fhi 1 ~, the temperature of the chip is typically about -40
It is ℃. These thermal cycles cause the solder layer used in typical conventional packages containing signal chips to
It is assumed that mechanical stress is applied. The conductor of the signal chip support on which the signal chip is attached is connected by the solder layer.
It is typically connected to the conductors of a printed wiring board containing multiple signal chip carriers. At this time, the mechanical stress exerted on the solder layer causes early failure of the signal chip package due to mechanical deterioration of the solder layer.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a power chip with enhanced durability of the solder layer, which is used as an electronic chip package in which electrical conductors are attached to the power chip through a solder layer.・Providing a package.

Another object of the present invention is to provide a power chip that includes a power chip that can operate at higher current levels after a longer number of thermal cycles than similar power chips in conventional power chip packages. It is to provide a package.

Another object of the present invention is to provide a signal chip package of the type having a solder layer, a signal chip support, and a printed wiring board, the solder layer having increased durability.

Briefly, in a power chip according to an embodiment of the present invention, a power chip package has a metal substrate, and a power chip is bi-thermally mounted thereon. It also has a housing attached to the board that at least partially encloses the power chip. A plurality of electrical conductors connect the power chip to provide external electrical access to the power chip. are connected via respective solder layers to electrodes integrally formed with the power chip package.
Applying a lateral compressive force exceeding ``rl square'' to the solder layer L
[I have the means.] A solder layer that receives such lateral forces has significantly increased durability. Suitable pressure means for exerting a lateral compressive force on the solder layer may consist of elastic means, such as springs, for example.

In a preferred embodiment of the invention for a signal chip, the signal chip package includes a printed wiring board having a plurality of conductors and a signal chip having a plurality of conductors and disposed above the printed wiring board. It has a support. A plurality of solder layers are disposed between the printed wiring board and the signal chip support to respectively electrically connect the conductors of the signal chip support to the conductors of the printed wiring board. Pressure means, such as a spring, engages the signal chip support and the printed wiring board to signal a compressive force sufficient to cause a lateral compressive force in excess of about 2 pounds per square inch to be applied to the solder layer. Add between chip support and printed wiring board.

Although the gist of the invention is specifically and clearly described in the claims, other objects and advantages of the invention will be better understood from the following description of the drawings.

FIG. 1 shows a partial cross-sectional view of a power chip package 100 of the present invention. The package 100 includes a metal substrate 102, preferably made of copper, and a housing that connects the substrate 102 at an interface 106, such as with epoxy (not shown).
Preferably one boxy housing 104 fixed to two
and has. Preferably, the interface 106 is provided in the well portion 108 of the substrate 102.

Fixed to the top surface of the substrate 102 is a power chip 112, such as a diode, with integrally formed upper and lower electrodes 114,116. Preferably, the lower electrode 11G serves as a molybdenum or tungsten support plate for the power chip 112 to protect the power chip 112 from strain and cracking. The commercial chip 112 is coupled to the substrate 102 by a solder layer 118. Solder layer 1
18 is electrically conductive so that the substrate 102 is electrically live and constitutes an electrical conductor or terminal of the power chip package 100.

The upper conductor or terminal 120 of the package 100, preferably made of copper, has a generally planar, sturdy plate-like portion 122, with a shaft portion 124 integrally attached to the plate-like portion 122, It then extends vertically upwardly through a slot 126 in housing 104 . The upper terminal 120 is connected to the power chip 1 by a solder layer 128.
It is electrically connected to the upper electrode of 12. The thickness of the solder layers 118, 128 is exaggerated for clarity.

In this invention, the spring 130, preferably made of steel, is attached to the shaft portion 12.
4 in a generally helical manner, with its upper end 132 abutting the housing 104 and its lower end 134 abutting the plate-like portion 122. The spring 130 acts to transmit a lateral compressive force through the plate portion 122 to each of the solder layers 118, 128. Preferably, this force is perpendicular to the respective solder layer 118,128.

Preferably, the lateral compressive force thus applied to the solder layer 118,128 has an magnitude greater than about 2 pounds per square inch.

Preferably, the upper end 132 of the spring fits into a downwardly opening recess 136 in the housing 104 to maintain the spring 130 in alignment with the shaft 124.

Although the shank 124 is shown as generally filling the inner diameter of the spring 130 near the lower end 134 of the spring, thus helping to keep the spring 130 aligned, it will be appreciated by those skilled in the art that the shank 124 Other methods of keeping the values consistent with each other may also be considered.

In order for the spring 134 to be effective in producing the desired lateral compressive force, the shank 124 of the upper conductor 120 is movable vertically relative to the slot 126 in the housing 104. Should. In another configuration (not shown), the plate portion 12 of the upper conductor 120 of the shaft portion 124
2 and the upper portion of the housing 104 comprises a flexible conductive member, such as a braided copper conductor. An alternative configuration such as this allows the upper portion of the shaft 124 to be secured to the vortex hole 126 of the housing 104.

When a lateral force is applied as described above, the solder layer 118
．． 128 is more than when there is no such lateral compressive force.
Durability increases significantly. While not intending to be bound by the following discussion, such lateral compressive forces on the solder layers 118, 128 can be applied to the solder layers 11 during thermal cycling.
It is believed that the shear forces acting on the solder layer 118.128 act to prevent cracks from forming in the solder layer 118.128 in the shear or horizontal direction. These shear forces are caused by the fact that the metal substrate 102 and plate portion 122, both of which are typically made of copper, expand and contract to a much greater degree with heat than the power chip 112, which is typically made of silicon. It is thought that Alternatively, it is believed that even if such shear strain cracks occur, the lateral compressive force applied to the solder layer 118 will help anneal or repair such beak cracks when the solder layer cools from the high operating temperature. It will be done.

It has been found that the greater the lateral compressive force on the solder layer 118,128, the more durable such solder layer is. The primary parameter that indicates the durability of the solder layers 118, 128 is the value of the thermal resistance of the power chip package 100 as measured from the power chip 112 to the terminals 102 of the board. During the thermal cycle, the solder layer 118.
As 128 deteriorates structurally, the value of this thermal resistance increases. The increase in thermal resistance of power chip package 100 as a function of the number of thermal cycles experienced is graphically illustrated in FIG. 2 for various lateral compressive loads on solder layers 118, 128. .

The thermal resistance in FIG. 2 is normalized to 1 when the thermal cycle is zero. Each thermal cycle holds the power chip package 100 at -40°C for 0.5 hours;
The temperature is kept at 140°C for an hour. Figure 2 shows an example of what is typically experienced in reliability testing of power chip packages.
Power chip package for hundreds of thermal cycles1
It shows a thermal resistance of 0.00 C. In curve A of FIG. 2, when there is no external load on the solder layer 118,128, the power chip
It can be seen that the thermal resistance of package 100 reaches a normalized value of 8 after 800 thermal cycles. However, curve)
3. In C and D, 5.12 and (f 23 real/square 040) orthogonal lateral compression no. J are applied to solder layer 1, respectively.
18.128 multiplied by 14, the thermal resistance of package 100 only reaches a normalized value of 4 or less.

From this data shown in FIG. 2, it is reasonable to estimate that a significant increase in the durability of the solder layer 118, 128 can be obtained with a lateral compressive load of only about 2 bonds/square inch. Furthermore, it can be seen in FIG. 2 that the stronger the load on the solder layers 118, 128, the smaller the observed increase in the thermal resistance of the package 100. However, to obtain the most economical power chip package, the solder layer 118.
Preferably, the maximum compressive load for 128 is approximately 50 pounds per square inch.

FIG. 3 shows a power chip package 30 of another embodiment of the present invention particularly suited for large area power device packages.
0 is shown. Package 300 has a metal substrate 301, preferably made of copper, and a housing 302, preferably made of epoxy. Housing 302 is bolt 3
03.304, and is fixed to the substrate 301 using any suitable bonding means such as a well 305 of the substrate 301.
It is preferable to fit in.

A power chip 306 is enclosed within the housing 302 . This electronic chip includes, for example, a pair of base electrodes 310 on the left and right sides of the chip 306. 312 respectively constitute an integrally formed upper electrode IMi 3 (18) and a power Darlington transistor with an emitter electrode 314 disposed therebetween. In addition, a power chip 306 forms the collector electrode 4M. It has an integrally formed lower electrode 316.

The collector if4316 is made of a dielectric plate 31 made of ceramic beryllium oxide or alumina with high thermal conductivity.
8, electrically isolated from the substrate 301. The exterior of the housing 302 is provided with an electrical conductor or terminal 320 for making electrical contact with the collector electrode 316. The conductor channel 320 includes a sheet metal 322, such as copper, a portion of which is preferably is bonded to the top surface of dielectric plate 318 by using a eutectic bonding method. This bonding method is known as "direct bonding" and is disclosed in U.S. Pat. No. 3,766.634 and U.S. Pat.
It is described in No. 30. Dielectric plate 318 is connected to substrate 301 as shown, preferably by a layer 32G different from gold B layer 323, such as a thin copper plate bonded directly to the underside of dielectric plate 318. Instead of this, the dielectric plate 318
may be epoxied directly to the substrate 301.

Additionally, the conductor structure 320 also includes a terminal post 328.

This terminal post is made of a thin metal plate 3 by using a solder layer 330 or the like.
22 and are connected to a dielectric plate 331 and upper and lower thin metal plates 33 preferably composed of copper in direct bond.
It is electrically isolated from the substrate 301 by 2.333. A solder layer 334 connects the pillar 328 to the upper sheet metal 332, and a solder a 336 connects the pillar 328 to the lower sheet metal 33.
3 is connected to the board 301.

The upper base electrode 310 of the power tube 306 is electrically connected to the metal sheet 338. This thin plate preferably comprises a copper substrate bonded directly to the underside of dielectric plate 340. A slat 338 is connected to a terminal post (not shown) that is similar to post 328 but has a lower current carrying capacity than post 328. Base electrode 310 is electrically connected to metal sheet 338 by solder layer 342 .

The upper base electrode 312 and emitter electrode 314 of the power chip 306 are electrically connected to the metal sheets 344 and 346, respectively. Preferably, both sheets are similar to sheet metal 338. The thin metal plates 344 and 346 are connected to the pillar 328.
Base and emitter terminal posts similar to (not shown)
are connected to each. The base terminal pillar has a smaller current capacity than the pillar. Base electrode 312 is connected to sheet metal 344 by solder layer 348, and emitter electrode 314 is connected to sheet metal 346 by solder layer 350.

Lateral compression is applied to all solder layers above and below the chip 306 (ie, layers 324, 326, 342, 348, 35o). This is accomplished by placing a rubber-like material 352 (partially shown broken away), such as a room temperature cure silicone rubber, into the housing 300. This material fills any voids within housing 302. This lateral compression on the solder layer constitutes static pressure. This static pressure can have two separate causes. First, the housing 302 is somewhat overfilled with rubber-like material 352 and allowed to cure before securing the housing 302 to the substrate 301. Second, the rubber-like material 352 is
While the temperature of power chip package 300 increases, it can be chosen to expand at a higher rate than housing 302. Therefore, the static pressure within the housing 302 increases as the temperature rises.

In the present invention, it is preferred that the rubber-like material 352 expand at a higher rate than the housing 304 while the temperature of the package 300 increases. This is because greater lateral compression is applied to the various solder layers at higher temperatures, where the shear stress on the solder layers is greatest. As with package 100 (FIG. 1), the lateral compression applied to the solder layers within power tip package 300 above and below power chip 306 is preferably greater than about 2 pounds per square inch.

Including dielectric plate 340 in power chip package 300 is advantageous in that it provides more uniform lateral pressure applied to upper solder layer 342, 348, 350. This means that the dielectric plate 340 is directly bonded to the thin metal plate 338.
This is because together with 4.346, it constitutes an overall planar and sturdy structure.

It will be appreciated that in the power chip package 300, the solder layers 330, 334, 336 associated with the lead structure 320 are also subjected to lateral compressive forces due to the presence of the rubber-like solder 352 within the housing 302.

For this reason, this kind of solder layer is located above and below the electric horn chip 306 and does not receive the same thermal stress as the solder that is heated due to power consumption in the power chip 306, but the durability of this kind of solder layer is strengthened. .

FIG. 4 shows a power chip package 400 of another embodiment of the invention. The package 400 includes a metal substrate 401 such as copper, preferably a well portion 40 of the substrate 401.
3, the housing wall 402 is fixed to the substrate 401 using an epoxy (not shown) or the like, and preferably a groove 405 in the wall 402, using a 1 boxy (not shown) or the like. It has a housing cover 404 secured to the housing wall 402. The conductor structure 420 fixed to the substrate 401 is connected to the electrical chip package 300 (
3), and for this reason parts of the conductor structure 420 are labeled with reference numerals in the 400 range, corresponding to the 300 range of the reference numerals in FIG. What has been described for each portion of conductor structure 320 also applies to the portions of conductor structure 420 with reference numerals incremented by 100. Similarly, power chip assembly 460 within housing 402,404 also includes the power chip assembly 460 shown in FIG.
It is similar to the power chip assembly 360 of the package 300, and therefore the components of the assembly 460 are numbered 400, but with reference numerals corresponding to the 300 reference numeral in FIG. What has been described for each part of assembly 360 also applies to the parts of power chip assembly 460 with reference numerals incremented by 100.

In power chip package 400, block of material 4
62 is provided to connect solder layers above and below the power chip 406 (i.e., solder layers 424.426.442.448.450
) is provided to apply a lateral compressive force to the Preferably, the upper portion of the block 462 snaps into a quadrilateral 464 on the underside of the housing cover 404 to maintain alignment of the block. Block 462 is constructed of a material such as nylon or Teflon (polytetrafluoroethylene) that has a larger coefficient of thermal expansion than housing wall 402. For this reason, the power chip package 400
When the block 462 is heated, the housing wall 402
51 expands, thus increasing the lateral compressive force applied to the upper and lower layers of power chip 406. When the electric horn depth package 400 is assembled, block 4
62 is preferably preloaded, ie, pressed downwardly, by housing cover 404.

As with power chip package 100 (FIG. 1), it is preferred that the minimum lateral compressive force applied to each solder layer above and below power chip 406 exceeds about 2 bonds/square inch.

FIG. 5 shows a power chip support 5 according to another embodiment of the present invention.
00 is shown. The support body 500 is the package 40
0 had a block 462, but instead a spring 5
In other words, the power chip support 40
It is appropriate that the structure be the same as that shown in Figure 4). This applies a lateral compressive force to the solder layers above and below the power chip 506. To this end, various parts of package 500 are labeled with reference numbers in the 500 range using the same last two digits as the 400 reference numbers in FIG. (Aside from the block 462 of the ``feedback''), what has been described with respect to each part of the power chip package 400 also applies to the parts of the power chip package 500 with reference numerals incremented by 100.

Spring 570 advantageously fits into a recess 572 in the underside of housing cover 504 to maintain vertical alignment of the spring. The lateral compressive force exerted by the spring 570 on the upper and lower layers of the power chip 506 is transmitted through the dielectric plate 540 to these solder layers and may exceed approximately 2 pounds per square inch. preferable.

When making the power chip packages described above, it is preferred that the housings of the packages are each constructed of epoxy and that the housings are secured to the respective substrates by an epoxy adhesive. In this invention, both the epoxy housing and the epoxy adhesive are of a type that can be cured by holding at room temperature (i.e., about 24°C) for 24 hours, or by holding at 50°C for 1.0 hour. Preferably, it consists of an epoxy of the type obtained. In the present invention, each solder layer is preferably comprised of a "soft" solder, ie, a solder having a melting point below about 400°C. As an example, the appropriate value is /V, lead 9
2.5% tin, 5% tin, and 2.5% silver.

151 lead-tin solder.

FIG. 6 shows a portion of a signal chip package 600 in partial cross-section. The illustrated portion of the package 600 constitutes one quarter of the complete signal chip package, and the quarters shown in the drawings are approximately the same as the quarters shown. Printed wiring board 602 with a dielectric body 604, typically made of plastic
and a plurality of printed conductors 60G provided thereon.

The package 600 further includes a signal chip support 608 having a dielectric body 610, typically made of ceramic, and a plurality of conductors 61, typically of thick film configuration, disposed thereon.
It has 2. The signal chip support 608 is the main body 6 of the support.
A battlement or recess 61 is provided at the periphery where the 10 inner conductors 612 are arranged.
You can have 3. A signal chip support 608 supports a signal chip 614 and a wire coupling 616 interconnects an electrode 618 of the signal chip 614 with a conductor 612 of the chip support 608, suitably in a conventional configuration. do.

A plurality of solder layers 620 disposed between the signal dip support 608 and the printed wiring board 602 connect the chip support 608.
The conductors 612 of the conductors are electrically connected to the conductors 606 of the printed wiring board 602, respectively. A solder layer 620 is shown filling a portion of the battlement 613. This is the solder layer 620
helps visually detect the presence of Solder layer 620 is preferably comprised of a soft solder (as previously described). Chip support 608 and printed wiring board 6
Pressure means 622 engaging the signal chip support 608 and the printed wiring board 602 compress the support 608 and the printed wiring board GO2, thereby compressing the solder layer 620 at least directly between the signal chip support 608 and the printed wiring board 602. , applying a lateral force. An example pressure means 62201 is shown in detail in FIG. 7, taken from arrow 7-7 in FIG.

In FIG. 7, the pressure means 622 in this example includes a hole 610H provided in the body 610 of the chip support and a body 60 of the printed wiring machine.
The hole 604H provided in the bolt 627I is inserted through the hole 604H provided in the bolt 627I.

Hole 6041-( is chip support 608 and printed wiring board 6
Pol h such that the vertical alignment of 02 is determined by solder layer 620 and not by Pol 1-624.
It is preferable that the size is sufficiently larger than 624. In this way, the chip support 608 and the printed wiring board 60
Some relative movement in the horizontal direction is possible between the two. Spring 6
27 is wound helically around the bolt 624, and the main body 604 of the printed wiring board is biased in the opposite direction from the washer 17 G26. As a result, the compression horn is transmitted to the washer 627 via the bolt 624, and presses the main body 610 of the chip support and the main body 604 of the printed wiring board. In this way, solder layer 6
22 is subjected to a lateral compressive force, which should be in the same range as the lateral compressive force applied to the solder layer of the power chip package previously discussed. That is, in excess of about 2 pounds per square inch, the maximum value is preferably about 50 bonds per square inch to produce the most economical signal chip package 600.

As an alternative to the indenter 622 in this example, one end of a spring clip (not shown), made of a slightly curved strip of spring steel, may be attached to the printed circuit board 602 with a screw or the like, and the other end Unbiased pressure can be applied so as to press it downward against the signal chip support 60&.

Other suitable materials for constructing the splash clip include:
Examples include bronze and copper-beryllium alloys.

The above is a semiconductor chip with a solder layer that has increased durability.
This describes the package. In power chip packages, this is advantageous because it allows smaller area power chips to conduct more current than previously possible.

This is because the power chip package of the present invention reliably extracts high levels of waste heat from the power chip even after multiple heating and cooling cycles.

In signal chip packages, this is advantageous because it results in increased durability after multiple heating and cooling cycles.

Although the invention has been described with respect to particular embodiments, many modifications will occur to those skilled in the art. For example, hybrid semiconductor chip packages that package both power and signal chips can also be made in accordance with the present invention.

It is, therefore, to be understood that the following claims are intended to cover all possible modifications within the scope of this invention.

[Brief explanation of drawings]

FIG. 1 is a schematic cross-sectional view of a portion of the power chip package of the present invention, with solder debris being shown on an enlarged scale. FIG. 2 is a graph showing the thermal resistance of the power chip package of FIG. 1 versus the number of thermal cycles experienced by the package; FIGS. A diagram showing the package similar to Figure 1;
FIG. 6 is a schematic cross-sectional view of a portion of the signal chip package of the present invention, with solder debris being greatly enlarged. FIG. 7 is a detailed view of the pressure means of the signal chip package of FIG. 6, taken from arrow 7--7 in FIG. Explanation of main symbols 102: Board, 104: Housing, 112: Power chip, 114: Solder layer, 120: Conductive wire, 130: Spring. patent applicant

Claims (1)

[Claims] 1) A power chip package having a solder layer with enhanced durability, comprising a metal substrate and a plurality of integrally formed electrodes thermally attached to the substrate. a housing fixed to the top surface of the substrate and at least partially enclosing the power chip; at least one electrical conductor 9 extending from the interior of the housing to the exterior of the housing; a solder layer within the housing for bonding the conductive wire to one of the plurality of electrodes; and a solder layer within the housing for bonding the conductor to one of the plurality of electrodes;
pressure means for applying a lateral compressive force to the solder layer in excess of . 2. A power chip package as claimed in claim 1, wherein said pressure means is operative to apply a maximum lateral compressive force to said solder layer of about 50 bonds per square inch. 3) The power chip package according to claim 1), wherein the lateral compressive force is perpendicular to the first solder layer. 4) In the power chip package according to claim 1), the pressure means is constituted by an elastic means biased to apply a lateral compressive force to the layer at /υ. Current electronics chip package. 5) The Ic power chip package as claimed in claim 4, wherein said elastic means comprises a spring C'. 6) The power supply package according to claim 4) has a generally planar rigid structure adjacent to the solder layer, and the elastic means is arranged to extend through the rigid structure. A power chip that applies lateral compressive force to the /v layer.
package. 7) In the power chip package according to claim 1), a shaft portion passes upwardly through the housing in a manner such that the electrical conductor is connected to a sturdy temporary portion and forms a terminal post. and the pressure means comprises a spring wound generally helically around the shaft, a lower end of the spring is applied to the plate-like portion, and an upper end of the spring is applied to the housing. Power chip package dedicated to. 8) The power chip package according to claim 1), wherein the pressure means comprises a block of material interposed between the housing and the solder layer; has a larger coefficient of thermal expansion than the housing, so that when the power chip package is heated, the block thermally expands more significantly than the housing, thereby applying lateral compression to the solder layer. Power chip package. 9) A power chip package according to claim 8, having a generally planar rigid structure adjacent to said solder layer, said block of material being connected to said solid structure through said rigid structure; Power chip packages that apply lateral compressive forces to the solder layers. 10) In the power chip package according to claim 9), the generally planar 1" length structure comprises a ceramic plate having a metal layer bonded thereto and adjacent the solder layer. 11) The power chip package according to claim 8, wherein the block of material is made of nylon or Teflon resin. 12. Patent In the power chip package according to claim 1), if there is a substantial void in the housing, the pressure means is comprised of a rubber-like material that fills the void and the solder layer 13) In the power chip package according to claim 12), the rubber-like monthly charge is made of silicone rubber. Chip package. 14) In a signal dip package having a solder layer with enhanced durability, a printed wiring board having a dielectric body and a plurality of conductors printed on the body, and a dielectric body and the body a signal chip support disposed above the printed wiring board; a signal chip support disposed between the printed wiring board and the signal chip support; a plurality of solder layers electrically connecting conductors of the signal chip support to conductors of the printed wiring board, respectively; 15) A signal depth package according to claim 14, wherein said pressure means has a pressure of about 50 bonds/square inch. acting so as to apply a maximum lateral compressive force of ° to the solder layer.
Tsuru signal chip package. 16) The signal chip package according to claim 14, wherein the dielectric body of the signal chip support is made of ceramic. 17) In the signal chip package according to claim 14), the pressure means is constituted by an elastic means biased so as to press the signal chip support and the printed wiring board, and The result is a signal chip package in which a lateral compressive force is applied to the solder layer. 18) The signal chip package according to claim 17, wherein the elastic means is constituted by a spring.