JPS6069987A - Recording and reproducing system of video format signal - Google Patents

Abstract

PURPOSE:To relax the tight requirement of high speed processing of a control signal relating to information by inserting and recording the signal before at least one frame of a corresponding frame. CONSTITUTION:A horizontal scanning line constituting one field in a video format signal is divided into plural blocks and a digital signal of sound information and picture information are inserted to the 1st block. The content of information of the 1st block and the control signal relating to the signal processing are inserted to the 2nd block. Furthermore, the control signal corresponding to the 1st block is inserted to the 2nd block before at least one frame of a frame to which the 1st block is inserted. Since the time to decode the control code and to process the signal is used sufficiently at reproduction in this way, it is not required to use an element with high speed response.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a recording and reproducing method for video formats 1 and 4, and in particular to a method for recording and reproducing image information and 74 information as Piano 4-mat signals on a recording medium. Rir.

When audio information corresponding to image information is recorded on a recording medium together with image information, audio information is inserted into a part of the video A) A-Matsulf in the time axis F, and image information is inserted into other parts. In this case, the insertion position of the audio digital data, the content of that data, and various control signals regarding the playback process related to the data are also inserted at predetermined locations in the video format signal. This control signal is inserted in the same field (or same frame) as the digital data that is processed in parallel with this control signal.For this reason, the control signal is read and its contents are processed at high speed. It becomes necessary to decipher and process each C signal, and the control signal tegorde and signal processing circuit are required to have a circuit configuration that operates at high speed. (circuits) etc., and require elements that are difficult to integrate at high density.

Historically, control signals can only be recorded in the odd-numbered field, which is the first field of the upper frame, due to signal processing, so the recording capacity of the control signal is small and must be recorded in a short period of time. Therefore, it becomes difficult to add an effective error correction code, and the transmission of the correct control signal becomes impossible.

Therefore, the present invention is designed to perform high-speed processing of two-in-one roll signals that are inserted into a certain frame and record a second roll signal that is inserted into a certain frame at least one frame before that frame. A)
A--Ck provides a method for recording and reproducing the results.

The recording method of the video 7A-Matsu 1 signal according to the present invention is to divide the horizontal scanning lines into a plurality of blocks, and divide the horizontal scanning lines into a plurality of blocks. etc. are digitized digital gates or (and n), and the contents of the information f inserted in the first block and the information immediately related to f are inserted into the second block. The roll signal is φ, and the control signal corresponding to the first block is inserted into the second block of at least one frame of the inserted frame. Characteristics.

During playback, the controller performs playback processing, and processes the information inserted in the frame following the inserted frame of the control signal in turn. shall be.

The present invention will be described below with reference to the drawings.

FIG. 1 is a diagram illustrating the principle of the present invention in detail, and shows the number of horizontal scanning lines (corresponding to an effective screen) of a signal equivalent to one field of a video format signal at the time of recording.

Divide into arbitrary plural blocks b, c,.

In particular, a, b, and c are made up of integer horizontal scanning lines, and furthermore, the number of horizontal scanning lines of C is divisible by a predetermined integer X, and the relationship m=c/X (m is an integer) is established. It has become. Therefore, C is composed of m pieces c1 to c
It is divided into X subblocks up to x. Note that Q is not necessarily an integer.

Figure 2 shows a part of the video format 1/8 shown in Figure 1. Figure (A) shows images in blocks C and Q, and Figure <B) shows digital data in block C. This is a recorded example waveform. Figure 3 shows N'a, b, C in the SC signal.
, Q is a diagram showing specific numerical values of an example of division of 1) r
- Red scan line 262.5, right-handed scan line 241.
In addition, the numbers a and b are set so that they are outside the visible range of the television monitor screen 1. In this example, a
=1. b=4. c=234. x=9, m=26, Q=2
．． 5 and there is F.

Here, if a digital gator is used as a dwarf in b and c, interleaving is applied to prevent consecutive errors from occurring even if errors are concentrated in drop-aper 1, etc., and error detection and correction is possible. A correction code is added, but in this example b
Interleaving and error correction blocks are completed independently. Similarly, even if J is in C, C
The signals up to +-CX are each independent, and C interleaving j and error n■ are completed.

FIG. 4 is an example of inserting j initial data on one horizontal scanning line, and 2-evening slate 1408f+(fx
A clock run-in signal is inserted before the digital data. Further, following this signal, a data synchronization signal for data synchronization is inserted by several pins. Following this data synchronization signal, a C data word and an error detection and correction code are inserted.

Figure 5 shows various recording modes. In (A), only the image is inserted into blocks C and C, and since blocks a and b are outside the visible range, they are not the same as the regular TV image. The display will be similar. (B) is the result in which all the C digital data is inserted into the C block, and (C) is the result in which the digital data is inserted into Ql, C, , C8, and C9 of the block C divided into 9 parts. Images are inserted into C7. (D) is an example in which digital data is inserted into knob blocks C, C, and images are inserted into 03 to C9, and (E)
is sub-block C! An image is inserted into ~C7, and digital data is inserted into cB and c9, respectively.

In FIG. 6, there is a frame (field 1) in which digital data is inserted into block C, which continues for a period Al.

This is several frames to one frame, depending on the required data. Also, in the subsequent period B, Cb [
All posts have images inserted. Usually, images corresponding to the data entered in period A are stored here, and whether it is a still image or a video that has been moved frame by frame (it is good,
Even in still images, the same image may be recorded for several frames in order to prevent image crosstalk between adjacent frames.

Figure 7 shows the resolution of C block (4.c9).
There is an example C in which digital data is inserted into blocks 02 to C8, and images are inserted into blocks 02 to C8, respectively, for a continuous period A of several frames, and in the subsequent period B, only images are inserted into blocks C.

In this case, a part of the screen becomes distorted during the period, and both images are not interrupted.

Figure 8 is a diagram of the recording system for obtaining the video A/A-1 signal using the recording method of the present invention. .This digital word has a rimbling frequency f+
(R) Buffer memory 81 for 5-axis compression
written to.

Reading from the memory ε1 is performed at a frequency f2(W) higher than fl(R), thereby compressing the I axis. In addition to the above-mentioned clock run-in and data synchronization signals, the I-roll signal, which is control information, includes the capacity of the information in each block and various processing information used when reproducing the information. The video signal is a digital data signal including audio data compressed in the time axis by the buffer memory 81, and the control information is transferred to the switching circuit 82.
are entered respectively. Since the selection operation of the switching circuit 82 is now controlled by the timing signal generator 83, the timing signal generator 83 also controls the purposeful reading of the memory 81. The timing signal generator 83 outputs the same J signal of the input video signal.
An internal oscillator is synchronized with the signal, and various timing signals are generated in response to external control signals. The output of the switching circuit 32 is recorded.
7A-Pine 1E will be placed on the condyle 5.

FIG. 9 is an I8 block diagram of a general Sho++ production system. The reproduced video signal A-Matsu 1 is separated into a synchronizing signal and 5-initial data by a signal valve N unit 1, and further separated into audio data and control data from the back of the initial notator. The timing signal generator 2 generates timing signals Y such as the output pulse f2 (W) and the advance pulse 11 (R) based on the J signal. Error detection and correction of the control data is carried out by an error correction Z4, which is decoded by a single-roll code decoder 6 and sent to a system control generator 7.

Further, the digital data is written into the memory 5 via the error corrector 3 with a pulse of l2(W), and is written as fl(R).
The time axis is expanded by reading out the pulse with the following pulse. In addition,
The error correction of Geishitalnota may be configured to be performed after the inter-verse axis expansion process.

This i-digital notebook whose time axis has been expanded is a digital notebook.
It is converted into an analog signal by an analog transformer 9 and becomes a reproduced A-D signal.

Decoded by the control decoder 6, various control signals are generated from the system control generator 7 according to each control command, and the J raw video A signal is generated via the screen processor 8 which operates according to a predetermined control signal. derived. That is, for the digital data insertion block, for example, the image is processed as a black level and output.

In addition, a control signal is derived from the play 7 controller 10 to control the playback operation of l)P (video disc player), such as stopping the VD, 1LAY, etc.
etc. control.

As described in Fig. 1, the first block a in one field contains several sets of horizontally scanned data consisting of a clock run-in signal for clock synchronization and data synchronization, and a data synchronization signal. This signal is used to set clock and data word synchronization at the beginning of each field. This part of block a is called a field sink, and the details of this 11 configuration are explained in the first section.
It is shown in Figure 0.

Data transmission rate 1 is 408 fH, and no digital data is inserted into the 64 bits from the falling edge of the monthly sync. Field sync data strings use 320 bits. 320 bits 1 is further divided into 10 units to give 32 bits, and each unit constitutes one set of clock synchronization and data synchronization signals. 2I bit out of 32 bits 1 [This is a run-in signal, 1010...10
A continuous signal of 12 cycles of 3 is inserted, followed by a data synchronization signal of 111000100 of 8 bits. Gorera 2/Hit 1d 8 Pitsu 1's coat 3
I0 sets of 2-bit middle-order data are continuously inserted. In addition, the front porch will have the equivalent of 2I people.

In this example, this signal sequence is applied to the a=1 cell 2211 for j people. Various control signals for the contents of the information inserted in book C are entered in block b. When inserting essential data into blocks b and C, the effective data range is composed of 320 bits and 1T as in the field sync, as shown in Fig. 11, and the range from 1 sync to the beginning of the data string is 64 bits. In addition, the fact that the front board is equivalent to 24 bits means that the field sync shown in Figure 10 is equivalent to K (also, among the 320 bits, a 24-bit, 12-bit clock run-in signal follows at the beginning of the data string. 8 pins 1 data same 1 signal continues.Remaining 2
88 bits are divided into 36 pieces, and the information is in units of 8 bits (1 by 1). Note that 4I is assigned to block b in the case of the present invention. Ri Nawara, 23.24,
Each control signal is recorded in each 1 of 25 and 26.

Also, the information in units of 8 bits (1 by 1) in block b is completed due to interleaving and error T.Next, when recording digital data in block C, , 26l is 1 block, and 1 field has a maximum of 9 blocks.

Digital data can be recorded in a maximum of 18 blocks in one frame, and any combination of full digital data, full image, and digital data and images is possible. The r source data within a block is configured such that interleaving and error correction are completed within one block.

Next, Fig. 12 shows an example of a shellfish of the Jino system. In the case of the present invention, the digital data is time-compressed digital data, and an apparatus for adding audio to a still image will be described. This device includes a digital amplifier 11 that amplifies the video signal, an I/sync separator 12 that converts the video signal into a V sync, and a sync separator 12. Amplified flyer Aε
The monthly threshold bold level follows the data level and is automatically set to the optimal value, and the
A1c circuit 13 converts R7 (NON RETURN TO ZERO) into a digital data string, RUN- detects a single signal from the digital data string.
The IN detector 14 reads the digital data string with a clock, detects the data synchronization signal of 8 pins 1, and sends a signal to each HJ.
, detect the beginning position of the 7-ta in C. S/I converter 2l that reads the data string into 8-bit parallel data, detects 23H to 26H in the field, separates the controller data signal, and switches the output. 16, a clock extractor 17 that extracts one clock component from the data string based on the RUN-IN signal, and a system clock generator that applies a PLL to the extracted clock to generate the tarock required for system operation. 18. Using the clock signal obtained from the system clock generator J as a reference, [V separated from the V sync separator 12]
, a timing signal generator 2 which generates various timing signals under the control of the sync signal 1 and the detection signal of the beginning of data q'd by the data synchronization detector 12; A field sync detector 19 detects the clock run-in signal and establishes clock synchronization and data synchronization at the beginning of each field from the data cycle pattern. Switching circuit 1
A control buffer 20 for temporarily storing the control code separated from 6. An error corrector 4 performs error correction processing on the control code read from the control code balance, and an interleaver 21 arranges the error-corrected control code according to the control sequence of Ichigo. A series of con 1”-le J-de]
-1 system controller that generates various control signals7. When data is read from or read from the large capacity memory 5 from the system controller, the initial address signal is +(, and when data is read or written in 8-bit units, a tally clock pulse is obtained from the timing signal J generator 2 and count-up processing is performed. The address counter 21 performs the following and supplies an address signal to the address counter 5
．． The digital data in the IC is converted to 1+ by the signal f2 (W) from the timing signal generator 2.
A large-capacity buffer memory 5 for storing and reading out using the signal ft(R); an error corrector 3 for correcting large-capacity irregularities in the middle of the block; A deinterleaver 23 that converts the corrected data into a continuous data string.
A digital-to-analog converter 9 processes and converts a series of IR digital signals into analog signals at the timing of ft<R) obtained by the timing signal generator 2J, and receives a control signal for VDP from the system controller 7. A player controller 10 is configured to supply a VDP control signal to VDl.

In such a configuration, when reproducing a recording video format 1 signal having a rightward pattern as shown in FIG. 6, for example, in period A, the VDP performs a normal reproduction operation. During this time, the digital data inserted into block C is stored in memory 5.
are stored sequentially.

In the next period B, the VDP performs a wake-up picture or frame-by-frame playback. At this time, the digital data stored in the memory 5 is output, but if this data is time-axis compressed audio digital data, it is time-axis expanded and output as analog audio during the still image or frame-by-frame playback. It is.

In the period A, the television monitor is clamped to the black level by the screen processing unit 8 shown in FIG. 9.

In the reproduction of the video format signal having the pattern shown in FIG. 7, the digital data in the block C is sequentially stored in the mailbox during the period A. During this time, the upper and lower parts of the monitor screen are similarly processed to have a black level, and an image appears in the middle part.

More specifically, the amphib video format signal at the video A output terminal J of the VDP is input to the video amplifier 11 and amplified. This amplified output is applied to the equalizer generator 12, and each separated equalizer signal (V, l) is sent to the timing signal generator 2.
One input is supplied.

The amplified video signal is also applied to the input of the A10 circuit 13. This ATC circuit detects the peak and petestal level of the threshold, and automatically sets the threshold level one after another while following each note.
Extract the NRZ gauge data string from No. 5. The RUN-IN signal detector 14 detects a 24-bit 12-noise clock run-in signal from the extracted noisy data string under the control of the timing control signal from the timing signal generator 2. The output of the detector 14 is applied to the input of a clock extraction circuit 17 which extracts a clock component from a normal data stream based on the clock run-in signal. The extracted clock component is sent to system clock generator 1.
8.

This system clock generator generates the ζth system clock for operating a system synchronized with the PIL circuit array from the extracted clock components. The clock signal generated by the system clock optical generator 18 is applied to the timing signal generator 2. Timing signal generator 2
Now, the control terminal of the field sync detector 19 for detecting the 221st eye and field sync in 1 r field while setting the clock signal to m standard and being controlled by the synchronization signal (V, 1). A timing signal is applied to the light source. It also detects signals 23 to 261 and generates timing control signals for separating control data. Also, 27+ is detected and control of writing and reading data after 27+ occurs.

The serial data string output from the ATC circuit 13 is applied to the data synchronization detector 15 and the S4 converter 2lkb. These read the data in synchronization with the IC, and the data synchronization detector 15 detects a data synchronization signal in each one and applies it to the timing signal 8 and the optical signal generator 2 to determine the starting position of the data. Maintain a constant synchronization relationship with the timing signal.

Further, the S/P converter 24 converts serial data into parallel data in units of 8 hits. 8 pin 1) is applied to the switching circuit 16. In the switching circuit, the timing signal generator 2 indicates that the signal is from 23 to 26, and if there is a signal, it is applied to the control code buffer 20, and otherwise it is applied to the large capacity buffer 7 memory 5. It works.

The control code temporarily stored in the control code buffer 20 is applied to the input of the error correction circuit 4.

The two-in-one roll code whose errors have been corrected by the error correction circuit is applied to the input of the deinterleaver 21. The deinterleaver arranges the control codes in parallel in control order and applies them to the system controller 7. The system controller decodes the control code and outputs the timing signal generator 2.
Writing of digital data, screen control, initial setting of the address counter 22 of the large-capacity buffer memory, and management of the capacity of digital data are performed based on the timing control signal generated by the controller.

Signals 5 related to control such as operation and stop of the play 7 are applied to a player controller 10, which converts them into signals for driving the play 7 and supplies them to the player. Next, a timing signal 221 is applied from the optical generator 2 to the control terminal of the field sync detector 19. The detector generates a reference for the same clock signal and data in the field from the repeated signals of the clock run-in signal and the data synchronization signal, and feeds it back to the clock extraction circuit 17 and the timing signal generator 2. next,
The signal and control code detected by the timing signal generator 271 are decoded, digital data is recorded in the block, and when the code indicating small is decoded by the system controller 7, the control code generated from the system controller is decoded. According to the signal, the f2 (W) signal is generated from the timing information unit 2 and is temporarily stored in the person@h bagno-ameshiri 5 one after another. When the storage of the constant volume u data is completed, the system control G7J and others will instruct the camera 7 to reproduce the still image at the specified frame, and the play 7 will generate the still image. The large-capacity buffer memory 5 is read by the system controller 7 and the start address is sequentially read out by the f+(R) signal generated by the timing signal light 1 and 2 by the reset signal sync 22. The notations sequentially read out from the large memory 5 are applied to the correction circuit 3, where errors are corrected and added to the input of the deinterleaver 23. In the de-interleaver, J is applied to the input of the D/A converter 9 in place of the original arrangement. A D/A converter converts it into an analog audio signal and outputs the audio. Audio is output (while the player takes still pictures 7). When the specified capacity of J-Yu is output from Hitotani t buffer memory 5, search or play etc. is performed according to the program code. The purpose is to supply control signals to the player.

Here, a method of clock synchronization and data synchronization among the RUN-IN signal detector 14, data synchronization detector 15, and field sync detector 19 will be described. In each field, data synchronization such as tarock synchronization is first established using clock run-in signals and data synchronization signals included in each of the 22+ field syncs.

The clock component included in the clock run-in is extracted by the clock extraction circuit 17, and then the clock component included in the clock run-in is extracted by the clock generator 17.
Avoid synchronizing the PLL circuit. Further, the leading position of the data is detected using a data synchronization signal, and this is applied to the timing signal generator 2 to synchronize this circuit with the data. Field sync has 1 clock run-in signal and 1 data synchronization signal
The reason why 0 bits are included is to ensure clock synchronization and data synchronization within this field sync even if part of the signal is missing due to dropout or the like.

The clock run-in detected by the synchronization detector (RUN-IN signal detector) and the data The synchronization signal maintains clock synchronization and data synchronization by preventing clock phase shift and P1 shift.In addition, the clock run-in and data synchronization signal at the beginning of each clock synchronize the clock by dropping out, etc.
It plays the role of restoring synchronization when data is out of synchronization.

FIG. 13 is a diagram showing only an example of the data synchronization detector 15, in which a pattern 1100100 of the data synchronization signal is detected in the pattern filter i51 and a detection pulse is output. Since this detection pulse may fail to detect a chord or a false data synchronization signal, a NAND gate 152 is used to determine the input state of the detection pulse 8 to subsequent circuits using a gut signal Q (DSG signal) at a predetermined timing. is under control. This detection pulse is latched by a wrap circuit 153 and held in a functional wrap circuit 155 via a NOR gate 154. Then, the next 7 pits 1 shift register 1
56 in sequence. The MSB of this register and the detection pulse at that time are detected to be in a non-coincidence state in the NOR gate 154. When a match is detected, a synchronization pulse is output. In 22H shown in FIG. 10, a synchronization pulse is output after detecting 10 sets of data synchronization signals, and in 231 and later shown in FIG. The output timing of the synchronization pulse is different so that the synchronization pulse is output immediately after one data synchronization signal is detected. Therefore, the generation timing of the synchronization pulse is controlled by the Goo Toy signal (LDG signal) at a predetermined timing in the Ando Goo 1157,
221 and subsequent circuits are shared. Note that the AND GO 1158 is used for initial clearing of the shift 1 register 156.

Here, it is necessary to distinguish between an image and digital data within block C, and for this purpose, the next block display at the start of the image and the end of the image is inserted as roll data. An example of this is shown in FIG. 14, where the beginning of the image is set to START BLOCK and C4 is used. Further, its possible values are 1 to A (hexadecimal).

4 bits are used for the next block at the end of the image as END BLOCK, and the possible values are 2 to A (hexadecimal).
It is. Note that this possible size varies depending on the value of x that is used to further divide block C into subblocks. This example is for the case of x-9, and Table 1 (described at the end of the detailed description of the invention) shows the various video format signals shown in FIG. 5, START BLOCK, END BLO
The correspondence with each code of CK is shown.

FIG. 75 is a block diagram of a reproduction system that controls the reproduction operation using a code indicating the insertion position of this image information.
Detects the 26th H sync of the synchronizing signal separated by the signal separator 1 shown in the figure, and outputs the 252-bin counter 25 that manages the field and the pulse output when this counter counts 16 as the tarok input. A flip-flop (FF) 26 is provided so that Q becomes 1 and output Q becomes 0 with V sink. This FF26 Q
The output is connected to the input of AND gate 27. The other input of Goo 1 is connected to the 1 sync signal.

The output of Goo 127 is obtained by ANDing the output Q of F26 and one sink. In other words, the 27th and subsequent syncs are output. There is a 26-decimal counter 28 that uses the 27th and subsequent syncs as clock inputs and is cleared by the V sync, which is the block C
This is a counter that detects the back m of the rib blocks C1 to c9 located inside. In this example, it is m-23, so
It is a 26-decimal counter.

Performs a counter operation using the carry signal of the 26-decimal counter,
There is a decimal counter 29 that is cleared on the V sink. This counter counts the subblocks in block C and Q.

Of the outputs from the control decoder 6 in FIG. 9, the 4-bit latch 3o temporarily stores the 4-bit 1 of the star 1 block code signal, and the 4-bit latch 3o temporarily stores the 4-bit 1 of the end block code signal. There is a storage 4-pitch latch 31, and the output signal of the 4-pitch latch 30 is used as a single input, and also indicates each status of the decimal counter 29.
The output No. 1 Q1 to Q4 of is used as the other input, and the matching circuit 32 which compares each bit and outputs a pulse when all the bits are equal, and similarly uses the output of the 4-pin 1 rat f31 as one input, The other 4-bit input is converted to a decimal counter 29.
There is a matching circuit 33 which outputs a pulse when the bits are different from 01 to Q4.

In addition, the pulse output from the matching circuit 32 is used as a clock input, and the Q output is "1" at 1 to which this pulse is input.
'', and the output of the matching circuit 33 is used as one input, and the other input is V sink f>, and if either signal is present, No. 1 is output respectively. FF35 to set it to 01 and this Q output are connected to the a side in "1" σ month, and the Q output of FF35 or b to "0" to 1
There is a switch 36 connected to the side and a masking circuit 37 that forcibly sets the screen to a black level.In the switch 36, the r connected to the a side outputs the input video A signal, and the The masking circuit 37 is configured to output the output when the masking circuit 37 is in use. Further, the other output 0 of the FF 35 is connected to an AND gate 38 to control the application of a fortune-telling pulse f2 (W) to the large capacity buffer memory 5.

The video format A-mat signal containing both an image and a digital signal is applied to the input of the signal separator 1 and is also applied to the a-side terminal of the switch 36. Of the signals separated by signal divider 1, V sink is 2
It is applied to the CLRQ terminal of the 52-ary counter 25, the CLR terminal of the FF 26, the CLR terminal of the m-ary counter 28, the CLR terminal of the (X+1)-ary counter 29, and one input terminal of the OAG 134. 252 base J counter with V sync 25. FF26. m-ary counter 28.
The (X+1) base counter 29 and FF 35 are then set to their initial states. Next, the 1 sync signal separated by the signal separator is applied to the clock terminal ck of the 252-bin counter 25 and to one input terminal j of the AND GO 127.

The 252 binary counter 25 is a counter for managing each field in the NlSCTV signal. In each field, this counter records a run 1 up operation after V sync rises and is cleared, ie, every time an H sync pulse is applied from 11H. Then, after counting H sync 16 times, emit a pulse! Jru. This pulse corresponds to 26H of each field in the NlScrv signal. This pulse is applied to the clock terminal Ck of the FF 26. In the FF 26, when a pulse is applied to the ck terminal, a logic output of "1" is output from the Q output. FF2
6 serves as a flag, and the Q output becomes logic "1" until V sink is applied to the CLR terminal after 26H. The Q output of FF26 is one j of ANDGOO 127.
is applied to the input of The other input terminal is applied with the H sink signal separated by the signal separator 1. Therefore,
Anode gate 2 will output H sinks from 27H onwards. This means that the H sink from the back block C of the screen division in Figure 1 is the clock terminal C of the m-ary counter 28.
It will be applied to k.

Here, the m-ary counter is a counter for managing subblocks of a block. In this example, m=26. The clear output of the m progress counter is applied to the tally terminal Ck of the x+1 counter 29. The ×+1 counter 29 is a counter for managing the position of the subblock within the block C. This counter counts not only the C area but also the Q area until the V sync arrives, so it is based on x+1. In this example, X is 9
Therefore, it becomes a decimal counter. The output of the 4 bits Q1 to Q6 indicating the state of the tree count i is the coincidence circuit 32.33
C is applied to one input of each. On the other hand, the code of the start block indicating the beginning of the back image of the control data separated from the digital counter 1 is applied to the latch 30 and temporarily stored. The period to be stored is one no yield or one frame period. Output is matching circuit 3
is applied to the other input terminal of 2. In this minus number circuit, each bit is compared and if 4 bits are equal, a pulse is generated at the output. Similarly, the end blocker coat or latch 3 indicates the next block number at the end of the image among the control codes separated by the signal separator 1.
The output is applied to the input of the matching circuit 33, and the output is applied to the other inputs of the matching circuit 33, and each pitch is compared, and a pulse is generated when all 4 pitches match. The output of the matching circuit 32 is applied to the clock terminal of the FF 35. Again-
The output of the circuit 33 is applied to the output of the OAG-134. OAG1 is applied to the clear terminal CLR of FF35. When the coincidence pulse of the coincidence detection circuit 32 is applied to the FF 35, the output Q becomes "1", and when the coincidence pulse of the -number output circuit 33 is applied, the output Q becomes "0". Note that the O output is completely opposite to the Q output. The Q output of the FF 35 is applied to a switch 36, which is set so that when the Q output of the FF 35 is logic "1", it is on the a side, and when it is logic "0", it is on the b side.

Further, the Q output of the FF 35 is applied to one input terminal of the AND gate 38. A write pulse f2 (W) generated only within block C is applied to the other of the AND gates from the timing signal generator 2 (see FIG. 9). Therefore, when the Q output of the IF35 is "0", the AND GO 138 supplies the output pulse f2 (W) to the large volume buffer ameshiri 5, and sequentially stores the data separated by the Shinga-bunson device 1. I'm going to go.

For example, in the case of the waveform shown in FIG. 5(C), the code of the star 1 block is 3 and the code 1 of the end block is 8.

At this time, latches 30 and 31 are loaded with 3 and 8. Since the Q output of the FF 35 is initially "0", the switch 36 is set to the b side, so that the output of the massing circuit 37 is derived as the video A output. The masking circuit is a circuit that masks the portion of the video signal other than the synchronization signal and the colorverse to a black level, so the screen becomes black at this time. Also, since the ○ output of the FF 35 is logic [1], the A1 gate 38 outputs the pulse of f2 (W>) as it is, and the data separated by the signal 8 separation device 1 or the data separated by the signal 8 separation device 1 is sent to the Butts 7 memory 5 one after another. 7 will be inserted.

Next, when the X+l base counter 29 reaches 3, the matching circuit 32 generates a pulse, so that the FF is
Set the Q output of 35 to "1". Therefore, the switch 36 is set to the a side, and the input Pino A signal, that is, the image is output. The Q output of FF35 will be "0"C, and a pulse will be generated from Ku138.Therefore, there will be no fortune-telling operation for hack i mail L5. Then, a pulse is generated from the matching circuit 33 and applied to the CLR terminal of the FF 35 through the OAG 135, so the Q output of this FF becomes "0", the switch 36 becomes the b side, and the pulse is turned on again. The masking circuit 37 will output.In other words, a black screen will be output.The Q output of the FF 35 will be "1" and the output of the AND gate 38 will be output from the timing signal generator again. The generated f2(W) causes the C large-capacity buffer memory 5 to sequentially store data separated from the previous signal.

The timing of the above operation is shown in FIG. Although FIG. 16 shows the video A signal of the first field of one NTSC frame, the same applies to the video A signal of the second field. In the above example, in order to identify the image and digital data and detect the position of the digital data,
Data indicating the start block of the image and the next block after the end of the image are inserted into the control data, but it may also be the start block of digital data, the block next to the end of digital data, or the start block of digital data and the block next to the end of digital data. The same applies to those indicating end blocks.

The audio digital data (SWS data) to be inserted is not limited to monaural data, but there are various programs such as stereo data, human explanation, music, etc., and such cases will be explained below.

FIG. 17 is a block diagram of a video playback device for a video player having various contents, types, and sound quality. 12, the V and H syncs are separated and supplied to the timing signal generator 2 to generate a timing signal synchronized with the 6 syncs. On the other hand, the input video signal is also sent to the AFC circuit 13, and this circuit detects errors in data reading due to variations in the video signal between the J replayers and the video signal. In order to prevent
The highest M threshold level is automatically determined based on the peak level and base level of the data intermediated to the video A signal, and the waveform of the analog video A signal is shaped into a 7NRZ digital signal. The data that completed the Digicel Gokyu is processed by the Kurotsukran-in separator 14.
The clock run-in signal is extracted and a system clock generator 18 generates a system clock in phase with the clock run-in signal.

After separating the clock run-in, the digital notebook is connected to S/
The P converter 24 converts the serial data into 8-bit parallel data using the signal from the timing signal generator 2. The control data is separated from the 8-pin parallel data by the clock controller 1 roll data separator 3 at the timing from the timing generator 2, and the limp ring code (described later) in the controller 1 roll data is separated by the sampling code discriminator 40. It is determined and held by the lunch turnoff from the signal generator 2. Control data other than the sampling needs are stored in the control 1 roll code buffer 720 at the timing from the timing signal 8 optical L unit 2. The audio data other than the control data that has passed through the control I roll data separator 39 is stored in the passenger volume buffer memory 5, the address of which is designated by C by the address counter 22. The address counter is set to 2 (
W) After the signal is connected to the clock input terminal of the address counter and the first address is specified from the system controller 7,
The next address is sequentially written by the 71-res J counter counting at f2(W>).Here, f2(W) is required at the transmission rail L of the Shima-bori 1 reduction.

Next, the clock f to be read from the large-capacity buffer memory 5
1(R) is a sampling clock generated according to the output of the sampling code discriminator 40, and is also applied to the D/A converter 9 to command the start of D/A conversion. The starting address at the time of reading is specified by the system controller 7 in the same way as at the time of writing, and the address counter 22 is counted up by f1(R). The sampling code is represented by 2 pins 1 and latched by the coat discrimination product 40, or the link clock generator 41 receives the information from 2 pins 1 and generates four types of sampling clocks. Three types of 32KHz in the system
, 64 KHz, and 96 KHz are generated. The D/A converter 9 is operated at these three types of sampling frequencies. Here, it is assumed that the audio data has been digitized by adaptive delta modulation (ADM), and the D/A converter is
Converts the audio data into an analog audio signal.

Furthermore, the decoder 42 controls the switching circuit 43 and the selection circuit 44 based on the 2-bit sampling clock, and avoids passing through the filters 45 to 47 corresponding to each code. When the band is 2.5 KHz, the filter 47 is selected. When the band is 45.64 KHz, the filter is 5 KHz. When the band is 46.96 KHz, the filter 47 is selected. Each code stored and decoded in the clock code buffer 20 is controlled by the system controller 7 according to each code.
Controls related to play 7 include stop, playback, frame advance, etc., performed by a player controller 10.

Next, the operation of the video software 1 shown in FIG. 18 will be explained.

The SWS data for still image 1 is SWS data 1. SW
S data 2. The SWS data for still image 2 is SWS data 3. SWS data 4, SWS data for still image 3
It is assumed that evening is SWS data 5 and SWS data 6. Also, the sampling code of 2 pips 1 in the control data is shown in the table.
2 (described at the end of the detailed description).

] The control data is assumed to be recorded in the frame immediately before the frame of data controlled by it, and during VDP playback operation, SWS data 1 is sampled with the control data of the frame before playback. The discriminator 40 detects that the code is 64KHz, stores SWS data 1 and SWS data 2 in the large-capacity buffer memory 5, and stores SWS data 1 and SWS data 2 in still image 1 as 04
Plays at a sampling frequency of KHz. Next still image 1
At the time of SWSj-ta 3. The mounting 40 detects that the sampling reproduction frequency of the SWS noteer 4 is 32KHz, and reads the SWS data 3. Store SWS Note 4 and still image 2
It is played at a limp ring frequency of 32KHz. Similarly, still image 3 is reproduced at 96KHz.

In this way, it is possible to record and reproduce the contents and type history of the SWS7-data by changing the sampling frequency depending on the sound quality of the original audio information.

Here, the case of SWS data or monaural souffle will be explained using FIGS. 19 and 20. 19th
The figure is a block diagram of the reproduction system in such a case, and only the portions similar to those in FIG. 17 will be described. The stereo/monaural identification data inserted into the control code is extracted and discriminated by the discriminator 48, and the discrimination result is sampled by the crotter generator 41. Switching timing generator 49 and A
- Sends to switching relay RY+, 2 of D A output line.

The switching circuit 43 switches the analog audio A signal using switching timing signals generated from the four dimming generators in accordance with the determination result of the stereo A and E nodal signals and sends the signal to the filters 45 and 46. These filters remove high frequency components such as limp frequency components. Relay RY
+ and 2 are for switching between stereo A and C audio signals depending on monaural.

Next, the operation of the block shown in FIG. 19 will be explained using the video A format shown in FIG. 20. Control VDP playback and switch
The stereo/monaural identification data in the control data of the frame before the S data 1 is extracted and discriminated by the discriminator 48, and the SWS data 1 and 2 are stored in the memory 5. The data thus stored in the memory 5 is read out when the still image 1 is reproduced, and monaural reproduction is performed. Next, 1 still image 1
It is determined from the controller 1 roll data of the frame that it is stereo, and the SWS data 3 and 4 are stored in the memory 5, read out when the still image 2 is generated, and A is played back.

Here, f1(R) is equal to the sampling frequency in monaural mode, and is twice the sampling frequency in stereo mode, thereby extending the time axis. The relationship between f+(R) for stereo and monaural is as follows: f1(R) for stereo = 2 x {fl(R for monaural)
)} becomes. Accordingly, C, the sampling clock generator 41 is
Sampling in the above relationship is generated in accordance with the monaural/stereo A identification data, and C data is read out from the memory 5.

In the above example, the output of the D/A converter 9 is separated in stereo by the switching circuit 43, but if these two are replaced,
The output j of the large-capacity buffer memory 5 is separated by a switching circuit, and a D/A converter is connected to each separated output.
The outputs of the D/A converters may be connected to filters 45 and 46, respectively.

Although the control data is recorded in the frame immediately before the frame of the data to be controlled by it, the data to be controlled may also be recorded in the same frame.

Note that in the example 3 in Figure 17, three low-pass filters corresponding to the sampling frequency were used, and they were switched independently for each band. , which is composed of a switch and a capacitor, and can move the transmission characteristics similarly along the frequency by changing the frequency of the switch. In other words, if the clock frequency is changed in accordance with the sampling frequency, the operation of the filter in each band can be controlled (or a microcomputer may be used for control).

FIG. 21 is an example using a switched capacitor filter and a microcomputer. Explanation of parts that overlap with FIG. 17 will be omitted. Is the controller separated by the control data separator 39 a microcomputer?
At the time of inserting and reading, it supplies an address signal to the large capacity buffer memory 5 and issues a control signal for the brake A.
In addition to the sampling frequency switching
- A control code is supplied to the timing signal generator 2 to decode the code and generate three types of non-bringing frequencies and a clock frequency to the switched capacitor filter 51.

In addition to the write pulse f2 (W), the timing signal generator generates three types of rimbling pulses j+ (R) and the functions of the r filters in the corresponding bands while being controlled by the control signal of the microcomputer. The clock frequency of f3(B) is used to calculate Rir. Switched capacitor filters move their transmission characteristics analogously depending on the clock frequency to perform multiple layers of each bandpass filter.

As mentioned above, digital data is audio data corresponding to images, that is, SWS (Still Picture).
(With Sound) data, but if you add software information related to external equipment such as a digital signal processing device such as a personal computer, you can use a video disk as a recording medium to connect VDP and computer Which control becomes possible and the usefulness arises.

Therefore, in addition to the internal SWS data, external digital data is also inserted in block C as necessary, and the identification information is seeded in the controller data in block b to distinguish between internal and external data. Enter. FIG. 22 shows an example of the identification information signal 8. An internal/external digital data identification bit Y is inserted in a predetermined position in the controller 1 roll data, and if it is Y or "0", the internal SWS footer If it is "1", it is external digital data. In addition, as shown in the figure, the internal/external control identification bit X is also set in another predetermined position, and
If so, it can be determined that the following control data is control data for internal control, and if it is [1], it is control data for external control. Yotsu C,
By determining the high quality identification signals 1X and Y during playback, it becomes possible to control external equipment such as a personal computer.

FIG. 23 is a block diagram of the playback system in this case. The input video format signal contains internal and external digital data and control data, and this signal is input to the signal separator 1 and is also subjected to screen processing. It is also input to the device ε. The separated synchronization signal is applied to the input of the timing signal generator 2. The control data divided by the signal divider 2 is applied to the input of the error corrector 4. Further, internal (audio) data or external data is sequentially transmitted and stored in the buffer memory 5 for time expansion using the f2 (W) timing signal generated by the timing signal converter 2. Next, the f1(R) signal outputted from the timing generator 2 is read out from the buffer memory 5 and applied to the input of the error corrector 3. The internal (audio) or external data subjected to error correction processing is applied to the input of the data separator 52. The blind voice data separated here is applied to the input of the D/A converter 9.

A D/A converter 9 converts the digital signal into an analog signal to produce an audio signal. At this time, f2(W)>f1(R
) The audio signal is expanded on the time axis by maintaining the frequency relationship. The corrected control data output from the error corrector 3 is applied to the control code decoder 6.

Here, depending on the position X in the data shown in FIG. is applied to A digital data control signal based on the bit Y in the internal control register, which is one of the outputs of the system controller 7, is applied to the data divider 52. As a result, the data divider 52 Data output is applied to external interface 53.

One of the outputs of the system controller 7 is the writing of the memory 5;
The output of the music is applied to the control terminal of the timing signal generator 2 and the input terminal of the screen processor 8. In this screen controller, the normal The image is output as is, and the digital signal portion is output with the black level replaced.

The player controller 10 uses various signals from the system controller 7 to transmit control signals for stopping the VDP, normal playback, frame advance, etc. The output of the interface 53 is applied to an external input of an external system (personal computer) 54. This allows the personal computer 54 to perform various operations. Further, an external output of the bass controller 54 (generally, a player control request or SWS re-control can be considered) is applied to an input of the external interface 53. This signal is applied to the input of the system control 7 and processed along with the internal control data. Computer 54 RGB (3F color)
The output and the video output processed by the screen processor 8 are applied to the input of an external screen processor 55. A control signal from the para 1 pin 57 is applied to the control 9 of the screen processor 55. This screen controller has video output, RGB
The output, video/RGB composite output can be switched, and the output is turned on. Note that the keyboard 1 and 56 are input devices for a general personal computer.

FIG. 24 shows another example of a video format in which internal SWS data and internal SWS data are mixed in a digital VDP of an external device such as a personal computer. In this example, the blocks C in each field are divided into three blocks c1 to C3 (herein referred to as blocks). The contents of Higemen l1 are SWS data for explaining one still image (frame 3), and there are 5 blocks in total: blocks c1 to c3 of field 1 and blocks c1 and c of the next field 2. Consisting of Segment 12 is external data, including the blotter of field 12 03 and field 3.
Blocks 01 to c3 and field 4 CI, C2
A total of 6 vines with vines. It should be noted that the number 08 of Noilt 4 is an image with a black level. The relationship between information 9 related to these Nords, segment 1, blocks and the internal/external data identification code is shown in FIG. This shows the count contents of the book counter 53 that is input to the device shown in the figure.
o, is f, and the data for the name Kumen 1 is ``ribuso'' tsuku (represented).

Figure 26 shows a playback thread book suitable for reproducing the video format 1 signal, which is smaller than that shown in Figure 27. 52 is a circuit that connects SWS data to
This is a switching circuit that selectively outputs digital data other than the A body model 9\ to the interface circuit 53. Reference numeral 63 denotes a block counter which is clocked by 1 every block period and reset by the pulse of the system clock generator 18 as necessary when the j-counter is entered into the memory 5; This is a data identification code data for decoding a data identification code indicating whether the digital data is SWS data or other external data from the 1-roll code. 59 is a block number decoder that decodes a code indicating the number of blocks constituting each digital data from the control code and outputs it to the comparison circuit 61;
is a segment number decoder which decodes the box code of each segment 1 number from control data and outputs it to the comparison circuit 61.

The comparator circuit 61 reads out the block of SWS data from the memory 5 based on the segment number, block number, data identification code decoded by each decoder 58 to 60 and the output of the block counter 63, and outputs the H level to the outside. While reading a block of data, the L level is output to the switching circuit 52, and as soon as the reading of the data is completed, the FF6
Generates a reset pulse to reset 2. Incidentally, codes other than the control roll code decoded by each of the decoders 58 to 60 in the control data are temporarily stored in the control roll code buffer 20. The FF 62 is controlled by the output of the system controller 7.

In such depiction, data from the beginning of segment 1 in FIG. 24 is sequentially loaded into the memory 5, and all data included in segment 11 and segment 12 are stored in the buffer. Subsequently, when the VDP starts to reproduce a still picture, the system controller 7 resets the clock counter 63 and at the same time reads the memory 5 and returns to the read state. As soon as reading of the first block of segment 1 is completed, counter 03
becomes "1", and the count continues by 1 each time one block is read out from the memory. In this procedure, the blotters corresponding to 11 segments, that is, the counters from "0" to "4", are 3 points opposite to the data identification code "1" (
25), a signal indicating that the TSWS data is present is sent to the switching circuit 52, and the counter changes from "5" to "10" corresponding to segment 2.
The data up to corresponds to the data identification "-o", and therefore, the JL level indicating that the data is external data is output to the switching circuit 52.

When the counter 63 reaches "11" and all data has been read, the comparison circuit 61 resets the FF 62,
The Q output of this FF causes the memory 5 to stop reading.

In accordance with the above operation, the contents of segment 1 are outputted from the D/A converter 9 as an audio signal, and the contents of segment 11 are outputted as external data via the interface 53 to a personal computer or the like.

Next, not only SWS data but also characters and other codes are recorded for the still image, and the SWS data and characters are also recorded with mutually similar contents, and this can be arbitrarily changed during playback. The J-UniRepo you select can be used in many different fields.

I am satisfied with the system described above.

FIG. 27 is a diagram showing a recording example of the video format of the system, in which each control code is recorded in the b block one frame before the image to be controlled and the digital video. For each still image, audio, text, and other digital data of appropriate types are recorded (in the case of 4 cases, 4 types of audio and data are recorded. Fig. 28 (A) is the sound and the letter j−
This is an example of the case of data, (B) is a similar example of 4 kinds of 9 voices, and (C) is the data of 4 kinds (although there is data, "-ta 1 is compared with external input. Also, theta 2 to deke 4 are character codes. Fig. 29 shows various controller codes and their corresponding processing counters (6J). All codes are ASCII codes. Fig. 30 shows The control code of each frame in the case of Fig. 28 (A) in the video format of Fig. 27 is shown. Fig. 32 is a button diagram of the SWS decoder in this system example. .

In the figure, a control code 20 for storing the control code of the previous frame is provided, and the control code is read out from this memory, decoded, and thereafter various processes are performed. The system controller 7 determines whether the digital data is SWS data, character data, or comparison data with an external signal, and controls the supply of each data to each block. It also has control functions for directly outputting the video signal, setting the screen to black level, displaying text in this black area, or adding text to the video signal. That is, the operations of the character buffer 65 and the video processor 8 are controlled to perform video processing. The character buffer 765 is used to temporarily store character codes of characters to be displayed during image composition, etc.

The audio/text data in Figure 28 (A) is converted to the video A in Figure 27.
FIG. 30 shows the contents of the control code recorded in block b of each frame when recorded on a recording medium using Fiber Pine 1. Generally, a video signal is reproduced in the order of odd field and even field 1. First, the odd-numbered field of Bucock A is beefed up. The internal playback controls recorded here are processed within the player, so the SWSD (adding audio and data to still images) decoder is not involved at all! I won't do it. Next, before entering part 4 of block b, screen and reputation control is performed according to the control code one frame before the current frame. Next, part b is reproduced, and the control ``-1'' of the next frame is temporarily stored in the storage area of the odd field of the control ``control'' in the SWSD.

Next, play part C. If the content is a normal moving image C, the image and audio will be recorded in the part C (if the content is a normal video C), each signal H supplied from the brake 7 will be sent to the outside.If it is digital data, it will be recorded in the previous frame. The specified digital data is read into a large capacity buffer memory, and the screen and audio become meat.Next, C re-4 is completed, and Q
Then, the even field will be reproduced,
Repeat a and b in the same way as the life number field. Now * is the SWSD control code 1 recorded in even field b.
Similarly, the even number frame of the control code
-Stored in the field area. When the playback of data b is completed, the next frame control code page J-1 is read into the control code puff 7 memory in the reader. Next, C is to be played back, but the processing of C in this frame follows the control code read in the frame before this frame, similar to the odd field.
In parallel with the same processing as for the odd field, the controller 1 roll read in this frame is processed, de-interleaved and decoded, and control signals are set in each part of the system control. . c, Q's? When the playback ends, before playing the next frame, it reads the current frame, outputs the control signals set in each part, and performs screen, audio, and data processing.

Next, a detailed explanation will be given with reference to FIGS. 27 and 30. The frame shown in (A) in FIG. 27 is played back. AM, PM, DAW0l
When the codes of 006018 to DAW03006078 are stored in the buffer memory, they are corrected by the error corrector 4, and the corrected control 1 roll code is decoded by the system controller 7, and each control signal is used for control output. set in the latch. Note that since an image (moving image) is recorded in C in this frame, the video and audio outputs of the decoder are supplied to each output of the player or to the outside.

Next, prior to the frame resetting in FIG. 27(B), the signals set in each control section within the system control are shifted to directly control each section. At this time, AM
The A-def A output indicates the 1-to code C A 6 so 8
Voice output becomes Miyuto. Also, PM is a mini-1 screen, so a video signal that makes the screen black is output, and then each block is played back in sequence. At b, the control code for the next frame is read, and at C, the control code for the next frame is read. SWS of
Digital data is stored in a large capacity buffer memory. In this way, for each frame (C) and (D), the control code is always read into the decoder in advance of one frame to be controlled in order to control the next frame. Each control is performed in the next frame. When playing the frame of (E), (D)
The (E) frame is controlled by the control code read in the (E) frame. First, since the audio output does not indicate the audio output of the SWSD, the AS converts the SWS digital data of the SWSD into D.
/A conversion is performed, and the still image audio that has been passed through a low-pass filter is output. The PA serves as a skewer that outputs a combination of the video signal and text output from the player. At this point, the character code has not been read yet, so play 7
The image of the output from is output. 3.Of course, a stop code is recorded in a of this frame,
The player decodes it internally and starts playing still images. Here, the SCI is a command to output a data group specified from the outside, so unless specified from the outside, audio characters will not be output. When the second SWS and the second literary data are specified externally, the SWS digital data is read from the specified address in the large capacity buffer memory, D/A converted, and outputted through a low-pass filter. and read from large-capacity Hatsufun memory,
After storing it in the character haratsuno, it is combined with the output video signal of the camera 7 and supplied to the outside.

In this case, the voice is "Mother" and the text is "Mother"
are output respectively. Next, if you want to output other sounds and characters, you can supply another code from outside.Short sentences, words, characters, etc. are stored in advance in a large-capacity buffer memory in association with the control code. It is possible to select and output other digital art including any audio and text. When transitioning from the still image playback state to the next operation, it is sufficient to send a control signal to the play 7 from the remote control. FIG. 31 shows the processing of frames (1) and (2) on the time axis using timing chart 1.

Next, the operation will be explained using the block diagram of FIG. 32.

The video signal is applied to the input of the TV synchronization signal separator 1 and also to the input of the video processor 8. TV sync bow separator C separated H. (2) The synchronization signal is applied to the input of the timing signal generator 2. The timing signal generator converts the system clock (7.16MHz) to H. V
The timing signal for each block in the decoder is generated based on the synchronizer signal. In particular, the timing signal f temporarily stored in the controller 1 roll code buffer memory 20
4 (CW) is a signal generated at 23H to 26H of each field. The timing signal f3 (CR) for reading the code from the control code buffer 7 memory into the system controller 7 is a timing signal generated after 27H of the even field. f2(W) is a timing signal generated when digital data is taken into the large-capacity buffer memory 5, and is a timing signal generated during the period from 27H to 260H when data is recorded in block C. f1(R is a timing signal generated when reading data from the large-capacity buffer memory 5, mainly generated during still image playback, and depends on the audio limp ring frequency. Here, f2(W) in terms of frequency
If >fl<R), time axis expansion processing will be performed on the SWS digital data.

Each timing is controlled by obtaining control signals from the system controller 7 and generating these various timing signals. T
A video signal (from which the synchronization signal has been removed and also referred to as a luminance signal) output from the V synchronization signal device 1 is applied to the input of the threshold control circuit 13. In the Threshco Hall 1 circuit, if the amplitude is smaller than a given level, it is converted to "1" in the gay signal, and if it is smaller, it is "0", and so on. The data is converted and supplied to the controller neat buffer memory 20 and large capacity buffer memory 5. In the controller 1 roll code buffer memory, the timing signal generator 2 receives from the system controller the address of the area where the control code of the odd field is stored when the field is an odd field, and the address of the even field when the field is an even field. The f4 (CW) signal that is generated is sequentially stored.

When the storage of the control code is completed in the even field, the f3 (CR) signal is then applied to the input of the system controller 7 after correction processing is performed in the positive circuit 4. The system controller decodes the code and sets signals to each processing unit. In the case of a code that manages the capacity of digital data, convert the American 4-code to binary data,
The data management register is set to the video processor 8 and the audio changeover switch 6G before the next frame's 8th generation.
control. Digital data supplied from the threshold circuit 13 is applied to the input terminal of the large capacity buffer memory 5. In this large-capacity buffer memory, the timing signal qJ2 (W
) and the system controller to obtain address signals for writing and store them sequentially. Next, once the data has been input and output to the large capacity buffer memory, normally, a timing signal is generated (ft(R)) and a read address signal is obtained from the system controller. It is supplied to the input of the read error S positive circuit 3 from the input signal. After correction processing and de-interleaving in this error correction circuit, the data is sent to the system controller and, in the case of SWS digital data, is applied to the input of the l/A converter 9. In the 1/A transformer, the noisy signal is analyzed and converted into a j signal, which is supplied to the outside through a 1-bus noise filter and an audio signal changeover switch 63. In the case of character data, the system controller similarly controls the input signal (:, the video signal supplied from Brake 1 through the character buffer 65 is synthesized by the video processor, and the synthesized video signal is supplied to the outside. In addition, in the case of text data with several types of content, the control key 1, which specifies that it is an expression selection readout, is read and decoded one frame in advance. Finger tJru]
No eight voices or characters are output unless the - code is supplied.

When the specified ]-1 is supplied to the system control salt from the outside, the system controller decodes the specified SWS data and character data in the large capacity buffer. When the current address is supplied to the computer, the timing signal generator is controlled to generate a pulse of ft(R) to the timing signal generator. At the same time, a control signal is supplied to the D' display converter 9, and a control signal is also supplied to the character variable, so that the specified Yoshikawa and character are output.

Next, if different voices and characters are supplied, the same process will be performed to output eight characters and characters. If the digital signal is comparison data with an external signal, it will be taken into the system controller after error correction and will have data input from the outside.

In the case of a normal moving image, analog audio is superimposed and recorded using commonly used frequency multiplexing, and in this case, the switch 66 is activated and the analog audio is derived as a playback output. Those who do this are confused.

If the control data of the above-mentioned individual control 1 roll data is inserted in the same frame as the digital data or image information processed by this control data, this control data can be reproduced and broadcast for identification. In order to do this, it is necessary to perform high-speed processing. For this purpose, the processing circuit of the control 1 roll code is operated in a convex manner.
Circuits that use non-sisters (such as 1-sister ICs or 8-sister ICs) are difficult to miniaturize and reduce power consumption.

Therefore, the data corresponding to the digital data and image information processed as described above is entered at least one frame before the matchmaker frame of the digital data, etc. When this control data is transferred, it is necessary to move back and forth between at least 1 frame and 19%l.

That is, as shown in timing code 1 in FIG. 31, in the example of video component A 1 in FIG. (A)
Correction of Froome's 4th image, processing of f code ministry? Data processing for the next (b) frame is performed in accordance with this control code.

In addition, as the amount of information in the control code increases, 1
The control is based on the corresponding +- horizontal scanning lines of the two fields that make up the frame (odd and even fields).
"-"-word is assigned and inserted. The mode is shown in Fig. 33.
, c and Q are the same as in the example in Figure 1, and each subscript 1, 2
The numbers indicate r-fields (1 for odd fields and 2 for even fields). An example of the number of F in each scan is shown in 7th grade in FIG. As for block b, the control code, two fields j are constructed so that one frame C increment and error correction are completed, and block C
In this case, interleaving and correction are completed in each subblock (see Figure 1). Since block b is various control codes and has positive information for controlling equipment, block C has high correct ability. For example, 1 word, 1 sin, -m correction, and 2 word erase correction are performed in sequence. On the other hand, Bu'
Regarding the digital data of Tsuku C, there is no problem unless some uncorrectability occurs and it becomes bfA or undecipherable characters, so it is assumed that the correction ability is lower, and for example, one word syndrome correction f is J. UJ is made fun of.

FIG. 34 is a diagram showing revision 1 of the control book 1, and book 1 is marked with A and 1C. This block b is 1 node (231 to 26+ of root,
CJ consisting of 231-2G and 81 of 2 wheels 1
However, the valid information book 1 is ε
There are 0 high 1C, and the remaining 208 pie 1 are 70,000 bodies in the X, Y and Z directions shown in FIG.

1.

The subscripts X, Y, and Z of Q indicate the direction of the I command including its parity, and the numerical subscript corresponds to the number of the first word of the 71st word. The word lx1Yl has a parity of 1x in the X direction (which is also a parity in the Y direction, and it is assumed that the first 1x1Y number in each direction is O.J2QxQYQZ) The word 1 is a parity trQX in the XJ direction, and at the same time, a check word 1Qv in the Yj direction (with G and a small C that is a parity in the Z direction).

The same applies to other words expressed by combinations of 1 or Q and subscripts. Note that one word is assumed to be ε bits.

Here, the word fWo belonging to Y7 plain at the left end of the diagram,
W, W20. W40. W4+, Wco, Wrl, pYO
, QYO, PYI, QYI are used as frame identification codes to be described later. First, for error detection, (n
, k) = (12, 10>) and detects C. This corresponds to error detection in the X direction by PX and QX in Fig. 34. Next, as a positive imposition, 2H For each (n, k)=
(6, 4)) Configure No. 4 and apply b pressure. This is the PY in the diagram
.

This corresponds to Y-direction error correction using Qv. Furthermore, 2Hd3
For the 4 words of (n, k) = i, 2) 7
and make corrections. This is 1l in the figure.

This corresponds to error correction in the X direction by Ql.

In this example, we will perform error detection and error correction (G17
The Reed-Solomon code on F(28) is used for the first word of 8 bits 1, and the atomic element x 3, P(X) = X8+
X' +
00010> Do Juru.

Also, check matrix 1 is , and this can be calculated using 1 unit C matrix 1 ((wajdo, becomes.

tatashi, ■ is the middle 1st column of 8b8 column, and 8 like li・ki
Let's call it a matrix with 8 rows and 8 columns.

Now, until we know the location of the error and the details of the error, we can define the syndrome S defined as follows.

S=[Sp51J”=1・twn-1, Wn-2゜...
W2, I, Q]' In the above equation, l and Q are recorded together with the information word so that Sp=So=0. Therefore, when recording the frame identification code on even frames, "ooooooo
oo'', and '00111110'' for an odd frame. In this case, PYo.

The parity of QYO, PYI, Qv+ is "00000000" for even frames and "00" for odd frames.
111111', and can be used by repeating the frame identification.

Such a frame identification code is set at a second that changes between adjacent frame phases U, and is recorded in block b.
If you try to detect whether or not there is a change in this frame identification code during playback, you can quickly detect that it is a moving image when it changes, and that it is a still image.

For example, if the frame F system in FIG. A detector is installed and the output is sent to the 4 system controller 7. An example of the configuration of this moving/static both horizontal V detector is shown in Fig. 35, and is as follows. What's the configuration like?

1350 to detect whether the 3rd to 7th hits of the code are 1 to 0; The detection pulses (00000) and (1111) detected at 1 are applied to the + terminal of the next-stage Atsubu Town Counter System 352 in synchronization with 9 CK. Ruru non 1 goo 133
3, 354, Karan 1 or 10 or more] A-PaIN-.

In order to prevent an underduff of 0 or less, the input of the detection pulse counter is omitted, and the outputs of the counter are 4 bits QA, Qe, Qc, and Q.

A-bar anti-low preventer 355. monitors and when it reaches 16 or 0, generates a low level E and closes the gates 353, 354. Synchronize the output of the m upper bits of the counter 352 with the reading frame and shift it with the ``tick''.Using the two outputs of the register 35G and the shift register 356, detect whether it is a moving image or a still image and set the detection flag. It consists of an exclusive A game 1357 to be output.

Among the read control codes, the frame identification code is not corrected because it requires high-speed detection. Instead, a 12-word identification code is used to increase reliability, and the circuit shown in FIG. 35 is implemented. is input to. The input identification code is detected by checking whether the third to seventh bits are all O or 1. If all of them are O, the gate 352 is made to count up to 1, and if it is 1, it is made to count down. (00000000) and the even numbered frame is the 11th hQ of the 4-bit output of the gate.

is always 1, and Qo is set to 0 on the left during the odd frame i1 of <00111110).

This allows c1 to be an even number, making it possible to have a peak of 1 in the white frame, which is possible by detecting 1 pixel.

Here, if frame identification is detected as long as 1 or 1 is detected, it will be possible to detect the missing part of the video or still image. 12 watts are recorded in 1. Therefore, counter 3
E2J same frame identification] - How many times do you read 6 counts 1?
The degree of oxidation is 4.

Therefore, the output of the counter is sent to the A-H-J interflow preventer 355, and when the output becomes 15 (O), the input stage of the input stage of the input stage of the input stage of the input stage of the counter 1 is closed, and the counter 1 is switched to f1. ``Sa υru'').

The maximum output of this counter 352 is Q.

is serially input to a 2-bit shift 1resist 35G using a clock synchronized with the frame. In the case of playing back this clipped video, the counter outputs are different depending on what is input to the shift register, so if these are input to the goo 1357, the output will be 1. On the other hand, in the case of still image playback, the output of the shift 1 register becomes L, making it possible to distinguish between the moving and still image playback states.

This detection output is sent from the system controller 7 to each part of the system, and can also be sent to external equipment such as a computer via the interface 53 as necessary.

As another example for dealing with the increase in the number of control code containers, a method can be considered in which the control code corresponding to one frame is divided into a plurality of frames and inserted and recorded. The I block of the reproduction system in this case is shown in FIG. 36, and the separator 1 separates the V, l sync, data synchronization signals, control code, SWS data, etc. from the bifoff A-mat signal. , V, l timing signal generator 2 that generates timing signals from the sync and data synchronization signals to each part of the system, and a digital signal generator that converts SWS data into analog signals. an I processor 69, a haratsunomeshiri 20 that records control data, a corrector 4 that corrects errors in data, a data end detector 68 that detects the completion of control data, and data from the memory 20. The decoder 67 decodes the
Instructions, input information from input devices (computers, etc.) and VDP
A system controller 7 which receives the data status signal and sends out control number 1 to each part, a screen processor 8 which performs various processing on the video signal, and a SWSJ data output and general orderer.
It consists of an A-dio signal processor 70 with 7 signals and 8 signals.

Now, insert and record controller data corresponding to one frame into block 1 of multiple frames.
Then, an identification signal indicating whether or not this 1-roll data continues in the next frame is also requested.

Next, the operation will be explained. J in the diagram, video A-
The mat signal input is applied to the CS separator 1, and the vertical synchronization signal, horizontal synchronization shift, 1-9, 9-8, roll program, and digital audio data are separated. The separated vertical synchronization signal, horizontal synchronization signal, and data synchronization signal are applied to a timing signal generator 2, which generates timing signals to be sent to each section. In addition, the digital audio data is used in the buffer memory in the six digital audio processors, and after error correction is performed, the inter-verse axis expansion is read out, and the D/
An analog audio signal is extracted from the A converter.

The controller 1 roll data is stored in a baraf/meshiry 20 and error corrected by an error corrector 4. At this point, the data end detector 68 detects an identification signal indicating whether the control data is completed or continues to the next frame. If the control data continues into the next frame, the control data in the buffer memory 20 will be transferred to the decoder 6.
Do not send it to 7 and keep it as is. Further, when the control data is completed, the decoder 67 reads and decodes the control program in the buffer memory 20.

The system controller 7 receives control commands from the decoder, information from the input device, and the status signal of the player.
The screen processor 8 sends various control signals to the audio signal processor and the video disc player. The video signal is output by applying massing to the voice data (so that the screen does not drop to black), or by superimposing characters and figures. Does the audio signal processor 70 switch between the demodulated audio signal of digital audio data and the audio signal input? cormorant. Player control number A is applied to controller 11-rumanmandanj in play 7.

Controls normal playback, slow play, freeze, and frame number leave 9.

Next, diversification of so-called bifu-shofu 1 may be attempted by recording Toriyai's video (?i1sa) and SWS on a recording medium. A conceivable method is to record in advance the identification code 1 of the 7 moving pictures and the SWS, read this identification code at the time of il to determine it, and switch the playback operation keeping this in mind.

In the case of normal video, the audio remains in analog form, as is done with general video discs, for example 2.
1M1z (when stereo, FM modulates the audio signal of 2°8VIZ and converts it to video A information (this video signal is also F
M) and frequency multiplexed and recorded. In the case of still images, digitized SWS data is inserted into block C, time-division multiplexed, and recorded.

Refer to FIG. 37, which shows the contents of the control 1 roll code in such a case, in which the upper 4 bits of the 8-bit configuration are the output control code, and the lower 4 bits 1 are the input control code. The output control code is a code for distinguishing between stereo and monaural, and the input control code is for selecting SWS data or analog audio Chi when monaural.
It determines whether to select C12 or mute, and the logic "i" is used to select, and the logic "o" is used to deselect. Note that X is a bit that is not involved in control, and is forcibly set to "o" in this example. In addition, in the case of stereo, the audio input is selected from the 2c1 stereo output by VDP (re-7 output of frequency multiplexed recording), and priority α is selected.
]Soufflé A" is 8, and stay A has logic "1".
' is set to 4 so that the other bits are irrelevant.

Figure 38 is a block diagram of the l system in such a case (there is one, and the code for selecting 7l from controller 1 roll code 6) (
6-bit 1 latch 71 for storing -K (Fig. 37);
Due to the output of this RA/71, the voice selection relay RY1
~ Start the drive of RY6 and then use the drop roller 1 etc.''lZ
-A protection circuit 72 operates to prevent malfunctions from occurring on platforms where erroneous data has been inserted because the J rate could not be corrected, and A/A is controlled by the output of this circuit 72? ! The selection relays RY1 to RY6 are turned on.

Figure 39 is]nt[-runid and relay Y]~RY6
There is a diagram Q showing the operational relationship of 1. [And the output or a-? The helmet is the bottom 4 pits (37th
The i-source specified by (see figure) is output. Chl
When logic U1 is reached, VDI's Icl output is output, and when C12 becomes logic 1, VDP's 1ch high output is output, respectively.Generally, audio with content of C2 type is inserted into the video and the output is Used when making a selection based on preference. s
When WS becomes logic 1, the time-axis compressed SWs data is time-axis expanded, D/A converted, and output as analog audio. Furthermore, when the mute signal is set to logic 1, the audio signal is not output.

FIG. 40 is a diagram showing an example of the protection circuit of FIG. 38,
It is constituted by an inverter and an AND gate using 6 bits 1 except for the J2 pin 1 shown by X in FIG.

FIG. 41 is a diagram showing the video format 1 of this example,
In period A, the SWS data is inserted into the entire block C, so the audio is mu1. Therefore, while playing the video, the SWS data is sequentially stored in the buffer memory 5. Incidentally, the ]-do in this period is 11. In period B, the VDl will reproduce the still image again, but at this time the SWS data stored in the index 5 is expanded by 1 axis and read out from the C memory 1, and the output contains this SWS data. The analog voice is η13. The code during this time is 18. 7 in period C, while storing the SWS data in memory, the video 4 [41] and the audio at this time are
, C12 γ♂ is a J cow. ]-to at this time is 80
Then, when period I comes, V) I will take the still images and sell the SWS tape from memory.The time axis will be expanded and output as audio (during this period, the code will be 18). .

Next, regarding the separation of digital data (described above).

First of all, referring to FIG. 42, this figure is a block diagram of a conventional data separation circuit, in which 121 is a pedestal clamper that lowers the pedestal level by a constant voltage, and 422 is a threshold value (threshold) that controls voltage at VD. 423 is a detector that detects the sink, 12l is a V
Take the sink 61IL (Noei Slocked Loop)
A circuit 425 is a DS detector that is inserted at the forefront of data in one section and extracts the same data J (DS) pulse, 42
6 is a circuit that generates a signal that is the basis of the data read lock (DCK) from the DS pulse and the clock from the PLL 424, and I27 is a circuit that uses the clock output from the reset circuit 42G for each period of data. A delay circuit 428 and a delay circuit 428 for delaying the rising edge at the center read data with reference to DCK from the delay circuit 427.

Here, a partial waveform enlarged view of the digital data including the DS pulse of the digital signal waveform of the 11 sections shown in FIG. 11 is shown in FIG. The pedestal is clamped and the threshold value V is applied to the comparator 422.

Then, the waveform is shaped as a digital signal of J1,0 as shown in the 43rd (b).

On the other hand, detection? Based on the V sync detected at 123, the PL 1424 outputs the dynamic V sync, data dot root cycle & number 4 digits as shown in Figure (d). 425 as shown in Figure (C), this is detected as a goo 1 pulse and reset circuit 426
The operation of the IC is activated, and the 7D 7 (from PLL424)
It is reset to 1 at the VJ reset (point A in the figure) in d) and emits a clock with the same frequency as the normal 1 as shown in figure <0>.

This clock (e) is delayed by the delay circuit 427 so that the rising edge of the clock is at the center of each bit section of the C notator.
CK is generated as shown in (f). When this DCK becomes the system clock, it is used as the clock for the f1423 in J, and data synchronized with this lCK can be obtained as a read output.

In the circuit system shown in FIG. 42, the slice level (l value level) V1 of the comparator 422 follows the amplitude fluctuation of the input j signal, and there are four cases where K<constant. Therefore, it is impossible to obtain a positive data slurry, and the data cannot be read accurately. In addition, the 71 points for resetting the DCK base W tarot (e) are the IS pulse (C) for the correct position.
The clock pulse (
At the rising point of d), the clock (e) is reset. Therefore, the tarokk (e) causes a phase shift by one cycle of the maximum clock pulse (d), and finally matches the data phase exactly: DCK cannot be obtained.

In addition, in order to read the data in the 1] section using the falling edge of the DS pulse as the phase reference of the DCK, for example, the 11th
If the DS pulse shown in the figure is not detected due to dropout, etc., or if an incorrect position is detected,
In this section, the correct M reset 1 is not performed, resulting in a data reading error. Furthermore, instead of generating CCK in such a manner,
A system that constantly monitors data inversion and generates DCK that follows it, for example a system using ItL, would solve the above-mentioned drawbacks to some extent, but not completely.

Therefore, by using the field sync data shown in FIG. 10 inserted in J block a at the forefront of the field, a so-called A-C (automatic threshold control) circuit is constructed based on this data. This is to solve the drawbacks, and a block diagram of a concrete example thereof is shown in FIG.

When the video format signal 2 is pedestally clamped by the pedestal clamp 421, this clamper I
The pedestal level V is now output from 21. Since the other two-image signals of the digital signal also exist in the BJ" A) Aitsu 1 signal, only the digital signal is converted to 1 in the 1 circuit 429. Then, the j-beak of the digital signal is held, and the previous bed scale level V1 and this hold output J are divided into a voltage divider circuit z9 of resistors R+ and R2, and this becomes the threshold level: one input of the input rail 122.

This threshold m level is compared with the output level of the clamper 42J, and the waveform is shaped.
This pulse extractor 432 (= is formed) such that the inverse l1 of this NO 1 output rises.
The same frequency as the pitch 1 and the pitch 1 of the rider
] - As if the rise comes at the center of each pitch 1 section of RI a) CK
is generated by the lLL circuit 134. Digital data synchronized with DCK is read by the FF 428, which uses this CK as a clock input and the output of the comparator 422 as a data input.

In the peak hold circuit 430, a large time constant is selected so as not to follow sudden amplitude changes such as data drop-out 1 or noise.

In this way, the peak hold and PLL lock are maintained for a certain period of time by the field sync data inserted at the front of the field, so even if the image continues and digital data arrives afterwards, the peak hold is immediately applied to P. and PLl] ivy, and stable data separation is possible. Even if the 1LL lock is lost in the middle of the field, it is possible to relock the DS signal immediately before the digital data as shown in FIG.

If the image signal period is long to some extent, there is a risk that the PLL will become unlocked, so a pulse synchronized with the clock synchronization signal is inserted at the beginning of each period to which the image signal belongs, as shown in Figure 45. Even if the PLL lock is lost in the middle of the field, the PLL can be locked by the next pulse.
Qru.

In the above example, the PLL 434 is used, but it is also possible to use the Man-1 shown in FIG. 42 (not called Lillet Man-shiki). Moon straw, 431~ in Figure 44
C may also be used by replacing each booter 134 with each booter 423 to 427 in the NJ2 diagram.

By the way, as shown in Fig. 4, the clock run-in Yakumi and ) S signal are placed at the forefront of the intal data.
In Fig. 42 Noriref 1J type, since it is 0 that detects and resets a part of this signal, it operates well as long as the entire body of this signal is 1. Something stronger than illusion roars. Also, Rishitsu hj
When J (is in front of the image signal as shown in Fig. 45) is not used, relay 1 is not applied during the image signal J, so an phantom phase shift is superimposed on the DCK data. If the clock signal is dropped due to a dropout, the 1-section reset will not be performed and inaccurate data will be read.
As shown in Figure 5, the above-mentioned irregularity is eliminated by inserting Tsuta Shinkyu at the beginning of each 1. However, in this Norihira 1 system, it is unavoidable that a deviation of one clock cycle J per person occurs.

In the above explanation, we talked about video disks as recording media, but video tapes are also good, and
- In addition to SWS audio data, Matsu1 digital data includes textual information, storage information in the mechanical field, medical information such as electrocardiogram rings in the medical field, and physical information such as hot stone information. etc. can also be included.

This digital data is a straight line or broken line PCM method,
Various encoding methods such as adaptive differential PCM (ADPCM) and ADM can be used. Furthermore, the Hide Afu A-Matsu 1 signal type is compatible with systems other than the MrSC system, such as 1AL and SEC.
It is also possible to refer to it as the AM method.

Furthermore, it is clear that the number of scanning lines in each block a-Q is not limited to the example shown in FIG. 3, and can be modified in various ways.

According to the present invention, the information (image,
SWS digital data, text 2-1, other digital data) are recorded one frame ahead of the current frame, and played back one frame ahead of the frame in which the jL information is recorded. As a result, there is sufficient time to decode and process the control code I, so there is no need to use an element that responds at L speed for the decoding and processing of the second control code, reducing power consumption. Since power elements can be used, the power consumption of the entire system can be reduced.Also, it becomes easy to convert the 1-input I1-code decoding processing section into 11S.

Also, since the control code is one frame before the frame J to be controlled, there is J or + function C that records ]n1 roll'-1 in odd and even field 1, so regarding the field between fields, ( The code is between 2 and 41, and it is difficult to add effective interleaving and correction codes, but it is possible to disperse control codes at field intervals within one frame. Therefore, the effect is the same as applying a large interleave, and it is possible to add a self-effective correction code.Also, of course, the odd and even fields can be used for four effects. Therefore, the capacity of the control code becomes large, and it becomes possible to control a variety of video cameras and softwares.

It goes without saying that the control code is not limited to the previous frame of the information corresponding to the control code, but may be placed 2.3 frames before.

[Brief explanation of the drawing]

FIG. 1 shows how one field is divided into 10 sections on both sides according to the present invention, and FIG.
Figure 3 is a small J diagram showing an example of the number of horizontal scanning lines of the block in Figure 1, Figure 4 is a diagram showing an example of inserting digital data within one day, Figure 5 - FIG. 7 is a diagram showing the manner in which digital data and images are inserted, FIG. 8 is a block diagram schematically showing the recording method of the video A format signal according to the present invention, and FIG. 9 is a block diagram of the reproduction system. Figure 10 shows an example of the field sync waveform of block a. Figure 11 shows an example of the waveform of 11 minutes of digital data of block C. Figure 12 shows an example of the waveform of block C. Figure J shows another example of the playback system block, Figure 13 is a circuit diagram of a specific example of the J detector with the data in Figure 12, Figure 14 shows an example of control data, and Figure 15 shows 16 is a diagram showing another example of the block in the reproduction system. FIG. 16 is a timing chart showing the operation of the block in FIG. 15. FIG. 17 is a diagram showing still another example of the block in the reproduction system. The figure shows one example of the video display system 71, FIG. 19 shows another example of the playback system block, FIG. 20 shows another example of the video display system 71,
Figure 1 shows another example of the amphibious system.
- Figure 23 shows yet another example of the system block, Figure 24 shows another example of the B-7 sonoto, Figure 1, Figure 25 shows another example of the system block. Figure 26 shows yet another example of the J amphibious system. Figure 27 shows yet another example of video software. Figure 28 Figures 29 and 30 show the contents of noisy data, Figures 29 and 30 show examples of roll data, and Figure 31 shows the operation of the first raw system for video A software 1 in Figure 27. A diagram showing the timing, and Figure 32 is a diagram showing another example of the block of the 1st system. Figure 33 shows an example of insertion into video format 1 of control data, Figure 34 is a diagram explaining the error correction method of controller data, and Figure 35K is a control diagram. FIG. 36 shows an example of a data detector, and FIG. 36 shows another example of a reproduction system block.
Figure 37 shows an example of one control data υ diagram, Figure 38 shows another example of g-cow 0 block, and Figure 39 shows the third
7 shows the operational relationship between the control data and the Hatakekiridai relay shown in FIG. 36, FIG. 40 shows a specific example of the protection circuit shown in FIG. 3ε, and FIG. A diagram showing an example, FIG. 42 is a block diagram of a conventional example of the data portion front part,
Fig. x43 is a waveform diagram of each part explaining the operation of the block in Fig. 42, Fig. 44 is a block diagram of the data separation unit used in the present invention, and Fig. y45 does not show examples of 11 signal waveforms used in the block of Fig. 44. It is a diagram. Explanation of symbols of main parts 1...Signal valve H unit 2...Timing signal generator 3.4...Error correction circuit 5...Time axis expansion memory 6...Control] Roll code decoder 7...System controller 8 ... Screen processor 9 ... River / A converter 10 ... Play 7 control Z Applicant Pioneer Co., Ltd. Representative Patent Attorney Motohiko Kamura (one other person)

Claims (2)

[Claims] (1) Divide the horizontal scanning line that constitutes one field into a video format signal into multiple blocks, and insert digitized digital data or (and) image information of predetermined information into the first block. The second block contains the information inserted in the first block,
and a control 1 roll signal related to No. 3 processing, and the control 1 roll signal corresponding to the first block is inserted into at least b1 of the frame in which this first block is inserted.
A recording method for a video frame signal, characterized in that the signal is inserted in the second block before the frame. (2) The horizontal scanning line constituting one field corresponding to the video A-pine signal is divided into multiple blocks, and the C1 first block contains digital data or L (and) that is digitized with predetermined information. image information is inserted, the content of the information inserted in the first block and a control signal related to the image processing are inserted into the second block, and the above-mentioned 91
The first block corresponding to the first block is inserted into the second block at least 61 frames before the frame into which this first block is inserted (recorded, and upon playback, the second block is inserted). A video format 1 signal inserted into a block is determined by J4L, and signal processing is performed on the contents of the first block in the following frame. Signal recording NTh type.