JPS6069986A - Recording system of video format signal - Google Patents

Abstract

PURPOSE:To attain versatility of a recording medium by inserting sound and digital data for an external device to a video format signal and also recording an identification code. CONSTITUTION:The video format signal is recorded while being inserted with a sound digital data and a digital data for an external device. Moreover, the identification code distinguishing both digital data is also recorded. The signal is processed by reading this identification code at reproduction. Thus, a video disc being a recording medium is used together with an external device such as a computer, for as well as a video player so as to attain versatility.

Description

[Detailed description of the invention]

The present invention relates to a recording method for a video format signal, and more particularly to a method for recording image information and audio information on a recording medium as a video format signal. When audio information corresponding to image information is recorded on a recording medium together with the image information, the audio information is compressed in the time axis into a part of the video format signal, and the image information is inserted into other parts. In this case, when playing back the audio information, the time axis of this audio digital data is extended while playing the corresponding image (still image or video).
11.
1, control data related to reproduction signal processing of audio digital data is recorded in advance. In recent years, it has become necessary to use such a recording medium, such as a video disc, not only with the video disc player 17, but also with other external equipment, such as a computer, to increase its versatility. In view of this, the present invention has been developed so that when audio digital data is inserted into VIDEO A-Matsu 1 to 6, digital data that can be used and processed by an external computer or the like is also inserted into It, so that the general-purpose recording medium ( Hideoff A that can aim for 'L'
- The purpose is to provide a recording method for matte signals. The recording power method of the video format Ikuni according to the present invention is characterized in that audio digital data and other digital data are inserted into the video format signal and recorded. Furthermore, an identification (number i) that distinguishes both digital data is also recorded, and this is read and processed during reproduction.The present invention will be described in detail below using drawings. Fig. 1 is a detailed explanation diagram of the principle of the present invention, in which the number of horizontal scanning lines (corresponding to an effective screen) of a signal equivalent to one field of a video format signal at the time of recording is expressed as a, b', c, ( In particular, a, b, and c are made up of an integer number of horizontal scanning lines, and the number of horizontal scanning lines of C is divisible by a predetermined integer x, so that m=c /x (m is an integer). Therefore, C is composed of m pieces, and C1 to C
It is divided into up to X sub-blocks. Note that Q is not necessarily an integer. Figure 2 shows part of the video format signal shown in Figure 1. Figure (A) shows the waveform of an example in which an image is recorded in block C9Q, and Figure (B) shows an example in which digital data is recorded in block C. Figure 3 shows a, b, O in the N king SC signal.
, Q is a diagram showing specific numerical values of an example of division, in which effective scanning lines are divided into 241.5 out of 262.5 scanning lines in one field.
5 trees, and blocks a and b are set so that they are outside the visible range of the television screen. In this example, a
=1. b=4. C=234. x-9, m-26,
Q=2.5. When digital data is inserted into b and c, interleaving is applied to prevent consecutive errors from occurring even if errors concentrate due to dropouts, etc., and an error correction code ( = J is added, but in this example, interleaving and error correction blocks are completed independently. Similarly, in C, -
For C, C1 to CX are each independently interleaved or 11
8J is set to be correct or complete. Figure 4 shows an example of inserting digital data on one horizontal scanning line, and data transfer lines 1 to 408f+-+
(fH is the horizontal scanning frequency), and a clock run-in signal, which is a clock synchronization signal, is inserted before the digital data.Furthermore, following this signal, there are several data synchronization signals for data synchronization. Following this data synchronization signal, a data word and an error detection and correction code are inserted. Figure 5 shows various recording modes, and (A) shows C and C blocks. Since blocks a and b are outside the visible range, the display is similar to that of a normal TV image.(B) shows that all digital data has been inserted into block C; ) inserts digital data into subblocks Ct, 02.Os, and Cs of subblocks obtained by dividing block C into nine parts, and inserts images into subblocks 03 to C7, respectively.(D) inserts digital data into subblocks cI and c2. This is an example of inserting images in , 03 to C9, (E)
is subblock c1. An image is inserted into ~c7, and digital data is inserted into cB and cg, respectively. In Figure 6, the frame (field) into which digital data is inserted into block C is continuous over a period of time. In the subsequent period B, a C image is inserted into the C block.
In period A

[) Inserts an image corresponding to the data C1 Whether it is a still image or a frame-by-frame image, it is also a moving image. There are cases where the same frame image is recorded.
Digital data is inserted into C9 and images are inserted into C2 to C8, resulting in period A of several frames to several frames.1
) In the following period B, there is an example e in which only an image is inserted into block C. In this case, 1! l] During interval A, the image becomes a part of the screen, and the image is not interrupted. FIG. 8 is a block diagram of the recording system for obtaining the heat A format signal according to the recording method of the present invention, and the analog audio A signal is digitized by the A/D converter 80. . This digital signal is written to the buffer 7 memory 81 for time-base compression at a sampling frequency ft (R). Time axis compression is achieved by reading data from the memory 81 at a frequency f2 (W) higher than ++ (R). The control signal, which is control information, is
In addition to the clock run-in signal and data synchronization signal shown above, it includes the content and capacity of information in each block, various processing information when reproducing the information, etc. A video signal, a digital data signal including audio data time-base compressed by a buffer memory 81, and control information are input to a switching circuit 82, respectively. This switching circuit 82
The selection operation of the memory 81 is controlled by a timing signal generator 83, and the writing/reading of the memory 81 is also controlled by the timing signal generator 83. In the timing signal generator 83, an internal oscillator is synchronized with the synchronization signal of the input video signal, and various timing signals are generated in response to external control signals. From the output of the switching circuit ε32, the recording video format 1-low sea-J or 11i is performed. FIG. 9 is a schematic block diagram of a general still image with information for blue (IJ daytime LJ production equipment. P1 cow video A) A-mat signal is sent to the signal 3 separator '1 with C synchronization 1. Voice data and noise data are separated, and among digital data, voice data and control data are separated. Due to the synchronization signal, the 4F unit 2 generates the timing 48 and generates the timing 13 such as the store pulse 2 (W) and the read pulse I+(R'). Error detection and correction of the controller 1 to roll data is performed in the error corrector 4, decoded in the controller 1-1-digital data 6, and output to the system control generator 7. . Further, the digital data is written into the memory 5 via the error corrector 3 by a pulse of 52 (W), and is written as ++(
R) is read out and the time is expanded by 111111. In addition, is the digital data error 1□J correct after time axis expansion processing? l'J, sea urchin 4111 and C are also good. This time-axis expanded digital data is
The analog converter 9 converts the analog signal to m1 audio A.
It becomes a signal. Various control signals are sent to the system control generator 7 according to each control command decoded by the controller 1 to roll decoder 6.
A reproduced video signal is derived through a screen processor 8 which operates according to predetermined control signals on the other side. However, for the digital data insertion block, for example, the image is processed as a black level and output. Further, from the player controller 10, 1=1-
signal is derived so that the stop signal of VD1
1: Control of PIAY, etc. 10 As described in Figure 1, the first block a in one field contains a combination of clock run-in signals and data synchronization signals for clock synchronization and data synchronization. This signal is used to establish tally and data word synchronization at the beginning of each field. This block 11-1 is called a field sink, and the details of the configuration of block 11-1 are shown in FIG. 1O. The data transmission rate 1- is 40εI f +('(:), and no digital data is inserted from the falling edge of the 11th sync to the 64th p1-.320 bits should be used for the field sync data array. 5320 bits are further divided into 10 units (32 bits, 1 unit, each unit has 1 line L1 synchronization and 0 note data 1i1).
Constitutes a 1vJ signal. 32 hits 1~, 2/l pits 1~ or clock run-in signal, 10'IO・
... 10 continuous signals are inserted for 12 cycles C, 13, followed by a synchronization of 111000100 (i
L>* or 8 bits are inserted. These 2/I
The sum of I~ and 8 bits t132 bits 1-1i ()
10 players are inserted consecutively. In addition, for 71 nj~bo 1, a considerable amount is taken to 24 pits 1. In this example, this iJ1 column is inserted in 221H with a=1.Block l ) to (Yobuni 1tsuku C to 111
Various controls on the content of information held by one person (iJ'5
．． J or being a matchmaker. When inserting a gauge data into blocks b and C, the effective data range (as shown in Figure 11) is 320 pitches 1 to 320 pitches as in field sync.
4M is formed, and from 1 to 1 sync to the beginning of the data string is 64 pips 1 to . In addition, the front porch is equivalent to 24 bits 1 (there is a field sync shown in Figure 10 and all < trIJ-like C).Also, among the 320 bits, there is a 24-bit clock at the beginning of the j'-evening paper, and a 124-noise clock. The run-in signal is followed by the data synchronization signal for 8 bits 1~.The remaining 288 bits 1~ are divided into 36, and the 8 bits 1~ (
The information is in units of 1 byte). J3 block b
In the case of the present invention, each control signal is recorded in the case of the present invention (4H is assigned to -C, 23, 24, 25, and 26). Also, the information in units of 8 pieces (~(1 by 1) in block 1) is completely interleaved and error corrected.Next, digital data is recorded in block C. In that case, 26
1-1 is 1 block, maximum of 9 blocks in 1 field. Digital data can be recorded in a maximum of 18 blocks in one frame, and only full-scale digital data, full-scale images, and a combination of digital data and images are possible. ]”
The original data in a block is constructed so that it is interleaved within one block, and either the filters are alive or dead. Next, Figure 12 shows the reproduction system! , -1 body example 11-1 is smaller. In the case of the present invention (>''-rSitalf-Ichiyo 1.L Senma 1111 compressed digital data (
This is a device for adding audio to still images. 1. This device is used to amplify the video signal. Minmae Ruruo V synchronous separator 12. The threshold level from the amplified video signal is automatically set to the optimal value by following the level of the computer, and the 1-1g video image is converted to NRZ (NON l dog to T Ul dog N1 −○ Z
AI'C circuit that converts the data into a digital data string] 3. Digital data string Karini-1 Tsukran-r
The RUN-I N detector 14 detects the digital data string and reads the 8-bit data string) and detects the IJ times the signal and reads the digital data string by 1 to 110 each.
Detect the starting position of the node within. In the same way, read one line and convert the data string to 8 bits 1 to parallel data S/1) Converter 2/I, 23 to 26 in the field
A switching circuit 16 that detects the current time, separates the control data signal, and switches the output; a clock extractor 17 that extracts a clock component from the data string based on the RLJN-IN signal; and a PLL circuit for the extracted clock. Or

[
A system that requires locking for system operation.
Clock generator 18, obtained from the system clock generator
from the TV sync separator 12 based on the clock signal
Separated ■, 1” sync signal and data synchronization detector 1
2 (controlled by the detected signal at the beginning of the captured data)
℃, timing signal that generates various timing signals
Generator 2, which receives control from this timing signal generator.
Detects field sync, clock run-in signal, data
At the beginning of each field based on the periodic pattern, the clock is synchronized.
field sync detector 19 to establish data synchronization
．． Separated from the switching circuit 16
Container for temporarily storing the code 1-〇-Rubatufa 20. con
Control read from troll code buffer
” - Error correction process for error r'il iLL1
2 A series of error correction processed 'n1~roll codes
C-arranged interleaver 2 according to the control sequence of
1. Decode a series of control 1-roll coats. System a1 controller that generates various control signals7. Sith
Insert the large capacity Gl meter into L5 from the system controller.
When reading, the initial address is ``Ko'k'' (!,?
(, Read data in units of ε3 pits++, +1+
= Clock pulse is obtained from timing signal generator 2 and clocked.
Perform run mill up processing and add to buffer 7 meters [S5]
Address counter 21 that supplies the resuiha number. Bu1-1
Digital data in Tsuku C is timing 111 No. 5
/l-1542J, digital signal at f2 (W)
Store data -11,'J, and signal f+(R) (-read
H) Hanoff Memory 5, large capacity buffer I
Error 9J stopper that performs correction processing with L error in the middle of 10 3.
Adjustment processing 1jl+ data is made into a continuous data string.
Conversion J run interleaver 23. series of digital
,! - The timing signal generator 2J, which can be obtained by
Timing of (R) - Process C and Alog Hen (Joriru)
Digital/analog converter 9, system system tal
l im 7 J, S V D P O) 7;: M (
1) R111'611 (No. a @ Sl, +j
V D P -] >l'-Ll-L signal to V D
l) to the brake 17 controller 10 (consisting of
Ru. A3-C1 analogy for such a configuration is the pattern shown in FIG.
Recorded video with turn A) A-Matsu]
In case of IUJ interval A, v o l) is normally ■ raw operation.
I do. During this time, the digit inserted in block C
The file data is sequentially stored in the memory 5. In the next period B, still images or frame-by-frame playback can be performed using V D P#.
Perform 3 constructions - B's story. This 11, in memory 5 (6
The stored digital data will be output, but this
Data/J< IIJ n'J @ fi KM a t
L TaQ FJj 7' Inter/L/ Chi Tatea
If the still image or
is output to the frame-by-frame playback 11,). In addition, during period A, the television monitor
J3 in the surface processing section 8 is clamped to the black level.
Appearing Zuru J, it will be done. A video mat signal that follows the pattern shown in Figure 7.
No. 14 - (Ma, +ilJ 17j△(j1Jj
The digital data in Kuno 11 Tsunono C is met/\
Stored sequentially. This 11! Part 11 of the υ7Nita screen
Minutes are 11)
, an image appears in the middle of Mu town. Historically speaking, V D I) Noji i' 7I output*;:
:J, Rino 11” Raw Video A-A-Matsu 1-I, J:i
l;I, it is manually amplified by Jade A Nononbu 11. child
The amplifying horn of is applied to the synchronous H unit 12 and separated.
17 each. ．． I IsuJ(,'iL; (V, 11
> [, 1 timing signal supplied to 1 human power of optical instrument 2
It will be done. In addition, the amplified video A story 5-;
13 inputs. This AIC circuit circuit,゛-
Detect the peak and petestal level of the data, and
Threshold automatically sequentially without following: 1 small hell 1 ~ level
Set the bell, Pino' 71 (, ; ; Shih attack N1
Extract the noisy data string of </1. taken out
l'< U N -I N signal from one digital data string
The detector 14 detects the timing of the timing signal generator 2.
(24 hit 1-12 recycle under control of 211 signal)
Detects the run-in signal. Output of detector 14
Normal data based on the "Tutarain signal"
Clock extraction circuit 17 that extracts the J component from the column
applied to human power. Extracted and Utsuk components are system
is applied to the clock generator 18. In this system clock generator, the extracted clock
A system synchronized with the data stream is operated using a PLL circuit from the components.
Generates a system clock for operation. system
The clock signal generated by the clock generator 18 is
is applied to the timing signal generator 2. timing signal generation
In device 2, based on the clock signal (4), the synchronization signal (V,
1-1), within one field
22 Detect HIEI and detect field sink η Ruta
applied to the control terminal of the second field sink detector 19
Generate timing signals. Also check 23-26 +-1
Output controller 1 - Timing for separating roll data
generating control signals. Also, 271” was detected and 27
The control signal for fortune-telling reading of data after +-1 is also available.
It has occurred. The serial data string output from the ATC circuit 13 is data
I+jJ JIIJ detector 15, S/P change J% detector 2
4 is applied. These data (requires I-1)
1) Read the data, 1)
5] Each 11 (JJ5 I-C Teddy synchronization signal detected)
Then apply this to the timing signal generator 2 and start f-evening.
Set the position to T and keep the synchronization relationship between the data and the timing signal constant.
Keep it. Additionally, the S/P converter 24 converts serial data into 8-bit units.
Convert to parallel data. 8 pin 1- data is cut
It is applied to the switching circuit 16. Timing in the cut 8e circuit
A signal indicating that the number is 23 to 261-1 is sent from the programming signal generator 2.
If there is a number, please use the 21st f〕-le''-dopatsuno F20.
Also, it is in Agetani outside J-me (large capacity hanging buffer memory 5)
When I apply the voltage, it works fine. -11, Y memorized in CON 1 Herol code Batsuno 720
The input controllers 1 to 2 are manually operated by the error correction circuit 4.
is applied to Error correction circuit stops errors lfi iiil
The control code is the deinterleaver 21's control code.
Applied to human power. The deinterleaver is in 1 control order [
This control 1 - Sorting role codes - (System control 2
;Apply to 7. In the system controller, the control code
decodes the code generated from timing signal generator 2.
Writes digital data based on timing control signals
control, screen control, large buffer memory address counter
Initial settings of the printer 22, digital data capacity, management,
It is carried out. Control-related signals such as player operation and stop are sent to the player.
is applied to the controller 10, and in this player controller the player
17 into a driving signal and supply it to the player.
There is. Next, timing signal generator 2 outputs 221-1.
It is applied to the control terminal of the field sink detector 19. inspection
At the output device, the clock run-in signal and data synchronization are repeated.
In the field from the return signal, the daylight signal and digital
The clock extraction circuit generates a standard of 111J.
17 and timing signal generator 2.
There is. Next, detect 271-1 from the timing signal @ generator.
The output signal and control code are decoded and
Indicates that digital data is recorded within the lock.
When the code is decoded by the system controller 7, the system controller
Timing signal light 4 according to the control signal generated from the controller
1! Signals of +2 <W) emitted from 2 increase successively.
It is temporarily stored in the capacity buffer 5). one
When the storage of a fixed amount of data is completed, the system controller 7
commands the player to capture a still image at a specified frame.
Therefore, play 17 starts still image playback. Big
From the capacity buffer memory 5, the system controller 7
and sets the read start address in the address counter 22.
and f+ (
R) signals are read out sequentially. Large capacity memory 5?
The data read out sequentially is applied to the input of the correction circuit 3.
The error is corrected by the error correction circuit 3, and the deinterleaver
23 inputs. In Di Interleba,
D/△change J instead of the original data array! i! ! person of vessel 9
applied to force. In the D/A converter, analog audio signal 5
(J conversion and output as voice.The voice is output and output as voice.
While the player is playing still images. Enrollment r7t bar
The specified amount of data from buffer memory 5 or 81
Then, according to the program code, -reach or play.
This will supply control signals such as A to the player. Here, the RUN-IN signal detector 14 and data synchronization detection
15 and field sync detector 19.
The method of synchronization and data synchronization 1v1 will be explained. Each fi
In the field, each of the 221" field sinks
10 clock run-in signals and data
Clock and data synchronization are first ensured by the data synchronization signal.
Stand up. Clocks included in Zunawara clock run-in
The component is extracted by the taro clock extraction circuit 17 and a clock is generated from it.
The PLL circuit of the generator 17 is unsynchronized. Also, data synchronization
No. J: Detects the start position of the redata and uses this as a timing
(apply g signal to generator 2 to synchronize this circuit with data)
Ru. Clock run-in signal and data to field sync
The dropout contains 10 synchronization signals each.
Even if part of the J: signal is lost due to
Ensure clock and data synchronization within the sync +3
This is for the sake of becoming. One synchronization with field sync (:J
'JWare is at the beginning of each 14 that contains data.
RUN-IN signal detector and data synchronization detector, respectively.
C Detected clock run-in and data same Il+] <
i >-', -(1', clock phase shift and hill l-
Corrects J error and maintains clock synchronization and data synchronization.
I have it. Ma/j, the first clock run of each 1-1
The input and data synchronization signals are from L such as dropout.
If the data is out of synchronization, synchronize again at 8.
role 11 b. Figure 13 shows data synchronization detector 1! ] A concrete example of this is shown in Figure 1'
, and Jj is applied to the pattern filter 151. -Evening synchronization signal pattern 1100100 was detected and detected.
A pulse is output. This detection pulse [yo chord or false de
IjJ ljr: 1'
lb, so use the Nant gate 152 to
The circuit after J and ri is added to the gate signal (DSG signal)
The input state of the detection pulse to C is controlled. This inspection
The output pulse is re-notched to the latch circuit 153, and the output pulse is
C through the agate 154 and protected by another wrap circuit 155
held. Then register 1 to the next 7 bits 1-shift 1
56 in sequence. MSB of this register and its time
The detected pulse does not match in the previous NOR gate 154.
A matching condition is detected. When a match is found, the sync pulse
The output is 2 2 +-1 as shown in Figure 10.
detects the 101J data synchronization signal and then outputs a synchronization pulse.
After 231-1 shown in Figure 11,
immediately after detecting the data synchronization signal of shoulder 1.
Is that a J? The synchronization pulse output timing is
different. Therefore, the generation timing of the synchronization pulse is
A gate signal (LDG
(signal), and the circuit is shared between 22H and later.
We are trying to make this happen. Furthermore, the AND gate 158 is a shift register.
The initial clear A7 of the star 156 is inherited. Here, in block C, the image and digital data
It is necessary to distinguish between the start of the image and
Display the next block at the end of the image as control data.
and insert it. An example is shown in Figure 14, where the image
Nono fH Mari as S-1-A RT BLOCK
4 pin 1 - Use C. Also, the value of 4q is 1
to △ hexadecimal). Set the next block after the end of the image as END 13LOCK.
Use 4 pits 1 to J3, take ('Iru value CL 2
-A (hexadecimal). Na J5, this take ('l I +
+'IL, L, block C is further divided into sub-bucks "-"
There are various changes to the broken x candy. In this example, 1,
In the case of 9, A3C), Table 1 (nY friction I of the invention)
ll%! U2 written in IC at the end of the Ming Dynasty), the various types shown in Figure 5 are
Bidet Δf A-pine 1 signal and S T' A RT B
LOCK, IEN)) 13 LOCK's
It shows the corresponding code for each code. Figure 15 shows the insertion position of this image information using an indication code.
FIG. 9 is a block diagram of a playback system that controls the playback operation;
The back l-1 of the synchronization signal divided by n1 in the bind-off separator 1 in the figure
Detect 261-I It of sink J- and feed to Jξ
J25 binary counter 25 and this counter
Clock the pulses output to the 1G count 11.1 of the
Output Q becomes 1 as a clock input, and output Q becomes O with a V sink.
A fritz button (FF) 26 is provided such that
It is. The Q output of this FF2G is the output of the AND gate 27.
connected to the input. The other input of the gate is 1”
The link signal is connected. The output of gate 27 is [F
The output Q of 26 and the AND logic of 1-1 sink are taken.
is output. In other words, the 27th and subsequent l' sinks are
It will be output. 1-1 syn after this 27th
26 digits cleared by V-sync
There is a counter 28, which corresponds to the counter in block C.
A counter that detects rivers in blocks 01 to C9.
be. In this example, m=26, so the 26-decimal counter
It has become ta. Count operation f'lE with key 17ri signal of 26-decimal counter
, and the decimal counter 29 cleared by V sync is
be. This counter is 1 nub block in block C.
and Q is 1 to 1. Of the outputs from control decoder 6 in FIG.
Temporarily stores the 4 bits 1~ of the tart block code signal.
Similarly to the 4-bit latch 30, the end block []
4 bits of code signal are stored in 4 bits
There is a Trudge 31, and there are 4 Trudge 30 output signal stations.
On the other hand, each state of the decimal counter 29 is
/I bit output 1, numbers Q1 to Q4 as the other input
Then, compare each Hira 1- and if all the bits are equal, then
A coincidence circuit 32 that outputs a pulse and a 4-bit notch
The output of Pu-31 is human power on one side, and Behit man on the other side.
Calculate the force between Q1 and Q4 of the decimal counter 29.
There is also a matching circuit 33 which outputs a pulse when the tongue is off. In addition, the pulse (;iL't
is a clock input)j, and this pulse is manually input l+,
'l tJQ output becomes "1", and the output of the matching circuit 33
V-sync (i15'
:l, and Torara's signal is l[if each I>
, or output horns of Oagoo 1 to 34 (-Q output?
l Oj +,,,m% FF35 and this Q output?
When [1] is connected to the a side, is it the Q output horn of F F35?
11 of l-0,1. '+ LZ The switch connected to the l+ side
switch 36 and a mask that forcibly covers the screen to j, jj level.
There is a skinning circuit 37, and the switch 36 has J5, and a
When connected to the side (, one person outputs the video A Buddha number
However, when connected to the b side, the output of the masking circuit 37
It is structured to produce power. Furthermore, “F35’s
The other output port is connected to the AND gate 38 and is connected to the official bag.
Application of power pulse +2 (W) to family memory 5
It's in control. With such a configuration J5, images and digital signals are mixed.
The video format signal is applied to the signal separator 1
is applied to the a side terminal of the switch 36.
Ru. Among the signals separated by signal separator 1, V sink is
When applied to the CL R terminal of the 25 binary counter 25,
CLR terminal of FF26, CLR of m-ary counter 28
terminal, CLR terminal of (×1-1) base counter 29 and A
It is applied to one input terminal of the agate 34. V-shi
25 binary counter 25. FF26. m-adic counter
2B, (x+1) base counter 29 and F F35 are that
is set to the initial state. Next, (separated from g separator)
The 1-1 sync is the 25 binary counter 25
At the same time, the voltage is applied to the terminal Ck, and the ant
-j) human power yy1: [IJ is added to J-. . 252 jg 7J counter 251JN I SC1V (
C>;Li2 and a card to calculate the helix in each field.
There is Unta C. Each field has d3 - (this counter
This is after the V sync has started up and the
Straw 11 to 1" sink pulse or applied stone
Describe the down and up movements. Also, 1-1 sink 16 times
Generates a pulse after counting. This pulse is Nl5CT
This corresponds to 261-1 of each field in the V signal. This pulse is applied to the FF26 glue []tsuk terminal ck.
has been done. ``In 26, apply a pulse to the child.
Logic output 11 is output from the Q output. FF2
6 is the flag role; after 91, V after 261-1
Sink or C+ t<O;:: Sinking Q output applied to child
Power becomes logic ``1''. F F 2 Q output of C3
The horns are applied to the -h human power of Andogoo 1 to 27.
There is. The other input terminal is 1111 from the signal valve 1.
l': l-1 sink is applied. Therefore,
From Ando Goo 1 to 27, 27 +-1 or later 11 syns
will be output. This is the screen power 1 in Figure 1.
1 from block C in the memory is the m-ary counter 28.
The signal is applied to the clock terminal Ck of the clock terminal Ck. Here, the ■adc counter manages the sub-blocks of the block.
This is a counter for managing In this example, ■-26
be. The 41j output of m progress counter is x+1 counter
is applied to the clock terminal Ck of the printer 29. ×-t
The linear counter 29 is the number of blocks in the block C.
This is a counter for managing the position. This counter is
, C's territory 1. V sink is not limited to f but also in the Q region.
It is p, X+i base of Karan 1 to Jru. In this example, since X is 9, it becomes a decimal J counter. Book
The output of 4 bits from TQ+ to Q6 indicates the state of the
The forces are applied to one input of the matching circuit 32, 33 respectively -
There is C. On the other hand, the controllers 1 to 1 separated from the signal divider 1
Star 1 to Blots that indicate the beginning of the image in the tool data
This code is applied to the human horn of latch 30 and is temporarily stored.
It will be done. The period to be memorized is one field or one frame.
period. The output terminal is the other input terminal of the matching circuit 32
is applied to In this minus number circuit, we compare each pin from 1 to
If 4 hits are equal to t, a pulse will be generated at the output.
, 41 sea urchins - (1 sea urchin, similarly separated by signal separator 1
The next one after the end of the image among the
A small L block cord wraps the block L1 can bow.
31's human power and the output is the matching circuit 33's other human power.
is applied to each bit, and each bit is compared to determine if all 4 pins match 1- or
Then pulses will start to be generated (3, - several circuits)
The output of 32 is applied to FF35 (1).
There is. Also, the output of the minus number circuit 33 is Δ)'G+-3/l
Human power is applied. Oagoo l-1,,1F"'
C is applied to the clear terminal CLR of F3b. l-
' F 3 b is the coincidence pulse of the coincidence detection circuit 32 or applied
Then, the output JQ becomes "1", and the -number output circuit 33
When a coincidence pulse of 3 is applied, the output Q becomes I'OI.
. 'cL J) The Φ output is exactly the opposite of the Q output. ,
The Q111 force of E, F3b is applied to switch 36.
Q output of [Ca2S, 1-1Co31] is 1 of logic [1]
1;'l On the a side, logic rOJ") Uj combination 1) I≧ on the side
There is a switch set to
Applied to the input terminal. The other side of the and gate is a tie.
From the timing signal generator 2 (see Figure 9)
lj input pulse +2 (
W) is applied. Therefore, the AND gate 38 is F
F35+7) Q output is [)J (0 o'clock, fortune-telling pulse
/2 (W) is supplied to the Daikan single buffer 7 memory 5, and the signal
Sequentially storing the data separated by N1 in separator 1
become. For example, in the case of the waveform shown in Figure 5(C), the start block
The court of the block is 3 and the code of the end block is 8. At this time, 3,8 is set in the latch 30.31 and -C
There is. Initially, the Q output of FF 35 is "0", so
, the switch 36 is on the b side, so the video output is
The output of masking circuit 37 is derived. masking times
)”811 synchronization signal, video signal excluding color burst
This is a circuit that masks the black level.
The screen turns black. Also, the Φ output of F F 35 is logic [-
1", the AND gate 38 is +2 as it is.
(W) pulse is output and the buffer 7 memory 5 has a signal.
The data separated by separation device 1 may be read one after another.
It becomes. Next, enter ×1,11 counter 29 or 3. Match circuit 3
2 generates a pulse C1 the rising edge of this pulse
Set the Q output of FF35 to 1-1. Therefore, the switch
Chi 36 is on the a side, and the human power signal A signal is not displayed.
Step 4 to see the image being output. The Φ output of 1-135 is rO
4 to J (, no pulse is generated from Goo 1-38
, Follow C1 Batsunol! There is no writing operation for [Meshi Sushi].
Kupui. Similarly, when the ×1,011 decimal counter reaches 8, the matching circuit
A pulse is emitted from 33 and passes through or gate 35 F
C1 of t35, go<9i; will be applied to the child
Then, this l-1(J)Q output becomes “0” and the switch is turned off.
The circuit 36 is 1) (rule), and the masking circuit 37 is in and out.
-11 to 416°, a black screen appears) J
become). Also, the 0 output of 1135 becomes “1”.
The output of An1-Goo1~3ε3 is the timing signal light again.
1- A large capacity battery is generated by +2 (W) emitted by the light 41 from the device.
data separated by signal separation
will be stored sequentially. The timing of the above operations is shown in Figure 16. In Figure 16
is the video signal of the first field of one frame of Nl SC.
However, regarding the second field's Δ signal,
It's the same as Techi. In addition, in the above example (Yo, image and digital
To identify data and detect digital data location
the block where the image starts and the block next to the end of the image.
Insert data indicating the
l of digital data? il beginning block digital
The next block after the end of the data is smooth and the digital data is
The same applies to those indicating the start and end blocks of data.
be done. Insert 4-behind audio digital data (SW Sj-ta)
) is [only in the case of Noral, in the case of Spray A and for humans]
There are various programs such as explanations, music, etc.
This will be explained below. Figure 17 shows how audio data has various contents and types.
If you have poor sound quality, etc., please send a message to
FIG.
V, l-1 sinks are separated and these systems
The timing key synchronized with the
Imingui 1. ) is supplied to the binary retrieval unit 2. -h1 person
TsunododeAnoA-mat (also on No. 5 iJ△IC circuit 13)
The video signal between the replayer and this circuit is
Data for variation and variation such as HifΔdesk
In order to prevent reading errors, Iφ is input to the video signal.
The peak level and pedestal level of the data
Automatically (optimal threshold level) The data on the signal is waveform shaped.
It becomes a barrel signal. The video signal became a digital signal.
Clock run-in branching device 1/I Nyoichi C, Ri L1 Tsuk
The run-in signal is extracted and the -ltsuk generation Z
:18 Nyoderi 1-1 Tsutaran ini,, Same as >shi
/4II system clock is generated. The connected digital notebook with separate clock run-in is S/
The P converter 24 converts the ε3I nitrogen parameter from the silicon
The timing is correct for the real data by the signal from the 1-month generator 2.
converted. 8 pick 1 ~ Clock from parallel printer
Timing generator 2 from controller 1 to roll data separator 39
The control data is separated at the timing from
The numbering code described below in the control data of
Timing signal generation by code discriminator 40
It is determined and held by a latch signal from the generator 2. Zan
Control data other than the pulling code is timing
Control code with timing from 4m generator 2
It is stored in buffer j720. ]N1 herol data
Audio data other than control data that has passed through the separator 39
The data is stored in the large Φ buffer memory 5, but the
The address is specified by address counter 22. a
The f2 (W) signal is used for the address counter.
Connected to the system controller 7 input terminal
After the first address is specified, the next address is: Fz
(W) causes the address counter to count up and write sequentially.
It gets sucked in. Here, f2 (W) is the time axis [14]
is the transmission rate. Next is Daikanmo Bachun?・Clock read from memory 5
f+ (at l) is Leansoling+ -l; Discriminator 4
According to the output of 0 -C generated 1 non-pring 1'
b is applied to the D/A converter 9 to open the D/Δ conversion.
Command the beginning. Read l+, "l's first address is river
specified by the system controller 7 in the same way as when
Then, the address counter 22's run 1-up is f+
(R). →Non-pull cord is 2 pins
It is represented by ``-1-''-1 and latched by the discriminator 10.
However, the rimbling clock 9 generator 41 is a 2-bit
Based on this information, four types of one-lean pulling clocks are issued.
Although it is a live monkey, this system allows three types of 32KHz and 64KHz.
．． K11z, 96KH2 sampling clock is generated.
Assume that 1 and μ. These three types of υ coupling
The D/A converter 9 is operated at the frequency μ. Here'C voice j
Data is adaptive delta modicolation <ADM
) is digitized by 1/Δ conversion.
The device converts ADM audio data into analog r'fjB signals.
exchange. In addition, the 1 numbering of 2 pitsu 1 ~ ``-1-'' is changed to b.
The decoder 42 controls the switching circuit 43 and the selection circuit 44.
filters 45 to 45 that control and correspond to each code.
47 passed 171-1 non-pring clock 32
For KHz, +-12 filter 45 for band 2.5
．． When 64KH2, band 5K)-Iz filter
data 46.96Kl- (band 7.5K f-1 when z
z filter 47 is selected. Also, clock code
Each code stored in the buffer 20 and decoded is controlled by the system.
The controller 7 performs control according to each code, and the playback is started.
Control regarding the player can be stopped and restarted by the player controller 10.
Controls such as playback and frame advance. Next, the operation of the video software shown in FIG. 18 will be explained. sws data for still image 1 is sws data i, sw
s data 2. SW for still image 2 S Data is SW
S data 3. SWS data 4°Still image 3 vs. M le SW
S Chi') lfi S W S Chi')
5. Let it be SWS data 6. Also, the 2 bits in the control data
The Tsutonori assembly code is shown in Table 2 (detailed description of the invention).
(described at the end of the text). Control data t or data controlled by it
What is recorded in the room immediately before the frame of
Then, VDP plays back 8wS data 1 during playback f1.
Go to previous frame 11-1【'' - Sample with Renown-Yuu
Discriminator 4 determines that the matching code is (3/IKI-1zC).
Detected at 0 and zsws footer 1. Large capacity SWS data 2
Store in buffer image 5, still image 1 and SWS data 1
．． SWS data 2 6/IK t-1z sampling
Play with frequency - Rir. Next, at the time of still image 1, the SWS data
Is it the sampling playback frequency of data 3.8WS-J゛-Y4?
32Kl-1z (Device 40T-detects something, 5W
Store SV'-'yl 3, SWS/-Y4,
Still image 2 with a rimbling frequency of 32 K l-1l
Reproduce. ]・Similarly, still image 3r is 96 KHz.
will be played. In this way, the content and type history of SWS data are based on the original audio information.
Depending on the sound quality of the information etc., the ringing frequency f;! Change l and write
Recording and playback are also possible. Here, if the SWS data is monaural and stay A,
19 and 20. 19th
The figure is a block diagram of the reproduction system in such a case, and FIG.
Only the parts that differ from the above will be described. Con 1~〇-Leco
The stereo/monaural identification data inserted in the card cannot be recognized.
It is extracted and discriminated by a separate device 48, and the discrimination result is sampled.
clock generator 41. switching timing generator 49 and
Send to audio A output line switching relay RY+, 2
do. The switching circuit 43 operates according to the stereo/monaural discrimination result.
Switching timing signal generated from timing generator 49
Switches the analog audio signal according to the
It is sent to filters 45, 4.6. These filters
Removes high frequency components such as sampling frequency components. Lillet
-RY+, 2 is spray A, A-D depending on monaural
This is to switch the A signal. Next, using the bidet A-Fu A-Matsu 1 in Fig. 20, see Fig. 19.
Explain the operation of the block. Controls VDP playback and
WS data 1 1) U frame control 1~roll date
The stereo/monaural identification data in the
8, and the SWS data 1 and 2 are memorized.
stored in the memory. In this way, the lJ data is stored in the memory 5.
゛ - Reads out the evening when playing still image 1 and outputs monaural 11'' raw
? Yes. Next, control data for frame 1 of still image
It is determined that the spray is A, and the SWS data 3.
Store /l in memory 5 and read it to M1113 of still image 2
Performs video playback. Here, when monaural, Jt(R) is the I numbering frequency
is equal to the number, and at the time of stereo Δ, it is twice the limp ring frequency.
frequency, and the -Ch axis is thereby expanded. Ste
The relationship between I+(R) for Leo and monaural is the same for stereo.
If you want to make the same band blue when it is monaural, use stereo f+ (at I) = 2X (when monaural)
4+(R)). Therefore, the Zambringuk [1tsuk generator 41 is
, the above relationship is determined according to the monaural/stereo Δ identification data.
The data is read from the menu 5 by generating sampling. In the above example, the output of the D/A converter 9 is switched by the switching circuit 43.
They are separated in stereo, but if you put these two together,
The output of Daikan Saibanoa Memory 5 is separated by a switching circuit.
, connect a D/A converter to each separated output,
The outputs of the D/A converters are filtered through filters 45 and 45, respectively.
46 may be connected to a. control data is the data controlled by it
Suppose that it is recorded in the frame one before the frame of
However, it may be recorded in the same frame as the data to be controlled.
stomach. In the example shown in Figure 17, it corresponds to the sampling frequency.
L] - Use three pass filters, each band 1υ
I was using it by switching independently to
I-passita filter (basically a switch and a filter)
It is made up of
(transmission characteristics can be moved analogously along the frequency)
This can be done with 4 'U's. In other words, San
Corresponding to the pulling frequency - change the C clock frequency
Then, the WJJ value of each band filter is c′.
. Or use a microcomputer for control.
b Good. Figure 21 shows the switch dollar 1 filter and microphone.
This is an example using a computer. Overlaps with Figure 17
The location will not be explained. Separated by control data separator 39
The control data is stored in the microcomputer.
Midair 1. ’l and large capacity buffer at the time of reading.
[A1 reply letter Y) to A5] or play A7.
In addition to generating control signals and passing through the IC, the sampling frequency
Wave number switching: ll Todo deciphered and 3M! kind of sample
switching frequency and switched capacitor filter 51.
Control that generates tarok frequency]
signal generator 2. The timing signal generator generates a jujube insertion pulse f. (W>In addition to microcombi", -ta's fli control iA
Three types of limp ring pulses 11 (
R) and function as a filter in the corresponding band.
(B) Generate 1st frequency, Jt(
R) is Daikan Cliff Buff 1 memory 5 and 1/'A'&I'
A device 9, and f3 (B) switch doki 11 pacitafu
It is supplied to the filter 51. switched capacitor filter
The frequency characteristics are moved analogously according to the taro clock frequency.
The functions of each bandpass filter are performed. In A3 above, digital data corresponds to images.
Audio data, that is, SWS (SL Mountain Picture
Wit113ouod) data, but in addition to this
It is also possible to use an external compensator such as a personal computer, digital camera, etc.
Input rough 1 heu 1 a information related to the total signal processing equipment.
”, the recording medium is the same disk.
It is now possible to control the VDP and computer using
Usefulness arises. Therefore, if necessary, internal SWS design is installed in block G.
– Insert external digital data as well, and
To distinguish between the inside and outside of the data,
Insert the relevant identification information into the roll data to the link 1. 22nd
The figure shows an example of the identification information signal.
Internal and external digital data identification pins at predetermined locations within the data.
Insert l-Y? :J A3 :=, Y is "○"
If it is "1" then there is an internal SWS date, if it is "1" then it is an external SWS date.
It is spelled digital-7゛-evening. Also, in the diagram, 1st grade
As such, the internal and external controllers 1 to LJ- are located at different σ month 91 fixed positions.
Also insert the file identifier X, and if X is "0", then
The following two data items are for internal control.
1-roux is set, and if it is "1", it is for external control.
1 pin (~I) - If you have a Renault motor, you can do J.
Rikoto I (XJ, Su, outside of personal computers, etc.)
9 becomes j'J (i'a.
People's Video No. A-ents l- (L, number includes internal and external
Mixed digital data and
The signal is input manually to the signal separator 1.
The screen processing unit 8 is also manually inputted. The separated sync signal is
A timing generator applies 20 human power. signal
Separator 2J, S'tj face 1, -1 door - day
is applied to the human power of the error corrector 4. Also, inside (?
, j:; ) seat or 1, the external seat is
Timing of f2(W) that can be generated by the switching signal generator 2
The signal is sequentially transmitted to the buffer memory 5 for time axis expansion.
It will be stored. Next, the buffer memory 5 is filled with timing.
output from the signal generator 2. Read C to f+(II) signal
and the error corrector 3 is applied to the input. Correct the error here
Correctly processed internal (audio) or external data is data
))t! Applied to Ifer 520 input. C separation here
The resulting sound μm data is applied to the input of the D/Δ converter 9.
It will be done. The digital signal is converted into an analog signal by the D/A converter 9.
It is converted into an audio signal. This Lljfz(W>
> fl (R) By maintaining the frequency relationship, the audio signal
11. The ¥ axis is expanding. Output from error corrector 3
Control data fJ controller 1 that has undergone correction processing
- roll] - dode] - applied to the input of da 6. Here, at the position X in the data shown in Figure 22,
The internal control data is output using the redata selector etc.
Applied to the input of system controller 7, external = 1 to 1
- file data output to external system interface 53
applied. The internal controller, which is one of the outputs of the system controller 7,
Game by pin 1~ of position Y in ``-run [-]''
Ijikurunota system i+++ f, >; is the data
From J, the data portion I is applied to the separator 52.
The il unit 52 connects the external 1i1i footer output to an external interface.
Marked IJII L' (1° system system) on Ace 53.
Fortune-telling and reading of one of the outputs of Goki 7 (Yomeshiri 1)
C is applied to the cutting control terminal. Also, other outputs are
Timing 13''; 3 Connect the screen to the 1 and 11 terminals of the
To the human power of the processor 8:: The people are applied to the end. These two
With the surface controller, the image with a 1:3 ratio of mountains is output as is.
, Also, the digital input part is replaced with black 1 color and output.
I'm starting to work hard. Play 17 controller 10 is seeded from Cislano, controller 7
J, S, V D + one +:...+J,
, through i:';I'l (f, frame-by-frame advance, etc.
The output of the interface 53, which transmits the signal, is
Applied to the external input of the external system (Bathone) 54
Ru. In addition, J, -)C perform various operations on the computer 5i.
I can say it. Also, outside of PC 54? J11 output (general 1,
Play Xl control 211 request, SWS playback control is considered.
) is applied to the human power of the external interface 53.
Ru. This signal is applied to the panono of the system control 7,
Processed along with roll data to internal controller 1. Pasoko
1<G13 (three primary colors) output of the main color 54 and the screen processor 8.
The processed video output is printed on the input of the external screen processor 55.
Added -C. Control 1 ~ Roll Jin from PC 54
A signal is applied to the control terminal of the screen processor 55. this
The screen controller has video output and RGB output. Switch video/RGB composite output and output
Natsu (there is. The keyboard is 56, which is a general PC.
It is an input device. Outside of a computer, etc.? 1tll digital machine! -Evening
Video A mixed with internal SWS data in J3 in VDP
) Other examples of A-pine 1~ are shown in Figure 24. In this example,
Block C in each field is 3 from 01 to C3.
] Nobubu 1" Tsuku (this is called a block here)
). The contents of segment 1 are still images.
- There is SWS data to explain system 3).
Blocks 1001 to C3 and the next fool'
2 C1, C2U) -, f Cl block total of 5 blocks
Garai iru 3, [・Kumen 1-21. ．． 1st all day
(1) riCl tsuku
and field 3's C1-(:3's b[-1 ivy,
The combination of Cl and C2 in field 1
' Consists of 0 blocks. In addition, 03 of file 1-4
Zorotsuk's black level images are amazing. These fields,
To segment 1, block related (J11) information and internal and external data.
The relationship with the data identification code is shown in Figure 23).
The protsukukaran 1 to number are the apparatus shown in Fig. 26, which will be explained next.
In block [II Tsuk 7 J counter 63 /, J run 1~
It shows the content. Tishikuruno-ri is [! Kumen
No. to segment 1 for every 1~ is (q), and each L/cumen
j-'s data Ld is 1" number of people (4 people) (
I spell it as something. Figure 26 shows the bit and 4 A-net signals shown in Figure 24.
There is a reproduction system block suitable for reproducing the issue.
57 is the digital data other than controller 1 to roll data.
This is a circuit that cuts and outputs the data, and 52 is the SWS.
Data to D/A converter 9, other digital data
selectively output the data to the interface circuit 53.
This is a switching circuit. 63, the data is manually stored in memory 5.
Togi, click from 1 to 1 every block cycle as necessary.
The pulse of the system clock generator 18 triggers the reset 1~
5B is the block [1] counter, and 5B is the load to controller 1.
Is the digital data from the rule code SWS data or something like that?
Decipher the data identification code to determine if it is external data other than
It is a data identification decoder. 59(J,'nt)
Roll code J, 4 blocks that configure each digital data [
] Indicates the number of ticks, decodes the J code and sends it to comparison circuit 01
- 60 is a book number decoder, and 60 is a book number decoder.
[:J-/Indicates each ceramic number from 1 to 2 from the data recorder.
]- code and outputs it to the comparator circuit 61.
No. J Korg. The comparator circuit 61 receives M readings from each encoder 58 to 60.
Lamen 1 ~ number, Bu 1'' number of ivy, data identification code and
J [SWS data based on the output of the counter 63
A block of 1 is read from the memory 5.
The level is output to the switching circuit 52 without reading the block of data.
When the power is overturned, reading the data of the command is completed.
Then, reset the F F Ci 2 to -reset 1.
Luz light 1-1j. In addition, -1 n 1 ~ roll data
Each decoder 5ε) and ~60 (controller to be decoded)
-+-1- other than "-" is 21-1~Roll code 1~
-11,'l is stored in the buffer i'20. ,F
F 62 is set by the output of the system controller 7.
J5 has such a configuration, and the lZcumen l-1 in Figure 24
Sequentially from the first data to subb: L, legmen 1
~1 and segment 1 to 2
It is stored in file 1. Continue (, VO2) or replay γ1 still image
System control as soon as growth begins; W; 714 /'Ro
Click counter 63 for 1~J +141'!
, take lmeshiri 5 into the state of protruding the bladder. [1 light to kumen 1
Riri,! When the reading of the lock is finished, the value is changed to ++5.
Counter C')3 becomes "1" and from then on
Itsuk1. Each time it goes on sale, the power increases by 1.
1, this 1B match corresponds to segment 1.
-f +, the four counters are 1-0"
"4" (Ha! - evening identification 21 - corresponds to code "1")
(See Figure 25), which is US data.
An H level indicating this is sent to the switching circuit 52, and the segment
Blocky straw counter corresponding to point 2 is r5J.
to "10" corresponds to data identification code 1101+
1L level, indicating that it is external data.
The signal is output to the switching circuit 52. When the counter 63 reaches ``11j'', all data is read.
lapses, the comparator circuit 61 resets the FF 62.
However, the Q output of this FF causes the memory 5 to stop reading.
Ru. In addition to the above operations, the contents of J.
It is output from the D/A converter 9 as a number, and
The contents of are sent as external data via the interface 53.
It is output to a computer etc. Next, for still images, not only SWS data but also characters and
other]-code, and also record the relevant SWS data and characters.
etc., each with different contents can be recorded and played back.
If you can choose these arbitrarily, it will help you in many ways.
It becomes possible to apply The following system will be explained below. Figure 27 shows the description of BeejAf A-Matsu 1~ of the system.
This is a V diagram showing an example of recording, and each control
One frame before the target image and digital data
It is recorded in block b. Also, for one still image
It has several types of text and other data with different contents.
Digital data is recorded. In this example, there are four types of
The sounds 7jj and f-y are recorded. Figure 28(A) is
This is an example of fame and character data, and (B) is similarly
In the fame example of the 4-second class, (C) is 4 types of f-ta, but data
Data 1 is data C to be compared with external input, or data
Data 2 to Data 4 are character codes (there are. Figure 29 shows each
These are the seed control codes and the corresponding processing contents. ]−
All codes are ASCII = 1-1~(゛. Figure 30 shows the second
Figure 7 bidet Δ) A-Pine 1 to J3U Figure 28 (A)
This also shows the controller of each frame in the case of
It is. Figure 32 shows an example of this system.
FIG. 2 is a block diagram of WS De'-Yu. In the figure, the control code of the previous frame is stored.
This memo indicates that the buffer memory 20 has been set up.
The controller 1-roll code is read out from the controller and decoded.
Post-processing is performed. The system controller 7 is a digital
Whether the data is SWS data, character data, or
It is determined whether the data is compared with the external signal and the data is sent to each block.
control to supply each data. Also, the video signal
Either directly output it or set the screen to the black level, or set it to this black area.
Display characters or add characters to the video signal n-=
It also has several control functions. Unawara, character buffer 6
5 and the video processor 8 are controlled so that no video processing is performed.
It will be done. The character buffer 765 is displayed during image composition, etc.
This is a memory that stores the character code of a character by -11.5. The audio/text data in Figure 28 (A) is converted into the video in Figure 27.
Each frame when recorded on a recording medium in the format
]n1~roll]-do recorded in block b of
Figure 30 shows the contents of ℃1.Generally, the video signal is
Playback is performed in the order of odd and even fields. Most
First 61 - Noy J Ledo's block a part is IJ1
be born. Recorded here&? (internal control)
Since the command is processed inside the player, the 5WSI
) (Adding one voice and data to a still image) Dego J-
In the evening, there will be no 1j(.) Next, write the part of block b.
The control code 1-11 before this frame is
Screen and audio control n++ is performed according to the instructions. Next, part b
play the next frame's controller 1-code within 5WSD.
Odd number f of con 1 ~ roll ni+-l・hatsunono'meshiri
-11) is stored in the upper rear of the field. Next, play part C. Of what is recorded in part C
The content is a normal video (if available, an image and 2 t” LJ
Supplying each signal supplied from the play to the outside
become. Digital 1D data C is that of the previous frame.
Buffer memory for specified digital data
, and the screen and Hatake 1:j become Minote. Next, the playback of C is completed, Q is 111 cows, and then the even number frame is
Re-Field-Zuru≧10ko4I: Odd number fee
play a, 1) in the same way as the 2, now [good LL even number
5WSD control code recorded in field b
Similarly, control
r-store in the field area. When the playback of b is completed,
The control code for the next frame is
Troll code buffer 7 was read into memory.
Become. Next, there is a way to play C, but in this frame
The processing of C in this frame is similar to the odd field.
Follow the control code loaded in the previous frame.
This field is processed in the same way as the odd field.
=J correct processing of the control code read in the frame
, de-interleaved and decoded each within the system control
A control signal is sent to the unit. The playback of c and Q ends.
and before playing the next frame,
Read in, output the control signals sent to each part, and display the image.
It handles screen, audio, and data processing. Next, this will be explained in detail with reference to FIGS. 27 and 30. In Figure 27
Play frame (A). Δfvl, PM, DAW
01006018~DAWO300 (3078 code
is stored in the buffer and corrected by error corrector 4.
1], the second control code that has been processed is
The stem controller 7 decodes each control signal for control output.
Let the latch. Note that this frame C is
(Since Φ (video) is recorded, the decoder's video and
and audio output, each output of the player is supplied externally,
The sea urchin is turning. Next, frame playback in Figure 27 (B)
is set in each control section in the system control prior to
The signals that were generated are shifted and are used to directly control each part.
Ru. At this time, ΔM is A-data r A output goes to mu1
The code is not shown (the audio output will be from mu 1).Also, since PM is a double-sided mini L-l-, the screen will be black.
The video is output. Each block is then played in sequence.
In step 1), the control code for the next frame is read.
In C, the specified SWS digital data
is stored in a large capacity buffer memory. in this way
Therefore, each frame of (C) and (D) is also 21st 11-
In order to control the next frame, the
In the decoder 11 times before 1 frame before
It is read and each control is performed in the next frame. When playing frame (E), frame (I))
The (E) frame is controlled by the control code read by the frame.
be done. First, the AS has an audio output of 5WSD.
D/A the SWS digital data of rsWsD of υ′
Audio for still images is output after conversion and low-pass filtering.
You will be forced to do so. PΔ is the video signal of the output of play V
This will output the tightening of the characters. At this point,
Since the character code is not read out, it is bla\7.
The output images of these are output. Of course, d3
A stop code is recorded at a of this frame -C
, Play 17 deciphered the internal image, still image (1J student C)
There is. Here, SCT collects a data group specified from the outside.
Since this is an output command, audio will not be output unless specified externally.
The characters are also not output. Here, the second SWS from the outside
If you specify the second character data, a large capacity buffer will be created.
SWS digital data from specified memory address
is read out, D/A converted, and output through a low-pass filter.
Powered. Also character data and Daikan L1\Tsuno L' memory
Read from, store in character buffer and play
It is combined with the power video signal and supplied to the outside. In this case, the voice is ``Mother 21, and the text is ['M atl
+ar j is output respectively)j is performed. Next, another 8 tones and sentences
If you want to output a character, supply it to another code from the outside.
), you can enlarge short sentences, words, characters, etc. in advance.
Capacity buffer memory is used to store information related to
and any other digital content, including any audio or text.
Uj can be used to select and output data. Still image re
When transitioning from the raw state to the next operation, press brake A7.
From Kon=1n1~[]-ru (If you send the iT1 issue
good. Figure 31 shows (1) frame and (2) frame 1.
1. Timing check the processing of ihl+1 (17-1~
This is shown in . Next, we will explain C) movement A'1 in the block diagram of Fig. 32.
Zuru. Video and other signals are applied to the TV synchronization signal part 1 unit 1 human power
At the same time, the human power of the image processing unit 8 is also applied. T
V synchronization signal separator The 1-1°■ synchronization signal is
It is applied to the input of the timing signal generator 2. Taimin
In the signal generator, the system ')IJy') (7,1
6fvlHz) Color 1-1. Based on V synchronization signal
generates timing signals for each block in the decoder.
I'm avoiding it. In particular, the controller - roll code buffer memo
The timing signal fa (CW) temporarily stored in the relay 20 is
2311 to 261] of each field.
Ru. Also, control code buffer memory to system
A timing signal for reading the control code to the controller 7.
No. f3 (CR) is in the even field after 271-1.
This is the timing signal that occurs. :I2 (W) is large capacity
Loading digital data into the volume buffer memory 5 1
1) Data is sent to block C by the timing signal generated in
In the period of 27H to 260 +-1 if recorded
It is a light-year timing signal. J'+(R) is crowded■
Read data from buffer 1 memory 5 and issue at 11.1
The timing signal that is generated is mainly generated when still images II
occurs and is dependent on one non-bringing frequency of the voice. child
Here, if I2 (W) > fl (R) in terms of frequency, then
, for S WS l'-' sitaruata, the time axis
The decompression process will be performed. Each timing is controlled by control signals from the system norm controller 7.
and generates these various timing signals.
. Video signal output from TV synchronizer 1 (synchronization signal)
The brightness signal (what some people call it) is the threshold value.
It is applied to the human power of the field circuit 13. threshold hole
In a circuit, if the amplitude value is larger than an arbitrary level, then
If the digital signal is "1" or smaller, it is called "0".
After converting to a digital signal string, 8 pins 1~
Convert to parallel, control code barafun) Meshiri 2
Supply to 0 and large capacity buffer j7 memory 5 - Ruru 3, controller
To roll code buff number 7 is sys y-1
x controller to odd field 11;
Stores the control I call code of Rudo]-Ria Nou'
Tres again, even field if to even field 1
Obtain the address of the code and generate it from 1 timing signal generator 2
Cheating: Store F4 (CW) No. 45 'c' sequentially? :'t
j<. Storage of control 1~roll code is completed in even field.
Then, the error correction circuit 4 corrects the error using the 53 (CR) signal.
applied to the input of the system controller 7 after processing
. The system controller decodes the code and sends it to each processing section.
Change the number from 1 to 1. Manage the bias of digital data
In the case of code, change from American 4--code to binary data.
and set it in the data management register to start the next frame.
-C video processor 8 and audio switching switch prior to playback of the program.
control switch 66. The threshold circuit 13
The digital data supplied from the
It is applied to the input terminal of 5. This large capacity Bano) memory
In this case, the timing signal supplied from the timing signal generator is
No. J2 (W) and the access point I4 from the system controller.
The address signals are sequentially stored in step 111. Next, Daikanden
When data has been written to the buffer memory, the
'If full, f+ (R
) and the read address signal from the system controller -C
One person reading error correction circuit 3 from buffer memory
Supply to input. This l) Sun'J positive circuit performs correction processing.
After the bidi interleave, the system system till device
Therefore, in the case of digital data for SWS, one
Applied to the human power of the converter 9. 1) /A transformer C is j゛
After converting the digital signal to an analog signal,
through the router, and through the audio signal switch 1-6G.
, in the case of a 33-character i-parameter supplied to the outside, similarly
Controlled from the system controller, ) - Bow and helmet - C1 character bag.
Supplies f-ray\/7J to video processor through F65
J, which synthesizes the video signals and supplies them to the outside.
Make it. In addition, in the case of several types of sounds and characters
Reads the selection in advance and specifies that there is 'r.
Control] 1-Read the code one frame earlier and decode it.
The code specified by the external/JI I is supplied.
Unless otherwise specified, 8 units and 15 characters will not be output. from outside
specified]-1- or system control 2;
The stem controller (is) -1-1- is decoded and a large capacity battery is installed.
Specified SWS data and character data in I3 in 7 frames.
The data is recorded and the horn I response is recorded in a large capacity buffer.
・To the timing signal generator that is supplied to the
, f+(1'i:).
In addition to supplying the code to the timing generator, the D/A conversion
Supply a control signal to device 9 and also write a character buffer? Also control signal
output the specified sounds and characters.
ing. Next, if different voices and characters are supplied, the same processing C voice
and operates to cover the output of characters. digital data
If the data is compared with an external signal, error: J
+[Data input from outside is taken into the system controller]
I'll have to wait for power. In addition, in the case of normal videos, frequency multiplication, which is generally done
Due to superimposition, analog audio is superimposed and recorded on CD3.
In this case, the switch 66 is set to a3-C.
It shall be made so that it can be derived as a regenerated output.
are doing. ” - Conn l-1] of the b block on each side of the statement.
data to be processed by this control data.
inserted in the same frame as the digital f-riya image information.
If so, play this controller 1~roll data and play the data 1~
In order to identify the information, there is a drawback that high-speed processing is required. the
In order to achieve this, the processing circuit of the control module operates at high speed.
Hibome 1 - Circuit using Lancista (1 Mitsutakatsu)
Pring Logic or Schottshiki IC> is required,
It becomes difficult to miniaturize circuits and reduce power consumption. Therefore, digital data and
1~Roll)-data corresponding to the image information.
At least 1 frame for fli people rules such as Tal data etc.
Add +1p to 7) and change this control data.
Where to play, de"-do, etc. Jjlj IVJ I! fl.
It takes at least one frame worth of time.
It is. That is, as shown in timing chart A-1~ in FIG.
In Fig. 27, the example for bidet A and pine 1 is shown in Fig. 27.
A) frame block 1" button l)] control
] - Corrected during the image birth processing of the (Δ) frame,
Perform processing such as decoding (next < (R) frame
Data processing 1ri is executed according to this = 1 controller ni.
(Some 9゜Also, Control 1-Roll)
With the increase in information of Co-1 ~, 1 frame
The two fields that make up the system (odd and even fields)
Correspondence of 1 to 0 on the horizontal scanning line
Scrape and insert the code. Figure 33 shows the mode.
indicates Cd3, ■ is vertical 1til JIIJ signal section
, a, b, c and Q are the same as in the example of FIG.
The numbers 1 and 2 in each subscript are 1 and 2 across odd fields.
indicates an even field. An example of each number of scanning lines is the third
As shown in the figure. Buto 1 Tsuku b, Comte 1”
- For code, there are two fields J or 1 frame.
The system is configured so that interleaving and error correction are completed in the system.
In block C, each subblock (Fig.
J, where interleaving and 51 positive are completed in d5 (see)
It is being done. Block l) includes various control data.
Information important to the control of the C equipment can be manipulated using the computer.
From the correction 11i horn high error correction 1″1 is added.
For example, the one-word syndrome itJ' i [
, 2-word erase correction is performed like Rina. on the other hand
, about the digital data of block C U1. L, many
Even if a small error occurs that cannot be corrected, it may be replaced by an allophone or an undecipherable character.
There is no problem unless J]
No. 4111 Successful example (, [1 word syndrome lesson]
11-J to unite, to be united. Fig. 34 shows the error Wl' i in the conldrubuk]
This is a diagram for showing the block 1] and 1. L! recorded
There is a C. This block b is the above L horn, 1st floor like 1.
Field's 23 H~26+-1,2 Tweel 1~2
311.~2 (consisting of the combination t 81-1 of 31-1
J5, all (288 bar r1, but valid information
Yo, fil, yo ε30 high h -(-d lily, remaining
208 Pi 1 ~ is the approximate X, Y and
and 7.7J parity P, Q (・aru,, l
). The subscripts X, Y, and 7 of Q are 0∅Ω1: including its parity.
The subscript of the number ゛j′° is (U'
8 i+: There is C corresponding to the number of the first word of i. 19×13'I O', j: The word is
One tee
With b, 6 directions ahead flf + (1) l 'XPY loss
The month is 0. ) L k, QX Q
Parity Q y in the X direction to War 1 Y QZ. At the same time, Y
It also indicates 7-way parity. . P or Q's silk combination and addition-F (:A appears/J and others
The same applies to words. In addition, 1 word is 8 bits 1
~. Here, the word f! belongs to the YZ plane at the left end of the figure! YW
o, W, W2o, WIIO, W41. WGo, Wg+
, Pvo, Qyo, Pv+, Qy+ are the next 12 words.
C is used as a frame identification code for
Ru. First, for error detection, 1/3 horizontal scanning line (1/3
31-1'), the sign of (n, k) = (12, 10)
Configure and detect signals. This is 1]x,Q in Figure 34
This corresponds to error detection in the X direction using x. Next, error correction and
Then, the sign of (n, k)=<6゜4) is given to the 21st~th υ.
Configure and correct. This is the PY in the diagram. This corresponds to Yh direction error correction by QY. Furthermore, 21-1
(n, k) - (4, 2) for the 4 words of a3
The correction is performed by constructing the code of This is 1]l in the figure. This corresponds to error correction in the Z direction by Qz. In this example, all error detection and error correction are
(8 bits due to Reed-Solomon code on AGF(2)
This is done in word units, and the atomic element X is P (x)
=x8 +x 4-1-X 3+x 2-+-1 (D root
shall be. However, it is written as α-(OOO00010). Also, check matrix 1-1 is (n; code length), which is expressed using matrix -1- in units of 1 pill.
J and becomes . However, 1 is the identity matrix of 8 rows and 8 columns (-1 is J below,
8 rows and 8 columns? Take column j. Now, to know the location of the error and the details of the error, follow the steps below.
Let us consider the syndrome S defined as . Right S = [Sp So ] =I-I・[Wfl-1,W
ll-2゜...W2, P, Q]" In the above equation, information is set so that Sp = So = O is satisfied.
P and Q are recorded along with the word. Therefore, the frame
When recording the identification code in even frames, " o o
o o o o o o”, for odd frames
In this case, Pyo is '00111110'. QYO, Py+, parity t of QYI, even frame
In the case of “o o o o o o o o o”,
In the case of an odd number frame, it is “00111111”, and the frame
It can be used as a separate code for the thief. Such frame identification codes are shared between adjacent frame phases H.
, record it in block b and write it as J
3, there is a change in this frame identification = 1-code during playback.
If you try to detect nothing, it will be a moving image when it changes, and it will be useful.
When I wake up, I take a still picture.
0 screams. Therefore, for example, in the reproduction system shown in Fig. 26, the switching circuit
Output from 57]n1~roll-"
A video/still image detector that extracts the system identification code and identifies the system.
() and sends this detection output to the system controller 7.
Like Jru. A configuration example of this video/still image detector is shown in the third example.
It is shown in FIG. 5 and has the following configuration. Remove the 7th bit from the 3rd bit 1 of the frame identification code.
Noagu 1 to 350, which detects whether all are O.
Detect whether Gobete is 1 i) End gate 35
1. (00000) and (1111) by both goo 1-
When L1 is detected, the detection pulse becomes L1.
1111 with CK
To the Azzo and Taunkaran 1-control terminals of Ta 352, respectively.
India Noah 11 Jru and Goo 1~353°354, Cow
A-half flow with 16 or more points. To prevent underflow below O, the above
To prevent detection pulse counter input, set the counter to
Output 4 pitches hQA, Qe, Qc, Q. monitor and detect low levels when it reaches 16 or O.
A that generates a signal and closes -C goo 1~353.354
- Ba Angtulow preventer 355. The highest value of counter 352
- Read the L bit output and synchronize with the frame 1
2-bit shift 1 to register 356
And the two outputs of shift 1 to register 356 are used to create a video.
An executable that detects whether it is a still image or a still image and outputs the detection flag.
It consists of Crucive or Gate 357. Frame identification code among the [read] code
Since the code requires high-speed detection, the error h′J is correct.
Instead, a 12-word identification code is used to
The circuit shown in FIG. 35 is manually operated to improve reliability. input
identification] - is the 3rd to 7th bit [... is all O or 1
It is detected in 1~350.351. Zube
If it is O, move up 1 to 352.
, if it is 1, the down call is 1 or more. At this time the game
The initial value of the bit is set to 8, and the most significant bit of the 4 bits is set to 8.
1 -(J> +jc, frame identification w -Fk(
OO000000〉, that is, repeat the even numbered frames
11-When in the middle, goo 1~4 pits 1~output maximum''-
IzulpiI-Q +) is always 1, and (00111
110) [1,'J41, that is, during odd frame playback
, QD will be ○ for one person. . As a result, even and odd numbered beef cows are 94I.
It is possible to detect one bit. Here, the frame identification number 21-word (ma1war1~saei,
If you look at 'G, you can detect rivers in videos and still images.
However, the drop fl 1 to 1 etc. J mm this two
12 words are recorded so that it can be detected even if it is missing.
There is. Therefore, the counter 352 has the same frame identification code.
It is possible to repeat Do many times from 1 to 1. It is possible to produce bamboo 1°. Therefore,
The output of the counter is A-Ha Nonontanoro 1L unit 35
If the input is input to 5 and the output is 15 or 0, goo 1~
Assume that the input stage of ANDGOO L-3El 3-354 is closed.
This is why I am trying to stop Karan 1~. The maximum value of the output of this counter 352 is -J-6t hit 1 to Q1.
．． ) to 2-bit shift 1 to register 356, frame
It is synchronized and input serially using the same clock. At this time
Motion I! ! ! For I playback, input to shift 1~register.
In this case, the counter output is 4≧, so these are 1-3.
57, the output will be 1-1. On the other hand, stationary
For video playback, the output of the Schiffmil register is L and the video is played back.
, it becomes possible to distinguish between the playback states of still images. This detection output is sent from the system controller 7 to each part of the system.
At the same time, if necessary, the
External parts such as a combi coater can be sent to the vessel.
Ru. Control 1 - Other measures to cope with the increase in the roll cord container.
As an example, the control 1-1-ruco corresponding to one frame is
There is a method in which the code is divided into multiple frames and inserted and recorded.
Conceivable. The schematic block of the req system in this case is the 36th
As shown in the figure, from the videoph A-Pine 1-signal to V,
l-1 sink, same data! I] Signal, control
Code, sws data, etc. for everyone! II separator LV,
1 sync and data synchronization signals to each part of the system.
Timing signal generator 2, SW that generates timing signals
Ichifuri Shitalsho Voice Center converts S data into analog signals.
Science: ÷s69, memory of control data
・Meshiri 20, Control 1-Roll data 4 (Su5J I
I, jl +, ■ stopper 4, complete control data
Detector end detector 68, main end detector 20
A decoder 67 for decoding the data,
Your command, great technique U (personal feelings like a computer etc.?ff
Receives the VDP status signal () Controls each part
The system controller 7, which generates and sends the Jt signal,
A (screen processing that performs various processes on i-j S'r)
8 and S W S nonita output and general audio
A-dio signal processor 7 that performs switching between r-A-inshishi
Consisting of o. Now, the 1-1-1-roll date corresponding to a certain frame
Divide the data into multiple frames of blocks and record them.
Then, add this -III Herol to the next phrase.
61. Identification signal indicating whether the data is continuous or not. li person
45 <. Next, I will explain the operation. Figure d5-(,jiIA)
The A-man 1 signal input is applied to signal separator 1 and the vertical
Synchronization signal, horizontal synchronization time tag, f-t1i-it period a, 1
control program, digital audio data
data is separated. Separated vertical sync signal, horizontal sync signal
The signal and data synchronization signal are applied to the timing signal generator 2.
The timing signal is generated without being sent to each part. Also,
The digital audio data is stored in a buffer in the digital audio processor 69.
After being written to the buffer memory and performing error correction, the
Axis expansion readout, analog audio signal via D/A converter
Toshi C is taken out. Control data is buffer 1
J)8 is loaded into the memory 20, and the error corrector 4 outputs
Make corrections 1. At this point, the data 1nd detector 68
Whether the control data is complete or continues to the next room
Detects the identification signal. ”N1~Roll data is next
When consecutive frames, the copy in the Balanoa memory 20 is
The control data is not sent to the decoder 67 and is kept as is.
have Also, when the roll data is completed,
, D'-Y 67 is the computer)-1 in the buffer memory 20.
Rub! ”gram and decodes it. system control
The device 7 receives control commands from the decoder, information from the input device,
Receive player status Nio()c1 timing signal
Generator, digital 8j-F' processing: (in, screen processor,
audio signal processor, and
Sends out various control signals. Screen processor 8 is video A
- Matte signal human power; tJ L 7: , digital audio
j-1 ng in the evening part (nrepi 1ijlIi/+
) or superimpose letters and shapes.
Impose and output video signal 3, γ11
Signal f! l! The device 70 reproduces the digital sound iL 7'-ta.
Switch between key & angle signals and voice input. Play
l control i: number is player's] control person number 9;1:
Applied to the child, normal playback, slow, static iL, room monthly
-% Cp control. Next, the video of +11 (f'j f'i i) is transferred to the recording medium.
In order to record I a) and SWS,
It would be possible to diversify so-called HideA software. child
In the case of , for example, each frame is sent to AAA
WS Which identification code should be recorded in advance?
When converting, this identification code is read and determined, and the endogenous operation is performed.
A conceivable method is h-method, which switches depending on the situation. In the case of a C-type 1-le video, use a general BifA disc.
As it is being done, the voice [Yoana]
2.1M+-12 (spray: AIJI is an additional 2°8
MHz audio signal is modulated by Ffvl and video
A information (this video signal is also FM) and frequency
Multiplex and record. For still images, digital
Insert the converted SWS data into block C and time-sharing J
Multiplex and record. Figure 37 shows the contents of the control code in such a case.
-4 bits, the top 4 pins of the 8-bit configuration are output
It is a control code, and the top 4 bits 1-1 are manual control codes.
be. The output control code distinguishes between spray A and monaural.
The input control]-do is monaural.
Next, change the SWS data) or select it for analog sound.
Select cbl or cl+2 or further [Mamiko]
It is Jrurano who decides whether the number is 1 or not, and the logic "1" is given.
Select, "o" indicates non-selection. still
, X is a pin that is not related to control, and in this example
This is what is generally considered to be ``0''. Furthermore, stereo
In this case, the audio input is 2c11 by VDP)
-Figure 11 Raw output (Frequency multiplexed recording 11)
(output) is selected, and the priority gourd is Usufu (yyl
i becomes high and J5, logic ``1'' comes to spray A
1゜ which is made so that it has no relation to other humans 1.
Figure 38 is 11199 diagram of 7IJ<+- yarn in such a case.
(Yes, controller 1-roll coder °' computer 6
Temporarily store the &F11 selection code (Figure 37).
6-bit latch 71 for
and does not drive audio selection relays RY1 to RY6.
In addition, the roll code of Dorotsubuara 1~etc.C''n1~ has been corrected.
To prevent malfunctions, etc., if incorrect data is read without
The protection circuit 72 that covers the operation and the output of this circuit 72
Controlled by ΔnA; t F'U selection relay
RY1・～1、Y6 3゜Figure 39 is a con.
Trolney 1-1 ~ Relay 1 < Y 1 ~ RY 6
This is a diagram showing the operational relationship, and there is a logical 1 in monaural.
The same Hatake parameter j from the R output is the lower 4 bits (3rd
The blind 7ffj source specified in Figure 7) is output.
Ru. When a logic 1 appears on chl, 1-Ch output of VD I)
When the power becomes logic 1 in C1)2, the Rch output of V D P
The force is output individually, and generally different from the video.
Insert the audio of the content and select according to the user's preference 1)
Used when making a change. When SWS becomes logic 1,
Is the time axis compressed SWS data subjected to time axis expansion processing?
The signal is then D/A converted and output as analog audio. Ma
T-mute theory II! When 1 is set, there is no audio output.
It will be done in such a way. FIG. 40 is a diagram of an example of the protection circuit shown in FIG. 38,
C using 6 bits 1 to 1 excluding the 2 bits indicated by X in Figure 37.
It is composed of an inverter and AND GO 1~. FIG. 41 is a diagram showing video formats 1 to 1 of this example.
, the SWS data is inserted into the entire block C.
Therefore, the audio is assumed to be mui-. Therefore the video
While playing back, sequentially store the SWS data to buffer 7 and 7 and 5.
I'll pay it and go. Note that the =1-do in this period is 11. period
When it reaches B, V l) P (playing 3L still images
However, at this time, the SWS data stored in memory 5
Taka11. The r axis is expanded and read from the memory (Nre1,
Output (, - is the analog high of this SWS data)
X+ is output. The code t during this period is L18. +y11iiI When it becomes G, 33WS data is stored in memory.
While storing the video 41j 'J, the sound at this time is
The voice is Chl, cl+2's 1) μ4 is like IIJ. The code at this time is 80 and 4τ. First period
Then, VII) P takes a picture of Pj,
Read SWS data from memory and extend axis between II;'J
During this time, "-1~" is output as a voice.
It is 18. Next, following the formula for digital data,
Described in 1. First of all, referring to Figure 42, the diagram is drawn in the conventional manner.
This is a block diagram of the data separation circuit.
A pedestal clamper that sets the stall level to a constant voltage of 11.
422 is the threshold 11 (threshold hole 1) VD.
Compare the digital data and add a wave to the jr digital signal of C1,0.
Shaping Halator, /123 detects V sync
/I 2-1 is a PL that manually operates the V sink.
L (phase locked loop) circuit, 425 is H section
Data synchronization (DS) inserted at the front of the data
Take out the pulse t DS detector, 426 is the DS pulse
and the clock from PLL424.
The reset circuit that generates the reference signal for DCK
427 is the clock output from the reset circuit 426.
delay so that the rising edge of the data is at the center of each pit section.
The delay circuit for delay and 428 is the delay circuit 427
There is a 1:FC that reads data based on the DCK. Here, the digital signal in section 11-1 shown in FIG.
Partial waveform of digital data including DS pulse of signal waveform
An enlarged view is shown in FIG. 43(a), and this signal (a
) is pedestally clamped by clamper 421, and the controller
In the parator 422 a threshold 1iOV. As a result, a digital signal of 1.0 is generated as shown in Figure 43.
The waveform is shaped into On the other hand, based on the V sink detected by J3 in the detector 423,
P L L /l 2 A operates as a standard, and the data
Hits l - Ray 1 - Frequency 4 (7X glue lit?
The output is as shown in figure td+. Also, DS pulse detection 2
ii 425 as shown in Figure (C), and
I+ to reset 1 as a reset pulse to circuit 42G terminal 1)
'j 4ノ(Bakesake(, Kuro from P L L 424
td〉 standing 1-ri (1 point A point)
and the same frequency clock as j'-evening pick-rate
The clock (G) is input to the delay circuit/127 as shown in figure (0).
Standing at the center of each pitch 1 to section - [Rigakuru 4),')
1, which delays the DCK and shows the occurrence as shown in ([).
One OK is the system clock and F r”
/l 28 clock is used for this DCK.
U1's arc is read out and output and J, sea urchin l
, I: □v C3, In the circuit system shown in Figure 42, ]n
Slice level of palator 422 (1 to % Ifi level
Level V 1) For the amplitude fluctuation of human chi 1°
Follow! J thing <'c < constant and /f. ”,
, the data slice is positive (1), or the data slice is
Data reading is positive 1IIr and 41. , (lgo, DCK
The relet point to set the reference clock (0) of
To be exact, [-)S pulse (C) falling fish catch/\ki
However, in reality, a clock pulse occurs at the rising point of clock pulse (d).
Lock (e) is relet. Zonotori 1” ivy
(+3+ is the maximum clock pulse (one cycle of the mountain or the phase
D that caused a shift and finally matched the data phase exactly
You can't get a CK. In addition, in this way, the falling edge of the DS pulse is determined by the phase base Q of DCK.
For example, to read the data of 111 section as +4,
The DS pulse shown in Figure 11 is detected by dropout, etc.
If it cannot be detected or it is detected in the wrong position,
In section 11-1, accurate resetting is not performed and data cannot be read.
Mistakes occur. Furthermore, to generate DCK using these 6 equations,
Instead, it constantly monitors and follows data reversals.D
A method for generating CK, for example, a method using PLL.
This solves the above-mentioned drawbacks to some extent, but not completely. Therefore, at the front of the field (pull block a)
The field sync data shown in Figure 10 is inserted.
Using this data, so-called ATC (automatic threshold value) is applied.
The above drawbacks are solved by avoiding the configuration of control) circuits.
A concrete example of the block is shown in FIG.
Ru. Video Fun - Matsu 1 ~ Hakugo is Bestal Crumba 421
When the pedestal is clamped, the same IK is violated, this club
The pedestal level Vl) is output from the amplifier 421.
It looks like this. The signal to Before A-No A-V Tsu 1 is
Since other image signals of digital signals exist,
, Only Digital Noburo is J-j in Goo 1~Circuit 429
It's going to be 1 ~. The next small circuit 430
The positive peak of the digital signal is held and the previous bedesk
The level V1) and the I\- field output are connected to the resistor R+,
The voltage dividing circuit C of R2 is divided into equal parts, and this is set as the threshold level.
Became one of 122 people. This threshold level and the output of the clamper 421 are compared in level.
and waveform shaping. Of this ■1 inverter output,
Only digital data is gated in circuit 1~circuit 431.
Then, the inversion of this gate output +1 rl C rises.
Luz extracts clock 'l', /l 32 'r-Ushinari
be done. And the same as the rise of this pulse 1111 L
Same frequency C and data as j'-Evening Pit Ray 1-
A DCK with a rising edge coming from the center of each pitch 1 to section of the
Generated by PLI-circuit 434. Clone this DCK
The output of the comparator 422 is used as the data input.
Digital data synchronized with DCK by FF428
data is read. In the peak bold circuit 430, the data dot
Do not follow sudden amplitude changes such as noise, noise, etc.
The time constant is selected to be large. In this way, the field inserted at the top of the field
Peak Bold and I) 1m according to RudoSync data
The lock is maintained for a period of time so that the image continues
Even if digital data arrives later, the peak hole will occur immediately.
This enables stable data storage and PLL lock.
It is possible to separate. In addition, PLL lock occurs in the middle of the field.
Even if the data is removed, the data immediately before the digital data is
It becomes possible to pull into lock by the DS signal. If the image signal period is long to some extent, PLL lock
There is a danger that the
There is also a clock synchronization signal at the beginning of each 1-1 light interval to which the image signal belongs.
Enter several pulses synchronized with the number Hi l + li J: Sea urchin
If you arrive at Shi-C, there will be an example of Pl-1-Ro in the middle of the field.
Even if the lock comes off, the next glue II Luck will cause I)
LL can be locked by locking 1°.In addition, in the above example,
The method uses PLL434, but the method shown in Fig. 42 is
6 types (referred to as the rillette method) may be used.
It is. ! J four pieces, each of 431 to 434 in Figure 44
Blocks 423 to 427 in Figure 42
By the way, as shown in Figure 4, the initial data should be changed to
Although the clock run-in signal and DS signal are inserted,
Figure 42 Noriref 1 Le b type detects part of this signal.
Since this signal is used to reset 1-, almost the entire signal is
``Do 1'' Tsubu > Know 1~ Do 41 J and perform good movements.
Unodedo 1] Tsubuau 1 to 9 = I Stronger than L
Become. In addition, in the method 1~, the picture is as shown in Figure 45.
When the clock is not inserted before the image signal, the image signal
Since Harihira 1 ~ will not be held during the period, DCK data
The phase shift relative to the data is folded back into digital data
During the January conjunction, the tarot signal will drop out.
If it is lost in the 11th section, you will not be able to get the section reset and it will fail.
Accurate data reading is performed, but as shown in Figure 45, each 11
The above inaccuracy occurs because the clock signal is inserted at the beginning of
will disappear. However, this reset method
It is unavoidable that a deviation of one period will occur. The above explanation refers to video discs as recording media.
However, it is also possible to use a videotape, etc.
SWS audio as formatted digital data
In addition to data, text information and stress in the mechanical field
information, medical information such as electrocardiograms in the medical field, and
can also include physical information such as temperature information.
Ru. This digital data is a straight line or a broken line PCM.
Various types of formulas, adaptive differential PCM (ADPCM), ADM, etc.
You can use the Shungetsu method. In addition, video
-The matte signal format is other than MTSC, such as PAL or
It is also possible to refer to it as the SECAM method. Also, the number of lines per building in each block a to Q is limited to the example in Figure 3.
It is clear that independent transformation is possible without being
be. As mentioned above, the S W S 11j cattle clothing [1] according to the present invention
γI is 11.1-axis compressed audio digital data.
Since it has the ability to read from a video signal, right? +
I!・When digital data other than data is inserted
'c-L), the data is faithful to D/A conversion@device input.
Indeed, IIj will be born. Therefore, the video format
Since the product data has been changed to the control data of the mat signal.
Enter a code in advance to identify whether it is external digital data.
Record it, identify this code on the playback device, and use the D/
A relatively simple device for switching the human power of the A conversion device.
(= J is added to the playback of mixed voice data and non-audio
It is possible to have both functions of the data. child
For recording digital data on the video recorder A)'
Produce a video disc by
g (9) and can be a recording medium of high r”
+J By recording still images on the same disk and playing them back,
This shows that a wide range of functions can be achieved with a single playback device.
ing. (Table-1) (Table-2)

[Brief explanation of drawings]

Figure 1 shows 10 fields of the d3*J field screen according to the present invention
Figure 2 (Mavide A' 7 A)
- An enlarged view of the matte signal V-branch 4-ngui. Figures 5 to 7 show examples of data insertion. Figures 4 and 8 show examples of data insertion, respectively. Figure 9 is a block diagram showing an example of the j[-1 ts] of the jJ3'I- system. An example is shown in Figure 11 (Mazo).
The figure shows another example of the playback system block.
FIG.
Figure 5 is a diagram showing another example of the playback system block III, No. 16.
The figure shows the timing diagram of the 10 wheels in Figure 15 ('l), Figure 17 (shows still another example of the 10 wheels of the Mailj/J- system, and Figure 41163 shows the timing chart showing the movement of the 10 wheels ('l). ” /1 Figure 19 is a diagram showing an example of the software 1 ~, Figure 19 is a diagram showing another example of the playback system, and Figure 20 is a diagram showing another example of the video software 1. Figure 21 is a diagram showing another example of the regeneration system.
Fig. 2 shows another example of control data, Fig. 23 shows yet another example of the 10 playback system, Fig. 24 shows another example of video sono 1, and Fig. 25 shows another example of the playback system. The figure shows the relationship between block C and the data "identification code," FIG. 26 shows yet another example of a reproduction system, FIG. 27 shows yet another example of video software, and The figure shows the contents of digital data, Figures 29 and 30 show examples of control data, and Figure 31 shows the operation timing of the playback system for the video software in Figure 27.
Figure 2 shows another example of playback system blocks, and Figure 33 shows the video format signal of control 1-roll data (
), Figure 34 is a diagram explaining the control data error correction method, Figure 35 is an example of a control data detector, and Figure 36 is a reproduction example. Fig. 37 is a diagram showing another example of the system block, and Fig. 37 is a diagram showing an example of control data, ff! Figure 38 shows another example of the playback system block; Figure 39 shows the operational relationship between the control data in Figure 317 and the heel switching relay in Figure 38; Figure 1 and Figure 110; Figure 1 shows a specific example of the protection circuit in Figure 38, Figure 4'1 shows an example of Hashi-J-A software,
Fig. 7'12 LJ is a block diagram of a conventional example of the footer separation section, Fig. 43 is a waveform diagram of each part explaining the /''1111 check of Fig. 42, and Fig. 114 is a diagram of the data front section used in the present invention. The block diagram, FIG. 45, is a diagram showing an example of the 1 1-1 (ij +3 waveform) used in the block of FIG. ...Taiminquim 2J beef praise ÷ 3.4...
...Error correction circuit 5...Time axis expansion method 6...Control]-1-T'-ri7...
...System system υII mi8...Screen processor 9...D/△ converter 10...Play A7 controller Applicant Pi A Nia (λ, formula company agent Person Patent attorney Motohiko Fujitoshi (1 other person)

Claims (2)

[Claims] (1) A recording method for a signal to a video format 1, which is characterized in that not only audio digital data is inserted into the video format signal, but also digital data other than the audio digital data is also inserted. (2) The recording method according to claim 1, further comprising recording an identification signal that distinguishes the audio digital data from other digital data.