JPS60689A - Mos storage device - Google Patents

Abstract

PURPOSE:To attain high speed operation by completing the selecting operation of a word line and a data line of a memory array immediately when the read of a memory cell is finished and conducting the pre-charge for the next operating cycle. CONSTITUTION:When an address signal Ai is changed, a detecting pulse phic(phir) is formed and a timing generating circuit TG forms a series of timing signals. A pre-charge pulse phipar goes to a low level in this case and its operation is finished. Then a word line selecting signal phix goes to a high level and a word line is selected. A sense amplifier SA amplifies read storage information. A memory on the verge of losing its stored information through said read is recovered by receiving as it is a level amplified by the amplifier SA in the timing applying a bootstrap voltage to the potential of the word line. Then a selecting signal phiy goes to a high level and a read signal is amplified by an amplifier MA. After the start of amplification, the signals phix and phiy go to a low level and the data line of the memory array is brought into a high impedance state. Further, complementary data line pairs are short-circuited so as to start its pre-charge operation.

Description

[Detailed Description of the Invention] [Technical Field] The present invention relates to a MOS (i-electromagnetic semiconductor) 1q device, which detects, for example, the change timing of an address signal and based on the detected output. 'ζ relates to a technique effective for an internally synchronized MO3 storage device that controls the timing of its internal operations.

[Background technology]

The inventors of the present application detect the change timing of the address signal, use it as a detection output, and use an internal synchronous MO3O3 that performs internal operation timing;
I7J was issued to the storage device. This kind of internal synchronous M
In the O3 storage device, the change timing (edge) of the address signal is detected to determine the operation timing of all "C". In particular, the -F edge is detected and the internal circuit is precharged by this detection output. However, the disadvantage is that the access time is delayed by this precharge time.

[Purpose of the invention]

The purpose of this invention is to provide an internally synchronized M
The purpose of the present invention is to provide an O3 storage device.

The above-mentioned objects and novel features of this invention are as follows:
It will become clear from the description of this specification and the accompanying drawings.

[Summary of the invention]

A brief overview of typical inventions disclosed in this application is as follows.

That is, as soon as the reading of the memory cell is completed, the selection operation of the word line and data line of the memory array is immediately finished, and the precharging for the next operation cycle is performed, thereby achieving high-speed operation. It is.

〔Example〕

FIG. 1 shows a block diagram of one embodiment of the invention.

In the figure, each circuit block surrounded by a dotted line is formed on a IIva semiconductor substrate such as silicon by a known semiconductor integrated circuit manufacturing technique, and is formed on a IIva semiconductor substrate such as silicon.
Terminals DO-D7. AO~814° Power is supplied from an appropriate external power supply device.

The circuit indicated by the circuit symbol M-ARY is a memory array, which includes a storage capacitor and an address selection MO3F.
1MO3 type memory cells made up of ET are arranged in a matrix. In this embodiment, although not particularly limited, 1. The memory cells described above are arranged in a so-called two-intersection system in which their input/output nodes are coupled to either one of a pair of parallel complementary data lines D.

The circuit symbol Pct is the data Azusa precharge circuit, which receives the precharge pulse φpcr &J
Then, the complementary data line 1] is connected to a MOSF that precharges each data line D to Vcc/2.
Composed of ET.

The circuit symbol SA indicates a sense amplifier, which is composed of a CMO3 (complementary MO3) latch circuit in which a power switch MO3FET is provided for the m source voltage VCC and the circuit ground potential Vss, although this is not particularly limited. and its pair of input/output nodes are connected to the complementary data line D
is combined with

The timing pulse φpa is the power switch MO3
This is for controlling the FET. power switch M
The O3FET is turned off just before precharging, and the complementary data line is connected to Vc (, Vss) with D floating.
Hold the level. And the above precharge MO3F
When ET is turned on, the complementary data line D is precharged.

A column switch, designated by the circuit symbol C-SW, couples a selected complementary data line to a common complementary data line according to a column selection signal.

The circuit symbol R-ADH is a row address buffer, which receives an external address signal from an external terminal AO-A8 and inputs internal complementary address selection aυ to a8 .
aυ〜a 11 kM31u 'Tru*7. In the explanation and drawings that follow &8s, the internal complementary address signal in the - column, for example aQ, 0, will not be expressed as the internal complementary address signal 10. Shitakashi-C1' Two internal complementary address signals aO~aQ, aQ~^8 are internal complementary address signals lO
~18 and not expressed.

The circuit symbol C-ADB is a column address buffer, which receives external address signals from external terminals A9 to A14 and selects internal complementary addresses A9 to A14.
a14. Form a9 to a14. In addition, in accordance with the way of expressing the internal complementary address signals described above, in the drawings and the following explanation, "two-legged internal complementary address signals a9 to a
14. a9~〒14 as internal complementary address signals 19~1''
It is expressed as 4.

The circuit symbol R-D CR is an 11 address decoder, which is a multiplexer MP described later.
In response to internal complementary address signal 0-e8 via X,
Forms the M-ARY word line selection signal. This sword if 3H saw (rt number) is transmitted to M-ARY in synchronization with the word lli! selection timing signal φX.

The circuit symbol C-DCR is a column address decoder and internal complementary address signal! 9~Lord 14
In response to this, an M-ARY data line selection signal is formed.

This data line selection signal is transmitted to column switch C-5W in synchronization with data line selection timing signal φy.

The circuit symbol PC2 indicates a precharge circuit for the common complementary data line, and is a MOS similar to the above-mentioned precharge circuit PCI that short-circuits the common complementary data line in response to a precharge pulse φpcd, although it is not particularly limited. F
Grooved by ET.

The circuit symbol MA indicates a main amplifier, which has the same circuit configuration as the sense amplifier SA described above. The timing pulse φma is the power switch MO3F
This is for controlling ET.

The circuit symbol DOB is data output cover 2.
The read data from the main amplifier MA is sent to the external terminal DO- by the read timing signal φOp.
Each is sent to D7. Note that during writing, this data output cover sofa DOB is rendered inactive (output cover/f impedance) by its low level.

The circuit symbol DIB is a data driver cover sofa, which transmits write data from external terminals D0 to D7 to a common complementary data line by means of a timing output φin. Incidentally, when issuing the command, this data buffer DIB is rendered inactive due to its low level.

The various timing pulse numbers mentioned above are formed by the following circuit blocks.

What is indicated by the V5 symbol REG is an edge trigger circuit that receives the address signals aO to A8 (or D() to D8) and detects the rising edge or the rising edge of the address signal, although it is not particularly limited. .

Although not particularly limited, what is indicated by the circuit symbol CEG is the address signal yi+a9 to a14 (or i9 to T1
4) is an edge trigger circuit that detects a rising edge or a rising F edge, and the edge trigger circuit J1 is not particularly 1ffll IW, but
The groove is formed by exclusive OR circuits receiving address signals aO to a8 and their delayed signals, respectively, and an OR circuit receiving output signals of these exclusive OR circuits.

That is, an exclusive circuit for receiving an address signal and a delayed signal of that address signal is provided for each address signal. In this case, nine exclusive OR circuits are provided, and the output signals of these nine exclusive OR circuits are input to the OR circuit. This edge trigger circuit REG
When any one of the address signals aO to a8 changes, an edge detection pulse φ synchronized with the change timing is generated.
!・Form.

The edge trigger circuit CEG has a groove bottom similar to that of the edge trigger circuit REG. That is, the groove is formed by exclusive OR circuits that receive address signals a9 to a14 and their delayed signals, respectively, and an OR circuit that receives output signals from these exclusive OR circuits. This edge trigger circuit CEG is the edge trigger circuit R mentioned above.
Similarly to EG, when any one of the address signals a9 to a14 changes, an edge detection pulse φC is generated in synchronization with the timing of the change.

The circuit symbol TG is a timing generation circuit, which forms the main timing signals etc. shown as the representative above. This timing generation circuit receives edge detection pulses φr, φCo) and a write enable signal WT■ supplied from the first terminal.

In response to the chip selection signal C3, a series of evening and timing pulses are formed.

The circuit symbol MPX is a multiplexer, which will be described later.
According to control No. 16 φref from P and F, write in -A I
10~
selectively informs the decoder R-DCR of item 1.

The circuit symbol Vbb-G indicates the substrate bias voltage generation [ilJ F'8.

The circuit symbol 11EF is an automatic refresh circuit, which includes a fresh address counter, a timer, etc., and receives a refresh signal RE from an external sentinel.
It is activated by setting SH to low level.

That is, when the refresh signal RESH is set to a low level while the chip selection signal C3 is at a high level, the automatic refresh circuit REF switches the multiplexer MPX by the control signal φref and transfers the internal address signal from the built-in refresh address counter to the row decoder R-. This is transmitted to the DCR to perform a refresh operation (auto refresh) by selecting one word line M. Further, when the refresh signal RESH is kept at a low level, a timer is activated, and the refresh address counter is incremented at regular intervals, and a continuous refresh operation (self-refresh) is performed during this period.

FIG. 2 shows a circuit diagram of a specific embodiment of the main circuits shown in FIG. 1 above. In the following explanation,
Unless otherwise specified, the MOSFET is an n-channel MOSFET.

In the memory array M-ΔRY, a pair of rows is shown as a representative.
As shown in the figure, the input/output nodes of each of the plurality of memory cells having the MO3 configuration Lr are distributed and coupled with a predetermined regularity.

The precharge circuit Pct is MO3 shown as a representative.
Complementary data line 1), like FE u'I''Ql4.

(2) Consisting of a switch MO3FE'rQ14 installed between.

The sense amplifier SA is composed of an 0MO8 (complementary MO3) latch circuit consisting of representative p-channel MOSFETs Q7, Q9 and T1-channel MOSFETs Q6, QB. , the input/output nodes of -ri1 are connected to -tZ-complementary kwata1), I). In addition, the launch circuit may include, but is not limited to, a parallel p-channel M
Supply voltage V through OS Fg''Ql 2,0.13
C, C is supplied, n-channel MO3FE in parallel form
The ground voltage Vss of the circuit is supplied through TQIO and Qll. These power switches MO3FETQIO,
Qll and MO3FETQI 2. Ql 3 is commonly used for sense amplifiers SΔ provided in other similar rows.

Complementary timing pulses φpal and φpal that activate the sense amplifier SA are applied to the gates of the MOSFETQ-10 and Q12, and the MO3FET
The above timing pulse φ is applied to the gates of Qll and Ql3.
A complementary timing pulse φpa2 + φpa2 delayed from pal and φpal is applied. The reason for this is that when the sense amplifier SΔ is operated with a minute read voltage from the memory cell, a drop in the level of the data line is prevented by current limiting using MO3FETs QIO and Ql2 having relatively small conductance.

Then, the amplification operation in SA increases the potential difference between the complementary data lines (after that, the MO3FETs QI 1 and Ql 3 with relatively large conductance are turned on to speed up the amplification operation. In this way, in two stages By causing the sense amplifier S to increase +1?il!ti!+ in the minute DJ, high-speed reading can be performed while preventing the complementary data from falling on the burner level side.

The row decoder R-D CR has one circuit (sword t
! For example, r1 channel MO3Fl which receives address signals a2 to a6 is shown as a representative.
'rQ32~Q36 and p channel'/channel MO8FET
A word line j Tatsumizawa signal of 1 x 4 trees is formed by a NANI (NAND) circuit using a cMOS circuit composed of C>31 to Q41.

The output of this NANI) circuit is inverted by the CMOS-inverter IVl, and the output y I-MO3FE'l'C12
8 to Q31, and is transmitted to the gates of MO3FET'Q24 to Q27.

In addition, four word pure selection timing signals φx00 to φxll formed by combining the complementary address signal aQ, the decode signal formed by the main l, and the timing pulse φX are sent via the MOS IT ETQ24 to Q27. transmitted to each word line. Furthermore, MO3FETQ20 to Q23 are provided between each word line and the ground potential, and by applying the output of the NAND circuit to the gate thereof, the word line is fixed at the ground potential when not selected. be.

The above word line has a reset MOS FET.
Ql to Q4 are provided, and a reset pulse φp
- These MOS FET Q I~Q
4 is turned on, the selected word line is reset to the ground level.

Column switch C-5W is M shown as a representative.
O3FETQ42. Like Q43, complementary data line,
D and common complementary data lines CD, CD are selectively coupled. M OS F E TQ42, (143
A selection signal from the column decoder C-DCR is supplied to the gate of the column decoder C-DCR.

Between the common complementary data lines CD and CD, 14 precharge circuits PC2 similar to the above are formed.
S FET Q 44 is provided.

This common complementary data line CD, C1) is connected to a main amplifier MA having a similar circuit to the sense amplifier SA.
A pair of input and output nodes are connected.

The precharging operation of the memory array in this embodiment is to short-circuit a pair of complementary data lines, a common complementary data line, to an intermediate level of about Vcc/2, so the data line is changed from 0 volts to Compared to those that charge up to the Vcc level, the amount of level change is small,
Even if the gate voltage of the precharge MO5FET is set to a normal logic level (Vcc), it can be turned on in a sufficiently non-saturated state, so the precharge operation can be performed at high speed and with low power consumption. .

Then, as mentioned above, set the precharge level to approximately Vcc.
/2, so when reading the memory cell, ζ is also the same as the memory cell switch MO5F.
Even if an appropriately cool logic level (Vcc) is used as the ET gate voltage (word line selection operation), it can be turned on in a sufficiently unsaturated state, so conventional dynamic RAM
It becomes possible to read out the entire charge of the information storage capacitor without using a bootstrap voltage as in the case of FIG. Also,
Since the read reference voltage uses the precharge level of one of the data lines in which no memory cell is selected, a dummy cell forming the read reference voltage may or may not be present. Although the block diagram of FIG. 1 shows a ×8 bit configuration, this embodiment shows a memory array for one bit of the configuration.

The automatic refresh circuit REF is composed of an address counter CON "I" which forms a refresh address signal and a timer circuit TM, although this is not particularly limited.

This timer circuit TM is activated by setting the glue refresh control signal RESH from an external terminal to a low level. That is, when the refresh control signal RESH is set to a low level while the chip selection signal C8 is at a high level, the switching signal φr of the multiplexer MPX
ef is output, the multiplexer MPX is switched to the address counter C0NT side, and the internal complementary address No. 14 aO" formed by this address counter coNT is output.
-a, 8 are transmitted to the address decoder R-DCR to perform a refresh operation (auto-refresh) by a single word line selection operation.

Since the address counter C0NT is incremented each time the refresh control signal RIE S II is input,
By repeating the above operation for the number of word lines, all memory cells can be refreshed. Also,"
1 Fresh market Rifi! Tl1r'i issue RESII
If it continues to be at a low level, the evening/timer circuit will operate and emit a pulse at regular intervals, causing the 71 pulse counter C0NT to advance and perform a continuous refresh operation during this time.) .

Despite using such a refresh operation, it is possible to treat it from the outside in the same way as a static type RAM, even though it uses memory cells of the same type.

That is, it can be used as a pseudo-static RAM.

FIG. 3 shows a timing diagram for explaining the operation of this embodiment circuit.

When any address signal Ai changes, the edge trigger circuit CEG (REG) generates a detection pulse φC.
(φr) is formed. This pulse φC (φr) activates the timing generation circuit TG to form the following series of timing signals. At this time, as will be described later, the precharge pulse φpar, which has already been at a high level, becomes a low level, and the precharge operation ends.

Next, the word line selection timing signal φX rises to a high level, and a word line selection operation is performed.

Thereafter, the timing pulse φpal+φpa2 that puts the sense amplifier 5A into operation becomes high level, and the stored information of the memory cell read out by the word line selection operation is amplified. A memory cell whose stored information is about to be lost due to reading of stored information to the data line is supplied with the level amplified by the sense amplifier SA at the timing when the bootstrap voltage is supplied to the potential of the word line. Recover.

Next, the data line selection timing signal φy rises to a high level, and the pair of data lines and the common data line are held at 1:i* by the column switch circuit VRC; SW. Then, this common data was conveyed to Cotton.17. The verse number f1 is a nof'unf "MA, &τj-+)°otj(
aj will be looked at. In this example, this main amplifier
TV48 amplifies (blue ii'! 5! 7621).

However, considering that the above stored information is latched by the main amplifier M, the word line selection timing signal φX
and the data line j and the selection timing signal φy are set to low level to separate the ;'Morisel and the router kt&, the data line and the common data line. And, in the evening, Shinkyu φ
Box 1. φpa2 is also low [/as a bell, memory area f
When the data line of is set to high impedance state (and timing%, /gparf, φpc, r.
Then, the recharging operation starts at t??1. That is, precharging for the next 1h of extension jj12f1 is performed in advance.

Note that the signal amplified by the main amplifier MA is sent out from the external terminal through the data output buffer 7DOB, which operates in accordance with the rising edge of the timing pulse φop.

[Effect Go+l) The precharge operation of the next operation cycle is performed during the idle time of that operation cycle, in other words, the main amplifier M
/', By performing this while the data output bumper DOB is operating, precharging in the next operation cycle can be omitted, resulting in an effect that the access time can be increased by 1!7. In addition, in the write operation, since the write data of a relatively large level is input, the time required for the write operation to the memory cell can be shortened, so the precharge period as mentioned above is set after the write is completed. It is possible to provide

The invention made by the dud r71 person has been specifically explained based on the examples above, but it goes without saying that this invention is not limited to the above examples and can be modified in various ways without departing from the gist of the invention. Nor. For example, the specific circuit configuration of each circuit block constituting the pseudo-static RAM can be modified in various ways. Further, the storage bit can take various transformations such as x1. Furthermore, a state-of-state flip-flop is used as a memory cell.
ΔM can also be applied in the same way in cases where britching is performed as described above.
Since the 11,000 P-di is performed when the word line is not selected, the memory cells are removed from the data line pair without generating DC mIN, and it is possible to achieve the effect of reducing power consumption. . In addition, the precharge is
Although the precharge voltage is /2Vcc, the voltage may be charged up to Vcc for m-source lightning.

[Application field]

This invention can be used in an internally synchronized MO3-19 system that extends an external atlus and forms a series of timings fn ``j that control internal operations. .

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention. FIG. 2 is a circuit diagram showing a military embodiment of the main circuit, and FIG. 3 is a queen diagram for explaining the readout function f7:. M-ARY...Memory array, Pct...Precharge circuit, SA...Sense amplifier, 1iADB...Row address buffer, C5W...Column switch, (, -
ADB...Column address buffer, R-DCR...Row address buffer, C-DCR...Column address decoder, PC2...Precharge circuit, MA...Main amplifier, REG, CEG...Edge trigger circuit, 'FG
・・Timing generation circuit, REF・・Automatic refresh circuit, DOT3・・Data output buffer, DIB・・Data person Kaba Nofa, MI)

Claims (1)

[Claims] 1. In an internally synchronous semiconductor memory device that detects the change timing of an address signal and controls the operation of an internal circuit, the word in the memory array is M characterized in that the selection operation of the line and data line is finished, and the precharging operation of the data line in the memory array is started.
O3 storage. 2. The memory cells constituting the memory array are composed of an information storage capacitor and an address selection MO3FET, and the peripheral circuit for writing and reading of this memory cell is composed of a CMO5 circuit. An MO3 storage device according to claim 1, characterized in that: 3. The first aspect of the present invention is characterized in that the complementary data line pair constituting the memory array is precharged by short-circuiting the complementary data line pair.
or the MO3O3 storage device described in paragraph 2.