JPS6068455A - Microminiature computer - Google Patents

Abstract

PURPOSE:To extend easily a system by drilling plural through holes for system extension to a circuit board containing a CPU and a memory circuit element. CONSTITUTION:A training module consists of a module main body 1 containing a microprocessing unit MPU, an RAM, etc. looded on a printed base board 2 and a pocketable console 3 which is connected to the main body 1 via a flat cable 4. Many through holes are formed closely at the blank area of the board 2 for the extension of the system. Each of these through holes consists of <=10 close by aggregated fine pores.

Description

[Detailed description of the invention] This invention relates to microcomputers.

For example, by Genshiki Baba: Encyclopedia of Latest Electronic Devices (1937)
Pages 15 to 17 of the publication (published on March 20, 2013) describe the CP of a microcomputer (ultra-small computer) that has a storage device, control device, and arithmetic device mounted on a single semiconductor chip.
U (Central Processing■■＋,
4) The microcomputer according to the present invention includes at least a central processing control circuit, a main memory circuit, an auxiliary memory circuit, and a control circuit for peripheral devices on one printed circuit board to configure the computer. It will be described as a computer having a configuration in which a control signal input means and a display means are mounted on the printed circuit board or on the printed circuit board or outside the printed circuit board.

Known microcompact converters, called microcontrollers, were controlled by dedicated machine command signals and did not have appropriate control circuitry for peripheral devices.

As a result, conventionally known microcomputers require a high degree of knowledge and careful attention from the user. Furthermore, as mentioned above, since it does not have an appropriate control circuit device for peripheral devices, it is difficult to use peripheral devices other than those that are special or extremely limited, and furthermore, it requires the user's skilled operating skills. Was.

Microcomputers typically have minimal functionality for relatively wide versatility. Therefore, in use, the user must expand the system if necessary. Previously known microcomputers have not been able to adequately meet the demands for such expansion.

Therefore, one purpose of this invention is to obtain a full-scale microcomputer.

Another object of the invention is to obtain a microcomputer that can be equipped with an input/output device and an auxiliary storage device.

Another object of the present invention is to obtain a microcomputer whose t'z system can be easily expanded.

Another object of the invention is to obtain a microcomputer that can be used in a wide range of applications.

Another object of the invention is to obtain a low-cost microcomputer.

Further objects of the invention will become apparent from the following description and drawings.

One embodiment of the present invention for achieving the above object is a CPU
, peripheral circuit elements and memory circuit elements are formed with closely spaced through holes, and are used for system expansion.

Although not particularly limited, the microcomputer of the present invention can be implemented using an LSI (large scale integrated circuit) for a processor (central processing control circuit) that uses one semiconductor chip that performs 8-bit processing with 78 execution instructions and 7 types of addressing modes, for example. A computer body consisting of a large-scale semiconductor integrated circuit (for example, a large-scale semiconductor integrated circuit device with the product name HD46800), peripheral LSIs (memory, input/output board, etc.),
It can be configured with a pocketable console with a built-in calculator case, which corresponds to an input/output device.

This computer main body has a program memory for assembly language, which makes it easy for the user to learn programs, and because it is a symbolic language, debugging can be performed efficiently.

This device will henceforth be referred to as the training module.

An overview of a training module according to one embodiment of the present invention will now be described.

) The 1/-ning module consists of a module body made up of one printed circuit board, connected to this body by multiple wirings, and multiple key tops and signal displays built into a case similar to that of an electronic desktop calculator. It's like a portable console with the means. This training module is equipped as standard with a monitor and an assembler as firmware as system control programs, and operation of this training module is performed manually using the keys on the above-mentioned portable console. The response to key manual input is 8 segments 14 with 7 segments in mouth shape and decimal point indicator segment as display means.
displayed on the digit digitron display. The maximum of 14 indicators -@ are so-called alphamerics consisting of one or two alphanumeric characters, numbers and special characters. This module inputs the source program from the keys on the console, confirms the input characters on the Digitron display, and then inputs the input characters using the keys on the console. - The i- training module is equipped with an interface on its main body so that it can be used to create a tape deck that is exactly the same type as the tape deck that is commercialized as an audio cassette deck. Therefore, it is possible to assemble a source program from a cassette tape and to modify the source tape. Figure 1 shows an external view of the training module.

This training module has M on the printed circuit board 2.
P U (Mi cr.

Processing Unit ) * RAM (
Random AccessMemory), etc. is mounted on the module body 1, and a flat cable 4 is connected to it.
It consists of a pocketable console 3 connected by Figure 2 shows a block diagram of the module main body 1, and the
The figure shows a block diagram of the pocketable console/I/3.

The respective configurations in FIGS. 1 and 2 are as follows. The MPU is a central processor (central processing control circuit) composed of an LSI, and controls the memory circuit and control circuits for peripheral devices based on machine commands from the memory circuit, which will be described next. MI is RO as a control memory circuit composed of LSI.
M (read-only memory), and contains a monitor program and an assembly program as firmware. M2 is a 128-byte N-channel MOSF
This RAM is composed of an LSI using ET, and constitutes a work area when executing a monitor program.

M3 is a RAM consisting of six IKX4-bit N-MO8LSIs, and constitutes a program area for the user. PIA, 1 is used for an interface between the parallel l10 (input/output) boat body 1 configured as an LSI and the pocketable console 3. C1 is a 26-pin connector, which is used to connect the flat cable 4 from the pocketable console 3 to the main body 1. ACIA is serial I1 configured in LSI
0 port, and is used to connect the cassette tape deck interface 7/8 circuit IO and the system bus.

SB is a system bus, which includes 16 lines of addresses, 8 lines of data, and a R/W (read/write) system for inputting modulated information to a magnetic tape recording means such as a tape recorder and its recording means. This is a modulation/demodulation circuit configured on an LSI for demodulating the modulated recording information from. C
PG is an LSI constituting an oscillation circuit for generating a clock signal, and CR is a crystal resonator for the oscillation circuit. The CT is a frequency dividing circuit composed of an LSI and using a single counter, and outputs a clock signal (1,2 KHz) for timer interrupt 4 and a clock signal (1,2 KHz) used when writing information to a cassette deck tape. -Hz
.

Generates 2.4 KHz, 4.8 KHz). T
R is a 1-instruction trace interrupt generation circuit, and N
M I (Non Mask-able Interr.
uption) Interrupt. BD is a tri-state bus driver configured on an LSI, and has a logic value of 1.
A signal with a 0 state is output, and a signal with a logic value of 1.0 is input in a third state. Since this driver is bidirectional with respect to signals, it is used as a bidirectional bus driver when connecting this expansion seam to the address bus and data bus of the main body 1 when an expansion system is added.

PIA2 is a parallel I10 port configured as an LSI, and is an I10 port used by the user through terminal C2 of the printed circuit board 2.

RM is a remote control circuit for remotely controlling start/stop of the cassette tape deck. As is clear from FIG. 1, two 00 control circuits are provided on the printed circuit board, and therefore control the start/stop of the two cassette decks.

C2 is a 100-bin connector constructed from a printed circuit board 2, which can be inserted into a receiving connector of a card cage when an expansion system is constructed. Hl is a reserve hole for system expansion.

Jl is a jack for inputting an input signal to the tape deck, and J2 is a jack for receiving an output signal from the tape deck.

J is compatible with jack J1, jack for remote control of the deck, J4 Hashack J
This is a tool for remotely controlling a tape deck compatible with 2.

FT is a power supply terminal attached to the printed circuit board 2 and has ten terminals 5 and one terminal 6.

Next, each block of the pocketable console 3 will be explained.

SD is a segment driver, parallel l10PI
The display tube DSP is driven by one display segment pattern signal transferred to eight signal lines PAO to PA7 from AI.

The DSP is a 14-digit, 8-segment source display tube with seven display segments arranged in a square shape and one decimal point display segment per digit.

DC is a 4-16 line decoder. This decoder decodes display digit information consisting of parallel/I/4 bits on four signal lines PBO to PH1 of parallel I10 and PIAI, and generates a display digit select signal and a scan signal for six columns of the keyboard KB.

RD is a display digit selection driver, which is provided in one-to-one correspondence with one digit of the display tube, and receives a digit selection signal from the decoder DC to drive the corresponding digit of the display tube.

The KB is a 6×8 keyboard matrix, and has eight row conductors and six column conductors (not shown), and the key tops are used to connect the row conductors and column conductors to each other by means of key tops at the intersections of the row conductors and column conductors. It has contacts to connect. The six column conductors are each connected to the six output lines of the decoder DC as described above.

EC is an 8-encoder which encodes line information from the 8th line of the keyboard KB and outputs a 3-bit key encode signal and a 1-bit key operation display signal. This total 4-bit signal is parallel I10 baud)
It is transferred to outputs PB4 to PH1 and PH1 of PIAI.

SVR is a switching voltage regulator and serves as a power source (27V) for the fluorescent display tube driving circuit.

The above training module has the following characteristics.

(11 Same 7' bit mask R on 32 on lint board 2
By converting the assembler into firmware to OMM,
It is possible to assemble immediately without loading assembler paper tape as in the past. Furthermore, this R
Using the assembler by OMM, the source program that was manually written for the pocket console 3 was R.
It can be input directly onto the AM memory as an object program.

Therefore, the effort required for program conversion is unnecessary.

Furthermore, since a symbolic language is used, program input and depacking are very easy.

(The 21 console 3 is mechanically separated from the main body 1 and electrically connected to the main body 1 by a flat cable 4.The flat group is made by integrally molding multiple parallel conductors with an insulating material made of plastic. The console 3 is movable relative to the main body 1.The console is constructed in a case similar to a well-known electronic desktop calculator, and is mechanically connected to the main body 1 as described above. Since it is separated into two parts, it can be operated in the palm of the hand, and has excellent operability.

The 17 Sole 3 is also capable of alphameric keystrokes similar to conventional teletype consoles and is less expensive than teletypewriters.

As is clear from FIG. 4 and the above description, this console 3 is further equipped with a 14-digit display (or element) in the same case, so that it is located closest to the key for signal input. can display input signals and information inside the main body 1 during monitoring, etc. Therefore, it is easy to confirm the displayed contents based on key operations.

(3) With the control circuit and jack on the same printed circuit board 2, two cassette tape decks commercialized as audio cassette tape decks can be used as read-only and write-only, respectively, or one audio cassette deck can be used as auxiliary storage. It can be used as a device.

Furthermore, it is possible to program start/stop of the audio cassette deck using a microphone remote terminal provided on the cassette tape deck, and thus it can be used in a manner similar to a magnetic tape storage device for a large computer.

(41 This training module has a connector C2 on the training module main body, so it can be easily converted into an expansion system by simply inserting the training module main body and the expansion board into the card cage.

The card cage has a structure in which four cards (boards) can be inserted and these cards are connected through a common bus.

As expansion boards, RAM memory expansion board, FD
C (Flopy Disc Control) board, DMA C (Direct Memory Acc)
ess Control) board.

CRT C (Cathode Ray Tube Co)
ntrol) boards, etc., and these boards include HTP (Highspeed Ta
pe Puncher) interface.

PTR (Paper Tape Reader)
An interface, TT Y (Te1e type) ink face, etc. are also incorporated at the same time.

Figure 4 shows an example of an expansion system. Insert 1 (training module) and 4 (expansion board) into 3 (card cage) in the diagram, and insert 2 (pocketable console).
, 5 (floppy disk drive), 6 (television), 7
(teletypewriter) is connected.

15+ A terminal PT for power supply wiring is used on the printed circuit board 2 independently of the connectors C, C2.

With this configuration, only the main body 1 and console 3 as shown in FIG. 1 can be used without using an expensive receiving connector for a multi-terminal connector such as C2.

According to this system, the printed circuit board 2 is provided with a jack for an audio cassette deck used as an auxiliary storage device as described above, and the start/stop of this cassette deck is remotely controlled via this jack.

Conventionally, when using an audio cassette deck as an auxiliary storage device, it has been necessary to manually operate the operating buttons of the cassette deck and the buttons or keys of the microcomputer at the same time, taking into account the timing of starting and stopping the cassette deck.

If this method is followed, such troublesomeness will not occur due to remote control.

One of the highlights of this system is that it utilizes the microphone remote terminal provided on the audio cassette deck, and its switching is performed by a reed relay switch.

Since the reed relay switch described above is electrically isolated from other circuits in the printed circuit board 2 and does not restrict the direction of the current flowing between its contacts, it will start regardless of the voltage level and polarity of the audio cassette deck's motor power supply. /stop switching is possible.

Furthermore, since start/stop can be controlled by a program, data can be divided into blocks on the audio cassette magnetic tape.

As mentioned above, a control circuit RM is used for start/stop control of the tape deck.

Details of this control circuit RM are shown in FIG.

In FIG. 5, a reed relay contact SW is connected in parallel to jack J3. The on/off mechanism of the switch is as follows.

Coil L of reed relay 3 is driven by inverter 2 as a buffer amplifier circuit. The inverter 2 is driven by the output Q of the D-type edge trigger clip-flop 1.

The data input terminal of flip-flop 1 has a start/
A stop state signal is input, and a timing signal for determining start/stop timing is input to the clock terminal CP.

Therefore, when a rising signal comes to the clock terminal CP while the terminal RI is at a high signal level, the output terminal Q becomes a high signal level, and the input to the coil L of the reed relay 3 in the figure is set to a low level by the inverter 2. Become. In this state,
Switch SW is in an off state.

Conversely, when the input terminal C is at a low signal level, the clock terminal C
When the signal applied to P rises, the switch SW is turned on.

According to this method, key power from the console 3 can be sent to the main body 1 with a reduced number of wires and without using a complicated circuit to obtain a special control signal.

Conventionally, when creating a key code from the pressed keys of a key matrix (consisting of X lines and X lines),
With all X lines set to logic 0, select the multiplexers (with decoders) connected to the First, the X-line was scanned using the . Select information at that time (Y
Line information) was stored and simultaneously output to a multiplexer. Next, select the X lines one after another with a logic 0 signal, and combine the selection information (X line information) when the output of the multiplexer becomes logic 0 with the previously stored selection information (X line information). I created one key code.

This method has the disadvantage that the circuit is complicated because the X-line and X-in information are selected separately. Furthermore, when creating a key code from two pieces of selection information using computer software, ie, arithmetic processing, there is a drawback that the software becomes complicated.

The key manual method of the Pokentaple console in the training module of this invention is the conventional multiplexer.
By connecting the X-in, which was previously connected to the encoder, to an encoder instead of a multiplexer, the hardware scale and software scale were reduced.

This will be explained with reference to FIG.

The module main body 1 (not shown) and the console 3 are connected by a wire J or a stone, and the console 3 includes a decoder U11, an encoder U, and a keyboard KB.

The decoder U□ has four input terminals 1 to 1 and 1 to 1 to 1,000 to 1,000 yen to the main body 1 to T. to T304 bit binary signal is received. This decoder has 16 output terminals, lines -e, o
-e25 selectively outputs a logic O signal. For example, input line 11! . is logic 1000, output lines -elO to J32. Among them, Linebu. Dayu has logic 0
, and all others are 1.

Similarly, if the input is 0100, the output line! Only 11 is logic 0
becomes.

The keyboard KB has 6 X lines - e1o to! , 6 and eight X lines 13o to -La, and has a contact Cn at the intersection of each X line and the X line. Therefore, the number of contacts is 6×8. The wife's contact point C is operated by the key top KP of the keyboard (see FIG. 1). The X line and the X line corresponding to the operated key top KP are connected by a contact Cn.

X line! 1o to 21. is connected to the output terminal of decoder U1. Y line edict. 1 to 1 and 8 are connected to a power supply via resistors R8 to R8, respectively. Therefore, if the key contact Cn is open, the corresponding X diine is maintained at a potential corresponding to a logic value of one.

The encoder U has eight input terminals O to 7 and four output terminals A to C and GS. The output terminal GS of this encoder outputs a logic 0 signal when a logic O signal is input to any one of the eight input terminals, and outputs a logic 1 signal when all input signals are logic 1. Output.

Therefore, an output determined by a substantial AND circuit (not shown) in the encoder U, which receives eight input terminals, is applied to the output terminal GS.

Signals obtained by encoding the signals of the eight input terminals O to 7 into binary numbers are applied to the remaining output terminals 100 to C of the encoder U. For example, the logic of input terminals O to 7 is 1o
If ooooooo, output terminals A to C will be 100, and o
iooooooo becomes 010, similarly 000000
If it is 10, it becomes 111.

As is clear from the above explanation, the X input of the keyboard KB is selected by the decoder, and therefore the wiring from the main body 1! ,～ノ. is scanned by a binary signal at.

Only when a logic 0 signal is added to the X line corresponding to the key top KP by operating the key top KP, a logic 0 signal is output to the corresponding X line.

Therefore, the X line where the 0'' signal is output is the line where the key is pressed, and the encode p-U
By encoding with t, binary X line information of T4 to T7 can be obtained. At this time, the GS terminal, that is, T7 becomes 0'', and it is determined whether the key is pressed depending on whether T7 is 0'' or 1n. Therefore, T7 is read every time X2 in is scanned in the main body l, and when T7 becomes 0'', T7 is read.
A key code can be created at once from the transmitted binary information of o-Ts and the received information of T4 to To.

In this example, the key code corresponding to the operated key is obtained by processing the information of To to T6, but if necessary, the key code of T. It is also possible to create 6K8 types of key codes using an encoder that receives 6K to T.

In this example, as is clear from the above explanation, the wiring between the main body 1 and the console is T for inputting 48 types of key information. Only 8 wires from Tll to F7 are required.

The above-mentioned manual key system does not require special timing control and a complicated timing generation circuit for the console 3.

With respect to the microcomputer of this invention, an improved playback method is provided for a cassette tape deck used as an auxiliary storage device.

Information is recorded on a tape deck using a frequency modulation method. For example, a logic 0 signal corresponds to a signal at a frequency of 1.2 KHz on a tape deck, and a logic 1 signal corresponds to a signal at a frequency of 2.4 KHz.

Therefore, writing information to the tape deck is performed from the logic circuit via the frequency modulation circuit, and reading information from the tape deck is performed to the logic circuit. 2.4 by comparing with the preset time length
A distinction is made between KHz and 1.2KHz. However, this method has the disadvantage that it is susceptible to changes in the duty ratio or frequency of the reproduced modulation signal caused by the mechanical characteristics of the input tape deck.

These drawbacks are eliminated in a manner as explained in the following example. A circuit of a specific embodiment is shown in FIG. 7, and a time chart thereof is shown in FIG.

In FIG. 7, the reproduced signal from the tape deck is inputted via jack J to a low-pass filter consisting of resistor R4 and capacitor C8. The signal from the low-pass filter is inputted via a coupling capacitor C4 to an amplifier circuit Amp which is biased by a bias circuit including resistors R3 to R6, and is converted from a sine wave to a rectangular wave by an inverter INV.

Depending on whether the recording signal on the tape deck is logical 0 or 1, 1.
The frequency is 2KH2 or 2.4KH2, and the output signal of the inverter NV is ha! V has a frequency of 1.2KHz or x2.4KHz.

The output of impark INV is a D-type flip-flop F1.
to F8. Nant gate G1 and G21 force counter circuit F
A digital one-shot circuit consisting of 4 and F, and D
Type flip 20 tube circuit F.

and counter times MF, Nantes Gate G2. Noah Gate G
3. The signal is input to a reading time setting circuit consisting of an AND/NOR gate G and an inverter INV.

In the digital time setting circuit described above, the D-type flip-flops F1 to F are configured to read the input from the input terminal at the rising edge of the signal at the clock terminal Cp. Clip-flops F and F2 receive at their clock terminals C a 307.2 KI-Izz signal which has a much higher frequency than the 1.2 KHz or 2.4 KHz signal from the tape deck. Noritsubu flop F, is inverter NY,
A pulse signal of 307.2 KHz is output to the output terminal Q within the same period as the period in which the output of is logic 1, and the flip-flop F2 outputs a pulse signal of 307.2 KHz to the output terminal Q with a delay of one clock time. A Hz pulse signal is output.

With the outputs Q and Q of the clip-flop circuits F and F2, the Nant gate generates an output that becomes a logic 0 for one clock period from the time that y coincides with the rise time of the inverter INV, and becomes a logic 1 at other times. generates the output of The output of gate G2 is sent to counter F4. Added to the initialization terminal for F.

The D terminal of the Noritsubu flop F has a logic 1 potential "■".

. '' is added to the CP terminal, and the output Q of the flip-flop F is applied to the CP terminal.The signal to the reset terminal R (
(described later), the clip-flop F3 at the reset terminal receives the output of the clip-flop F, and produces a logic 1 output at its output terminal with a delay of r1 clock time from the rise of the signal of the inverter INV.

The output of the logic 1 of the clip-flop F3 causes the counter F
4 is applied with a 307.2 KHz signal via gate GI.

Counter F4. F, consists of a hexadecimal counter, 1
．． 2. 4. A control game with a weight of 8) has A to A. With A through ground, F4 is a hex counter, and with C and D ground, F is a hexadecimal counter. As a result, counter F.

generates a carry 625 μS after the output of F becomes logic 1. This carry allows the inverter INV
, through the Noritsubu flop F3° counter F, , F,
requires a reset.

The above-mentioned count time is equal to 1.0 of one period of the 2.4 KHz signal.
This corresponds to five times as long.

From the tape deck! j When a 2.4KHz signal is being regenerated, an initialization signal is applied to the counter from gate G2 before a carry is generated from counter F, and the contents of the counter are cleared, so a reset signal is applied to flip-flop F. do not have.

Since the load signal is not generated from the gate G2 within the counter time for the Wl, 2 KHz signal input from the tape deck, the counter F is added to the clip 70 block.

As a result, the flip-flop F3 generates a signal as shown in FIG. 8 based on the output signal from the tape deck.

The Norinob flop F6 receives the output Q of the Norinob flop F3 at its D terminal, and receives the output of the inverter INV at its clock terminal CP, so that it outputs a signal as shown in FIG. 3 at its output terminal QK.

The output of the Noritsubu flop F is the logic 0.0 of the signal recorded on the magnetic tape. This is a signal demodulated to 1.

1, 2. 4. Output terminal QA with weight of 8, Q8゜Q
A counter F7 having QDs and various gate circuits attached thereto generates a timing clock Rxc. This timing clock Rxo is used to define the readout time of the output signal RxD from the flip-flop F, which has been converted into two communication signals. can output a pulse width that is more than 10 times more accurate than the conventional CR one-shot.

According to this method, Alpha Nori'
An improved display method is adopted for the display of 7.

Conventionally, 7-segment LEDs (light emitting diodes) and fluorescent display tubes have a range of 0 to 9. The display was only up to A-F. This hexadecimal display alone is inconvenient because it is not possible to display, for example, assembler source statements. There are 5 x 7 dot tomato and RIX type displays that can display alphanumeric characters, but these have the drawbacks that the hardware is complicated, such as requiring a decoding circuit, and the display element itself is expensive. there were.

In the training module according to the present invention, alpha vents, numbers, 1% special characters can be displayed using the 7-segment i-display, which is widely used as a display on calculators and the like. The symbol representation is a segment pattern that is as close to the symbol that is being expressed as possible.

The greatest advantages of this 7-segment alphanumeric and special character display are as follows.

(1) The display element is inexpensive.

(2) The external display circuit is simple. In other words, it is possible to create a segment pattern directly from 1 byte of display data.

(3) The display element is small.

A specific method of displaying alpha vents, numbers, and special characters using 7 segments is shown in FIG.

The upper row of each book is the alpha bent and number of the display contents.

Special characters are shown, and the lower row shows the corresponding 7-segment display method. For reference, 7 segments with don'ts are also shown.

The keys of the pocketable combination according to the present invention are arranged with good operability. In conventional keyboard layouts, the alphabet keys are arranged randomly, and the arrangement of the numeric keys (0 to 9 are arranged regularly from the smallest number to the largest number) is also taken into account. Not yet. Therefore, there was a drawback that it took a long time to find the keys to press until the keyboard layout was adjusted. FIG. 10 shows the plane of the keys employed in the pocketable computer of the present invention.

This key has a decorative plate 4 and a key top exposed through a plurality of holes provided in the decorative plate 4. A symbol corresponding to the input is formed on the key top 5, and other symbols are printed on the decorative board. As shown in the figure, the key tops are arranged in ascending order of numbers starting from the top left, first letters of the alphabet in alphabetical order, similar to a dictionary.

This arrangement is based on the fact that the keys are arranged in the order that people (operators) are used to in their daily lives, and because the number 9 is followed by the alphabets A, B, and C. It is easy to operate.

This can be said to be a great advantage since hexadecimal numbers are often used when computers are used. Furthermore, the color of the keys on the pocketable console is such that function keys such as hexadecimal numbers (0-9.A-F) and cents are color-coded from other keys (described later), making it easy to search for keys. There is.

The key tops are light blue and the letters are black, and the keys like ■ have white key tops and black letters. Also, special characters are printed on the decorative board as described above, and including these characters, the key includes all ASCII characters.

Next, other functional features of the microcomputer according to the present invention will be described.

Regarding abort interrupts and timer interrupts; Product name HD4
68000MPU has NMI (NonMask
ablc Interruption) and I RQ
There are two types of interrupts: (InterruptRequest). When the rising waveform No. 41 is input to the 8M1 terminal of the MPU, the processing of the MPU always moves to the NMI interrupt processing subroutine.

On the other hand, when a rising waveform is input to the IRQ terminal, the mask bit of the Lucister (register indicating the status 'Bta) in the MPU becomes O"
', the MPU processing shifts to the IRQ interrupt processing routine. In this way, the abort interrupt and timer interrupt utilize the NMI interrupt and IRQ interrupt, respectively.

, As shown in (1) in the IE12 diagram, the 1 abort interrupt is generated by inputting the signal input manually from the AB key of the keyboard (KB) to the -HPIAf) CAI terminal, and
1 (Output from the QA terminal to the NMI terminal of the MPU.

When a signal enters the CAL terminal, the bit corresponding to the PIA register CAI becomes 1", and the monitor judges this flag and changes the bit of the register corresponding to the IRQA terminal to "O".
'' (set to i'X[1'') and generates an NMI interrupt. On the other hand, (2) in Figure 12 shows a timer interrupt, and as can be seen from the figure, the 1 or 2 KHz clock generated from the OCT block in Figure 2 is connected to the PIA's CBI.
input to the terminal. Like the CAI terminal, the CBI terminal also has bits corresponding to registers.

When the high level of the clock is input to CAI, this bit becomes 1'' and an IRQ interrupt is generated from the IRQB terminal at the discretion of the program.

Conventionally, NMI interrupts have been used only for top-priority interrupts such as system power failures, because interrupts cannot be prohibited.

As mentioned above, in the microcomputer of the present invention, by making the abort interrupt an NMI interrupt via -HPIA, the interrupt to the MPU's NMI terminal can be prohibited or delayed by the monitor. It became possible to do so.

According to this method, a timer interrupt occurs in this system,
It is used by not accepting abort interrupts during timer interrupt processing (counting when an interrupt occurs) and processing abort interrupts only after the timer processing ends.

Regarding the 1-instruction trace interrupt generation circuit: FIG. 11 shows the 1-instruction trace interrupt (NMI interrupt) generation circuit used in the present invention and its time chart. This circuit is a circuit for generating an NMI interrupt to the MPU by a program. When the D terminal of the D-type Noritub flop is set to Low level by a program, the D-type Noritub flop becomes High level. This Q output, φ, and TTL clock are processed by a synchronous 4-bit counter (product name: HD74).
161) 2 to the L and CP terminals, respectively.

When Q becomes High level, counting starts, and the CAR terminal of the 11th cycle becomes High level. When the D terminal of the D-type clip-flop returns to High level by program processing, Q becomes Low in synchronization with the rise of φtTTL.
It becomes OW level. At this time, CAR becomes Low level. Since the NJ and I interrupts to M p U occur at the end of the village, output CAR (L C IJ -) K as the NMI signal.
I'm using something that goes through an inverter.

The circuit described above uses the function of the L terminal of the counter to reduce the latch by one compared to the conventional circuit, and has a simpler circuit configuration.

Regarding prevention of destruction of LSI on a printed circuit board: In the microcomputer according to the present invention, a large number of highly integrated semiconductor circuit devices (LSI) are incorporated on the printed circuit board 2, but in the unlikely event that this printed circuit board 2 In order to prevent these LSIs from being destroyed if the power supply terminals (for example, S, T) of the As shown, a diode K is mounted on this printed circuit board between the power terminals (S, T) of the printed circuit board 2 with a predetermined polarity.For reference, FIG. v output characteristics.By mounting a diode between the power supply terminals on the printed circuit board in which the LSI is incorporated, there is no need to install a special fuse in the power supply input circuit as in the past. , even if the father's side is connected in reverse, there is no need to replace the fuse, and it can be easily done by simply reconnecting the printed circuit board.

[Brief explanation of drawings]

FIG. 1 is a perspective view of the ultra-compact converter of the present invention, FIG. 2 is a schematic diagram of the main body 1 of FIG. 1, FIG. 3 is a schematic diagram of the console 3 of FIG. 1, and FIG. A conceptual diagram to explain an example of the application of a microcomputer, Fig. 5 is a circuit diagram of the remote control circuit, Fig. 6 is a block diagram of the key human power section, Fig. 7 is a circuit diagram of the modulation/demodulation circuit, and Fig. 8 is an operating waveform diagram of the circuit in Figure 7, Figure 9 is a display pattern diagram of the display tube,
Figure 40 is a plan view of the keyboard, Figure 11 is a circuit diagram and time chart of the interrupt generation circuit, Figures 12 (1) and (21) are circuit diagrams for explaining other interrupt circuits, Figure 1
3(a) and 3(b) show a circuit diagram and characteristic diagram for explaining the power supply connection to the printed circuit board. 1... Computer body, 2... Printed circuit board, 3
...Console, 4...Flatkafe A/. Figure 12 (1) (2) Figure 13 (b) Hand balance correction form (method) Indication of the incident 1981 Patent Application No. 81786 Name of the invention Ultra-compact combeater correction person 1 Book with rumors Patent application Person's name: +510+I,T Co., Ltd. Hitachi Manufacturing Agency Contents of drawing corrections subject to personal corrections As per attached sheet

Claims (1)

[Claims] 1. (a) a central processing control circuit; (b) a memory circuit; (c) at least one peripheral device control circuit; A microcomputer made of a circuit board with holes. 2. The ultra-compact conbeater according to claim 1, wherein the plurality of through holes are composed of ten or more closely spaced pores.