JPS6065684A - Reception timing regenerating system in variable length coding - Google Patents

Abstract

PURPOSE:To demodulate correctly a real time signal by controlling the timing of reception side so that the sum of degree of storage of a transmission/reception buffer memory is kept constant thereby obtaining a stable timing. CONSTITUTION:The degree of storage of the buffer memory 7 is fed to an output of a coder 9 at a proper interval, e.g., once at one horizontal period or once per one field. On the other hand, the data of degree of storage at the transmission side and the degree of storage at the reception side are added by an adder 11 while the degree of storage data in the transmission side memory 7 is obtained in the process that a decoder 10 at the reception side reads sequentially picture information from a buffer memory 8 and restores it. Then a voltage controlled oscillator 12 is controlled so that the sum becomes constant. Thus, a stable timing is obtained and the real time signal is demodulated correctly.

Description

[Detailed Description of the Invention] [Original Field of the Invention] The present invention is based on the problem that a real-time 1- signal such as a television n= signal is subjected to variable length synchronization on the receiving side (i.e. The present invention relates to a timing recovery method, and particularly to a timing recovery method suitable for multiplexing .:I'] information for the same coded data and timing.

[Background of the invention]

When variable-length encoding is performed in the quotient efficiency encoding of the allevision signal, the parts where there is a lot of information 1t in the original signal (in interframe encoding &, j: 1 with movement (6 minutes), In encoding, there is a large amount of encoded data to be transmitted in a file (such as a small image part).In such cases, a buffer memory is placed and a transmission path (a broad transmission path such as a recording device) is used. Make the flow of data uniform.

However, if this is done, the time spent in the sofa memory during transmission (111) will be longer than V, and the real-time nature of the signal on the transmission path will be disrupted.

On the other hand, on the receiving side, Prevision No. 18 'c j"+
There is peace of mind that you can display the actual product correctly (at a certain time)
] (aside from the delay).

In a transmission system such as communication C, the receiving (;'4 +1III
(Also) (Sofa memory is usually set to 1).

Therefore, there is a problem in that it is unclear at what point the receiving section should read out the information stored in the buffer memory.

In order to solve this problem, as shown in Figure 1, only the timing information 1 and 2 is stored in the buffer memories 3 and 4 of these transmitting and receiving buffers.
There is a synchronous 100-bit transmission system that avoids the collapse of real-time performance due to the reduction in buffer residence time by bypassing the buffer. ('l'41' Publication No. 53-5124 "Synchronized signal transmission system for interframe coding of image signals") However, in this case, the place where the timing reproduction information 1.2 is input is the buffer memory. 3.4 (on the opposite side of encoder 5 and decoder 6 in a narrow sense), its input and output were complicated. For example, when entering information on the sender side,
This is because it is not easy to determine which bit should be inserted between which bits. In other words, there was a problem of complexity in controlling human output.

[Purpose of the invention]

SUMMARY OF THE INVENTION In order to solve these problems, it is an object of the present invention to provide a new method based on the premise that information for timing reproduction is stored in a buffer memory along with image data.

[Summary of the invention]

In the present invention, in order to achieve the above object, the idea of bypass, which causes this complexity, is not taken into account, and on the contrary, timing information is passed through both Bacher memories in the same way as general data. Then, the timing on the receiving side is controlled so that the time required for passing through both buffer memories is constant. That is, the configuration is such that the timing generation circuit on the receiving side is controlled so that the sum of the amount of data stored in the transmitting side buffer memory and the sum of the amount of data on the receiving side is constant.

[Embodiments of the invention]

An embodiment of the present invention will be described below. First of all, the original 1i1i
This will be explained with reference to FIG.

As mentioned above, in order to correctly reproduce the timing on the receiving side, it is sufficient that the timing data of all the cylinders and the front chamber 1 are delayed by a certain period of time. For this purpose, send
The total sum of data stored in each buffer memory 7.8 of the receiver must be one foot.

In FIG. 2, the amount of storage in the buffer memory is inserted into the output of the encoder 9 at appropriate intervals (for example, once every 1000 cycles or once every field). Specifically, the encoder reads the storage status of the sofa memory at the end of the encoding (for example, the end of the horizontal period mentioned above), and
Just insert this.

On the other hand, on the receiving side, in the process of sequentially reading data from the sender and transmitting image information using the decoder 10, when data on the storage status of the buffer memory on the sending side is obtained,
An adder circuit 11 adds this amount to the amount of storage on the receiving side. Then, the voltage controlled oscillator 12 is controlled so that the slope is constant.

At this time, if the oscillation frequency of the oscillator 12 is higher than the frequency that can be defined by the oscillation frequency on the transmitting side, the reproduction frequency of the TV timing on the receiving side will be higher and the buffer memory will be read earlier. As a result, the total amount of data stored in the sending and receiving memories will be less than the specified value. Conversely, when the number of oscillations is small like this, the oscillation frequency of the oscillator 12 is controlled to be lowered.
L good.

Next, a specific example of the transmitting side of this embodiment is shown in FIG.

This buffer memory is well known. That is,
It is composed of a normal memory 14, and can be equipped with a built-in address counter 13 and a read address counter 12. When writing, it is written to the 4th address of the address counter 13 and incremented by one when the writing is completed.

The same applies to reading. In addition, it is a well-known technique (F) to perform operations such as filling in useless information when the reading is about to overtake the reading.
Control to prevent overflow is also often carried out.

Now, in the conventional transmission method, as shown in FIG. 4, a synchronization button is inserted between image data. 1m is one break in encoding in the narrow sense encoder 9 (
This is done at the end of 1,000 cycles of water, etc.). This is accomplished by switching the electronic switch 16 under the control of the encoder 9 to output a synchronous bang output.

In the embodiment of the present invention, the memory amount is sent out following the synchronization pattern as shown in FIG.

Therefore, the storage condition of the memory, that is, (write address) - (read address) is requested from the subtraction circuit 15,
Send this. Note that, in the case of a negative value, it is natural that the amount of storage can be similarly displayed by calculation modulo the total capacity of the transmitting side memory.

FIG. 6 shows a specific example of the receiving section in the embodiment of the present invention. Buffer memory 8Il'j: configured similarly to the memory on the sending side. Then, information 181''l indicating the storage capacity of the memory on the receiving side is added to the information about the storage capacity of the memory on the sending side read from this memory by the adder 11.

This is compared in a subtraction circuit 19 so that it becomes a constant value C, and the voltage controlled oscillator 12 is controlled by this output. As is well known, there are various relationships between the subtraction circuit 19 and the oscillator 12 in actual circuits, and as shown in FIG. 2, there are configurations that do not require the subtraction circuit.

〔Effect of the invention〕

As mentioned above, although the embodiment has been described based on the basic idea of keeping the sum of the data stored in the sender's buffer memory 1 and the receiver's buffer memory constant, there are many variations to this. There is.

These are listed below.

(a) The IIC of data stored in the sending and receiving buffer memories is not necessarily equal to the capacity of each sending and receiving memory. It is also possible to prepare a large amount of buffer memory.

(b) Sending data it is sent at the coding break and t
Not limited to Yu. When Q is a certain specific value, it is possible to send it as a complete command.

(C) When encoding the horizontal synchronization or vertical synchronization portion, the amount of data generated is reduced using the normal tq encoding method. Therefore, if the maximum memory 'JjtfL is suppressed to this amount, it is possible to use a system in which the storage capacity is reduced to 0 when the synchronization part ends. At this time, it is also possible to control the excavator so that the storage amount on the receiving side becomes a constant value C.

(d) In addition to the memory formats shown in Figures 3 and 6, the buffer memory may be FIFO (pIrst
There are methods such as In First 01lt) memory, or a combination of these.

As described above, according to the present invention, the timing on the receiving side is controlled so as to keep the sum of the storage levels in the sending and receiving buffer memories constant, and stable timing is obtained to ensure correct adjustment of real-time signals. ” can be done.

[Brief explanation of the drawing]

Fig. 1 is a conventional block diagram for synchronization timing generation; Fig. n2 is a block diagram of an embodiment of the present invention; Fig. 3 is a main part diagram of Fig. 2; An explanatory diagram, FIG. 5 is an explanatory diagram of the present invention, and FIG. 6 is a main part diagram of FIG. 2. 7. Buffer memory, 9. Encoder, 10.
・Coffee, 12...frost 1 pressure 1u1) Osatsushiki. Figure 3: 4 Senshin Izo 12Z Synonymous Pattern Color 4 Illustrated Pattern Figure 5: Procedures Amendments to the Case 1982 Patent Application No. 172937 Title of the Invention Variable length coding Relationship with the case of a person who corrects the reception timing regeneration method Patent applicant name (5] 0) Hitachi Co., Ltd. Manufacturer Managing Director Address: 5-1 Marunouchi-chome, Chiyoda-ku, Tokyo 100 Hitachi Co., Ltd. Works Inner Type Story Tokyo 212-1111 (Major Representative) Image of the Amendment The section of the “Claims” section of the specification, Contents of the Amendment 1, Specification of the present application, page 1, and the scope of the claims are attached to the attached sheet. Correct as expected. 2. Ibid.'' Book 1, page 4, line 8, ``In other words...
. . ” to the 12th line, “It is a thing.” are deleted. 3. “Sum of data” in Book 2, page 4, line 20 of “Ibid.”
is corrected to the "sum of data delay times". 4. Ibid., page 5, line 4, "or once per field" is corrected to "once per field or once per frame". 5. Ibid., page 5, lines 5 to 6, replace "break (for example" the end of the horizontal period in item 1) J with "break (for example, the horizontal period T or frame period, such as the above horizontal period or frame break, etc.) In the below, when t=0, it is corrected to 1tD). 6. Ibid., page 5, line 15, ``Nao'' is corrected to ``That is.'' 7. In the same text, page 5, line 20, change “data” to “
Correct the data retention time. 8. Ibid., p. 6, line 19, r (when one horizontal period ends) is deleted. 9. Ibid., p. 7, line 10, "...of course. "[It is also possible to insert and send time information (1=1) that is actually read out from the buffer memory and transmitted." 10, Ibid., No. 7 page, line 16, after “added.” “This signal is added by the timing circuit on the receiving side, t=T
(1 = 0 in the next cycle), so by knowing the timing 1' of the receiver at the time of reception, the time remaining in the buffer memory on the receiving side (
'T' - t') can also be known.' 11. Ibid., page 7, lines 17 and 19, and page 8, line 1, "subtraction" is corrected to "addition." 12. Ibid., page 8, lines 5-6 and lines 9-10, "sum of data" is corrected to "combination time". ”
Claim 2: An encoder that encodes a real-time signal into a variable length encoder. A transmission side buffer memory that smoothes the data tray of the encoder output, a transmission line that transmits the output of the sofa memory to the above, a reception side buffer memory that temporarily holds the signal received from the transmission line, and the variable length encoding described above. In a system including a decoder corresponding to an encoder, a timing generating circuit on the receiving side is controlled so as to keep the sum of the time stored in the transmitting side buffer memory and the time on the receiving side constant. This is a reception timing recovery method in variable length coding.

Claims (1)

[Claims] 1. A signal unit that encodes the real-time signal length and length, and a transmitting side buffer memo that smoothes the cheater rate of the output of the signal generator. In a system including a receiving side buffer memory for temporarily holding No. 46, and a post-signal unit corresponding to the above-mentioned variable-length equalization coder, the first part of the amount of data stored in the sending-side buffer memory is A timing regeneration method in variable-length FJ encoding, in which the timing regeneration method on the receiving side is controlled so as to make the sum of the sum of the above and that on the receiving side one.