JPS6063790A - Pseudo static memory - Google Patents

Abstract

PURPOSE:To reduce an ON-ON current of a timer circuit and reduce an average operating current by composing the timer circuit, which is installed to a memory, with pMOST and nMOST and impressing a power cut signal and rest signal to said circuit. CONSTITUTION:When an input signal phiIN becomes ''0'' (t32), a node N31 becomes (-)VTN, a node N32 becomes less than VDD-¦VTP¦, and a transistor (TR) Q35 is turned ON. However, the TR Q35 is turned OFF since the power cut signal phiC is ''1'' and ON-ON current I will not flow from an electric power supply VDD to ground electric potential. When the signal phiC temporarily becomes ''0'' at time T35 and the Q35 is turned ON, the node N34 is charged. Since current capacities of TRs Q34 and Q35 are low, the rise of the electric potential of a node N34 is slow. However, when electric potential exceeds VTN, the output signal of an NAND circuit 2 becomes ''0'', a TR Q38 is turned ON, a TR Q36 is turned OFF. As a result, the node N34 speedily becomes VDD through TR Q38 having more electric potential than TRs Q34 and Q35. At the time t36, a reset signal phiR becomes ''ON'' and output signal becomes ''1''. As mentioned above, the ON-ON current of the timer circuit can reduce the average operating current since the signal phiC will flow only during ''0''.

Description

[Detailed description of the invention] [Technical field to which the invention pertains] The present invention relates to pseudo-static memory.

[Prior art]

Semiconductor memories have become highly integrated due to advances in microfabrication technology in recent years. In particular, dynamic RAMs are becoming increasingly large-capacity because the memory cell structure is simple. However, there is a drawback that it is necessary to refresh the data held in the memory cells even during standby, making external control complicated. A timer circuit is designed to eliminate this drawback.

Pseudo-static memory has been developed which incorporates an internal refresh circuit consisting of an internal address counter and an internal refresh control clock generation circuit and automatically refreshes during standby.

An example of a timer circuit used in a conventional internal refresh circuit is shown in FIG. This timer circuit is a p-channel MO8) transistor (hereinafter referred to as pMO8T).
The source of Q3 is connected to the power supply VDD, the gate is connected to the precharge signal φP, and the drain is connected to the node N2, respectively, to form an n-channel MO8)9 transistor (hereinafter referred to as nMO8T).
The drain of Q2 is at node N2, the gate is at ground potential, and the north is at node N.

and connect one of the capacitors C1 to the input signal φ
IN and the other to node N1, respectively, and nMOS T
Connect the drain/gate of capacitor C2 to node N1 and the source to ground potential, and connect one side of capacitor C2 to node N2.
and the other is connected to the ground potential, and the drain of pMO8TQ is connected to the output signal φ. It consists of connecting the gate to the UT, the source to the node N2, and the power supply vDDr (respectively), the drain of nMO8TQs to the output signal φotrr, the gate to the node N2, and the source to the ground potential.

pMOS TQ 4 and nMO8TQs are 0M
It constitutes the inverter l of O8. Here, nMO8
It is assumed that the current capability of TQ6 is much larger than that of pMO8TQ4.

Next, the operation of the timer circuit shown in FIG. 1 will be explained using the operation timing diagram shown in FIG.

At time tl, the precharge signal φP goes to the ``0'' level, the contact +jC2 is charged, the node N2 goes to the 91'' level (here, the DD level), and the output signal φ11.
□ becomes “0” level.

At time t2, when the input signal φIN goes to the ``0'' level, the coupling of the contactor -TC+ causes the input signal φIN to reach the node N.

becomes a negative potential, nMO8TQt turns on, and when the threshold voltage of nMO8T is VT'eVTN, capacitor C2
Charge flows from to capacitor C1, and the potential at node N1 is (→
It becomes VTN. At this time, the threshold voltage v of pMO8T
If T is VTP, the potential of node N2 is VDD l
The level becomes lower than vTP +, and both pMO8TQ4 and nMO8TQ5, which constitute inverter 1, are turned on. Therefore, the power supply VDD yj・rapMO is applied to inverter 1.
8TQ4, nMO8TQs k to ground potential through current I
(hereinafter referred to as on-on current) flows.

At time t3, the input signal φIN reaches the 51" level and the coupling of the capacitor C1 causes the node N to reach the "1" level, but nMO8TQ3 is turned on and the potential at the node N becomes "TH".

When the input signal φIN reaches the 10'' level at time t4, the voltage from capacitor C2 to capacitor C is the same as at time t2.
Charge flows into I, and the potential at node N2 becomes less than TN.

Therefore, nM08TQ5 of inverter 1 is turned off,
I) Output signal φ by MO8TQ4. IJT is ゝゝ1
“Get to the level.

As explained above, in the conventional timer circuit, the time t
2 to time t4, an on-on current I flows through the inverter 1, increasing the average operating current of the timer circuit.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a pseudo-static memory having a timer circuit in which the on-on current is reduced and the average operating current is reduced by eliminating the above-mentioned drawbacks.

[Structure of the invention]

In the pseudo-static memory of the present invention, the drain and gate of the first field effect transistor are connected to the first node, the source is connected to the first power supply, and one of the first capacitors is connected to the first input signal, and the other is connected to the first input signal. the drain of a second field effect transistor of -conductivity type is connected to the second node, the gate is connected to the first power supply, the source is connected to the first node, and a second field effect transistor of negative conductivity type is connected to the first node. The drain of a third field effect transistor of the type is connected to the second node, the gate is connected to the second input signal, and the source is connected to the second power supply, respectively, and one of the second capacitors is connected to the second node, the other is connected to the second node. are connected to the first power source, and the drain of a fourth field effect transistor of opposite conductivity type is connected to the third node, the gate is connected to the second node, and the source is connected to the second power source, respectively. The drain of the fifth conductivity type transistor is connected to the fourth transistor.
The gate of a sixth field effect transistor of conductivity type is connected to the fourth node, the gate is connected to the third input signal, the source is connected to the third node, the gate is connected to the fourth node, and the source is connected to the output signal. - a drain of a seventh field effect transistor of conductivity type is connected to the fifth node, a gate e is connected to the second node and a source is connected to the first power source, and a seventh field effect transistor of opposite conductivity type is connected to the first power source. The drain of the eighth field effect transistor is connected to the fourth node, the gate is connected to the output signal, and the source is connected to the second power supply, and the drain of the ninth field effect transistor of the opposite conductivity type is connected to the output signal. The gate is connected to the fourth node, the source is connected to the second power supply, the drain of the - conductivity type tenth field effect transistor is connected to the sixth node, and the gate is connected to the fourth node.
The sources of the eleventh field effect transistors of opposite conductivity type are connected to the output signal, the gates thereof are connected to the fourth input signal, and the sources of the eleventh field effect transistors of opposite conductivity type are respectively connected to the second power source. and a timer circuit formed by connecting a drain of a twelfth field effect transistor of -conductivity type to the output signal, a gate to the fourth input signal, and a source to the sixth node.

[Explanation of Examples]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 3 is a circuit diagram of a timer circuit used in one embodiment of the present invention.

The timer circuit used in this example is r+MO8TQ3
The drain and gate of 1 are connected to the node N31, and the source is connected to the ground potential, and one of the capacitors +jC3I is connected to the input signal φ, and the other is connected to the node 1'Jst.
The drain of MO8TQsz is connected to node N32, the gate is connected to ground potential, and the source is connected to node N31, and I) MO
The drain of 8TQ33 is connected to the node N32, the gate is connected to the precharge signal φ, and the source is connected to the power source Va.

and connect one side of capacitor C32 to node N3.
H and the other to ground potential, pMO8TQ3
The drain of pMO8TQss is connected to node N33, the gate to node N32, and the source to power supply VDD, and the drain of pMO8TQss is connected to node N! 4 is the gate power cut signal φ.

The sources are connected to node N33 respectively, and nMO8TQ
Output signal φ from the drain of sg to node N34. U
T sources are connected to node N35, respectively, and nMO8T
Q.1. The drain of is connected to node N3S and the gate is connected to node N11.
2, connect the sources to the ground potential, and connect the spM OS
Connect the drain of TQss to node N34, the gate to the output signal source, and the source to the power supply VDD, respectively, I)
The drain of MO8TQ39 is connected to the output signal i, the gate is connected to the node N34, and the source is connected to the power supply VDD, and n M
Connect the drain Φ of OS T Q40 to the node 1'lsa, the gate to the node N114, and the source to the ground potential, 11) Connect the drain of M08TQ41 to the output signal 6i, the gate to the reset signal φR, and the source to the power supply VSEI, nMO8TQ 42
The drain of the output signal 6i and the gate of the reset signal φR
It consists of connecting the source to node N3 (+).

Although the first power supply is at ground potential here, it is generally the source power supply VSS. Also, p M OS'
If' Qas! Q41 and n M O, S T Q
401Q42 constitutes the 0MO8-NAND circuit 2.

I'll take it as a gift.

Next, refer to the operation timing chart shown in FIG.
The operation of the timer circuit shown in the figure will be explained.

At time 131, when the precharge signal φ2 reaches the "0" level, pMO8TQas turns on and charges the capacitor C82, and the node N32 goes to the "1" level (here, vDD).
become.

At time tsz, when the input signal φIN becomes "O" level, the coupling of the capacitor CS+ causes the node N31 to
becomes a negative potential, the voltage nMO8TQH turns on, and the capacitor C3
Charge flows from 2 to capacitor C31, and node N31 becomes OV
Become TN. Therefore, node N32 is VDD IVrp
l or less (DV level fxKj pMO8TQs< is turned on. However, pMO8TQss is off) - cut signal φ
C is turned off because it is at ``1'' level, and pM is removed from the power supply VDD.
O8T Q10 + Qss and nMOS T Qse
.

The on-on current (2) does not flow to the ground potential via Qu.

nM OS T Qsa is output signal φOUT is ゝゝl
“Turn it on because it is at - level, node N34 is ゝゝ0.”
maintain the level.

At time t3B, the input signal φIN changes from the "0" level to 11
", the power cut signal φC is at the "0" level for a short period of time. In this case, the power supply VDD is
T Qs4r Qss and n M OS T Qss,
An on-on current ■ flows to the ground potential through Q37, but the current capacity of nMOSTQ36 and Q87 is sufficiently large compared to the current capacity of pMOSTQ34 and Qas, so the node N5aB'0'' level is maintained. .

At time ta4, when the input signal φXN goes to the "0" level, the node Nj2 goes to the level below "TN", fz9, nM08.
'J'Qsr turns off.

At time tss, the cut signal φ is turned on. 755 temporarily becomes ゝゝO“ level p MOS T Qss f
i", node hh4 becomes pMO8TQs4.Qa
It is charged through s. p M OS T Q34 +
Since the current capacity of Qss is low, it takes time 75E d-#≧ for the potential of node N34 to rise.

However, when the potential of node N34 exceeds VTN, NAND
The output signal G of circuit 2 becomes 10" level, and PMO8T
Q311 turns on and nMO8TQ,6 turns off. Therefore, the node N34 is charged through the pMOS T Qa@, which has a higher current capacity than the pMOS T Q10 and Qss, and reaches the VDD level more quickly.

At time 136, the reset signal φ8 goes to the 00" level and p
M 08 T QJt turns on and output signal 6 becomes '1''
become the level.

As explained above, since the on-on current of the timer circuit used in this embodiment flows only during the period when the M No. φC cloth is at the 0 level, the average operating current of the timer circuit is It has the effect of being able to reduce the amount of

Although the above explanation has been made regarding MOS transistors, it goes without saying that the present invention can be applied to other insulated gate field effect transistors.

〔Effect of the invention〕

As described above in detail, the pseudo-static memory of the present invention has a timer circuit having the above configuration, so that the power cut signal is temporarily suppressed during the period in which an on-on current flows in a conventional timer circuit. Since the on-on current flows only during a short period when it is at the "0" level, it has the effect that the average operating current of the timer circuit can be reduced.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a timer circuit used in an example of a conventional pseudo-static memory, FIG. 2 is an operation timing diagram thereof, FIG. 3 is a circuit diagram of a type circuit used in an embodiment of the present invention, and FIG. The figure is an operation timing diagram. 1...CMOS inverter circuit, 2...
・0MO8-NAND circuit 1Qr r Q4 + C3
1+ Qaa + Qss +Q3G + C41...
... p channel MO8) transistor, Q21Q31
Q51Q321Q331Q361Q371Q401Q4
□・・・・・・n channel MO8) transistor, NI+
N 2 + N 31-N86...Node, C1
, C2, C3□. C32... Capacitor, φIN lφ2, φ
. , φ8...signal, VDD...power supply,
■・・・°On-on current・Fig. 1 Fig. 2

Claims (2)

[Claims] (1) - The drain and gate of a first field effect transistor of conductivity type are connected to a first node, and the source is connected to a first power supply, and one of the first capacitors is connected to a first input signal and the other is connected to the first node. a drain of a second field effect transistor of - conductivity type is connected to the second node, a gate is connected to the first power supply, a source is connected to the first node, and a second field effect transistor of opposite conductivity type is connected to the first node; The drain of a third field effect transistor is connected to the second node, the gate is connected to the second input signal, and the source is connected to the second power supply, and one of the second capacitors is connected to the second node, the other is connected to the second node. A fourth field effect transistor of opposite conductivity type is connected to the first power source, a source thereof is connected to the second power source, and a drain of a fifth field effect transistor of opposite conductivity type is connected to the fourth node. The gate is connected to the third input signal, the source is connected to the third node, and the drain of the sixth field effect transistor of -conductivity type is connected to the fourth node, and the gate is connected to the output signal and the source is connected to the fifth node. A seventh field effect transistor of negative conductivity type has its drain connected to the fifth node, its gate connected to the second node, and its source connected to the first power supply, and an eighth field effect transistor of opposite conductivity type connected to The drain of a ninth field effect transistor of opposite conductivity type is connected to the fourth node, the gate is connected to the output signal, and the source is connected to the second power supply, and the drain of a ninth field effect transistor of the opposite conductivity type is connected to the output signal, and the gate is connected to the output signal. A source is connected to the fourth node to the second power source, a drain t'' of a first O field effect transistor of -conductivity type, a gate is connected to the sixth node, and a source is connected to the fourth node. the gate is connected to the second output signal of the opposite conductivity type, and the source is connected to the fourth input signal of the opposite conductivity type.
a timer circuit, the drain of a twelfth field effect transistor of - conductivity type being connected to the output signal, the gate being connected to the fourth input signal, and the source being connected to the sixth node; Pseudo-static memory characterized by (2) Fourth. The current capacity of the fifth field effect transistor is the same as that of the sixth field effect transistor. 7th. The current capacity of the eighth field effect transistor is sufficiently large, and the current capacity of the cascade-connected first O2 and twelfth field effect transistors is provided sufficiently large relative to the current capacity of the ninth field effect transistor. A pseudo-static memory according to claim (1).