JPS6062830A - Synchronization controller of plural parallel operation inverters - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a synchronous control device for parallel synchronous operation of a plurality of inverters.

[Technical background of the invention and its problems]

In uninterruptible power supplies that use inverters, a parallel operation system of multiple inverters is often used to improve the reliability of the system.

In such a system, it is necessary that the output phases of each inverter match both at startup and during operation.

FIG. 1 shows the synchronous side device of a conventional multiple inverter operating in parallel. In FIG. 1, l is a reference oscillator common to each inverter. The reference oscillator l is an excavator 11,
The output pulse train of the reference oscillator l (composed of a pulse generator circuit 12 and an OR circuit 13 that generates a synchronizing pulse with a wide width that produces double pulses). Next (210, 20,...M
O is inverter No. 1, not shown.

This figure shows the gate control circuits of the No. 2 unit, . 10
1 is a pulse width detection circuit that detects a wide synchronization pulse included in the output pulse train of the reference oscillator l, and 102 is the output of the pulse width detection circuit 101 (2) which generates a phase matching signal at startup and during operation. A phase matching circuit 103 is an N-adjustable counter (N is the inverter type) which is applied as a reset command to the output of the phase matching circuit 102 and generates an inverter gate signal using the output of the reference oscillator 1 as a clock input. , depending on the number of phases).

The phase matching circuit 102 in FIG. 1 is configured, for example, as shown in FIG.
The output of the flip-flop 1028% pulse width detection circuit 101 with the output of 02 A as the set input and the stop command as the reset input is inverted by the NOT circuit 102C, and the signal is ANDed with the output of the flip-flop 102B. It is composed of an AND circuit 102D and an OR circuit 102E that calculates the logical sum of the inverted output of the flip-flop 102B and the output of the AND circuit 102D. FIG. 3 is a time chart showing the operation of the device shown in FIG. 1 when the number of stages N of the ring counter 103 is six.

The operation of the device shown in Fig. 1 is shown in Japanese Utility Model Publication No. 56-11595. At startup (2), the ring counter 103 starts from the output pulse train of the reference oscillator l (2) from the pulse next to the synchronizing pulse included in the reference oscillator l. Start counting pulses, and reset the ring counter 103 every cycle or every few cycles during operation (at the timing when two synchronous pulses occur) (from the second point, the output phase of the inverter at startup or during operation Therefore, each inverter is exactly the same even if there are two units below the unit 2, and each inverter is controlled by the synchronization included in the output pulse train of the reference oscillator l. It is operated in synchronization with pulses, and the output phase of each inverter matches.

However, in the synchronous control device as shown in Fig. 1, if an erroneous signal such as noise is applied to the control cable connecting the output of the reference oscillator 1 and the gate control circuit of each inverter, the synchronous control device as shown in FIG. may be detected as a wide synchronous pulse as shown by the broken line (2) in Figure 3.Especially, as the number of parallel operating units increases, the distance between the reference oscillator and the i1j1 circuit of each inverter increases. Therefore, noise superimposed on the control cable becomes a problem. If such an erroneous signal is detected as a synchronization pulse, the ring counter 103 will be reset at irregular timing, and the inverter's output voltage and phase will change significantly (=suddenly), which may adversely affect the load (not shown) or cause the inverter's This may cause DC bias or transient phenomena in the transformer connected to output C2 or the AC filter for waveform improvement.

If the gate signal of the inverter changes at irregular timing, C: In the worst case, the inverter will trip and stop due to commutation failure.

[Purpose of the invention]

The purpose of the present invention is to achieve the above-mentioned points (in view of the above).

In the synchronous control system for multiple inverters operating in parallel using the output pulse of a common reference oscillator as a reference signal, control cable C connects the reference oscillator and the control device of each inverter; To provide a synchronous control device for a plurality of inverters running in parallel, which is stable and reliable and does not cause a large sudden change in the output of the inverter or cause the inverter to trip and stop. In order to achieve this object, the present invention uses a common bus that connects the outputs of each inverter without superimposing synchronizing pulses for matching the output phases of each inverter. Based on the voltage phase (2), a phasing signal is generated during startup and operation of each inverter (2).

[Embodiments of the invention]

Embodiments of the present invention will be described below with reference to FIG. In Fig. 4, numeral 41 is a common oscillator, but its configuration is not a circuit that superimposes a wide synchronizing pulse on the output pulse train, like the reference oscillator 1 in Fig. 1, but it is a so-called rate oscillator. . 14, 24, . . . M4 is an inverter, 15, 25, . . . M5 is an AC filter for shaping each inverter output into a sine wave 62, 16, 26
, . . . M6 is a breaker for turning on and off the parallel operation of each inverter, and 42 is a common bus that connects the outputs of each inverter. The internal configurations of the gate control circuits 10 , 20 , . A phase matching circuit 143 that responds to generate a phase matching signal at startup and during operation of each inverter is initialized (reset) by the output of the phase matching circuit 142, and the reference oscillator 4
This is an N-advance counter (which has the same function as 103 in FIG. 1, but operates at the falling edge of the clock pulse) that generates an inverter gate signal using the output of 1 as a clock pulse.

A concrete sequence of the phase matching circuit 142 is shown in FIG. A monostable multivibrator 142B with a trigger input, an AND circuit 142C that takes the logical product of the output of the monostable multivibrator 142B and the start command, and an AND circuit 14
2 Manually set output of C, flip-flop 142D with stop command as reset input, output of monostable multivibrator 142 B and flip-flop 142
AND circuit 1421ii that takes a logical product with the output of D, the output of the AND circuit 142B, and the flip-flop 142
It is composed of an OR circuit 142F that performs a logical sum with the inverted output of D. In addition.

Counter 142A1m, C so that P=N/2
:It is configured.

Next (=The operation of the synchronous control device configured as described above will be explained. FIG. 6 is a time chart showing the operation of the synchronous control device of FIG. 4. ).

First, the operation at startup (two will be explained).If we consider the device 1-1M unit to be started first, the 1M unit will be started at an arbitrary timing (before startup, no voltage appears on the common bus 42, so The phase detection circuit M41 does not operate, and the flip-flop M42D is set (= becomes) at an arbitrary timing.After that, when the breaker M6 of the M unit is turned on, the AC filter M5 ( A two-way shaped sinusoidal voltage appears (FIG. 6(B)).

The phase of the voltage that appears on this common bus 42 (: is determined by the N-advanced counter M43 of the M unit which operates using the output of the reference oscillator 41 as a clock pulse, as shown in FIG. 6; the output of the two single oscillators 41 To explain the operation when starting unit 1 in this state, the phase detection circuit 141 generates a detection signal at timing t when the voltage of the common bus 42 changes from positive to negative. 6th
Figure (C)), the phase matching circuit 142 responds to the output of the phase detection circuit 141 (2), and counts the output pulse of the common oscillator l P times (if N=6, P=3) (reset command of 143). 6 (D)), and the N-advancing counter 143 starts operating from time t3 (Fig. 6 (E)).
l), the M unit is activated. At time t, reference oscillator 4
It coincides with the falling timing of output pulse 1,
The inverter 14 of Unit 1 will be activated so that it has the same phase as the voltage of the common bus 42. After that, if the circuit breaker 16 is turned on, Unit M and Unit 1 will operate in parallel. .

Next, to explain the phase matching operation during operation, the phase detection circuit 141 generates a detection signal at the timing when the voltage of the common bus 42 changes from positive to negative (2) every cycle.
When this detection signal (temporarily operates and the phase matching circuit 142 counts the output pulse of the common oscillator twice (operates at the rising edge)), it supplies the phase matching pulse to the N-advancing counter 143 (Fig. 6 (D' )).

The N-advance counter 143 is initialized (reset) by this phase matching pulse (2), but is reset at the rising timing (time 1) of the output pulse of the two-unit single oscillator 41 (as in the case of startup described above). and falls (Fig. 6 (
B') ). That is, in the unlikely event that the N-advance counter 14
3 is miscounted due to an erroneous signal C2 such as noise, the above operation (2) corrects the output phase of the inverter 14 to match the voltage phase C2 of the common bus 42 (-).

Note that when a load is connected to the common bus 42, the voltage phase of each inverter and the common bus 41 will be shifted from each other due to the operation C2 of the AC filter (for example, the M unit that started up the When operating with two loads, the voltage phase of the common bus 42 is delayed as shown by the broken line in FIG. 6 (I3). In this case, the phase detection circuit 141 generates a detection signal as shown in the broken line in FIG. 6 (C). Usually, the voltage phase shift is short compared to the period of the output pulse of the reference oscillator 41 (in the embodiment shown in FIG. 4, N=6 and the period of the output pulse of the reference oscillator 41 is 60'afi in electrical angle). Phase matching at startup and during operation is performed by operations similar to those described above.

In this way, N in the gate control circuit of each inverter is
By aligning the operating timing of the advancing counter with the voltage phase 1 of the common bus, each inverter can be synchronously controlled without superimposing a synchronizing pulse on the output of the reference oscillator as in the conventional case. Since the level of noise superimposed on the common bus is low compared to the level of the main circuit, the so-called S/N ratio is high. Therefore, noise superimposed on the control cables that connect the reference oscillator and the gate control circuit of each inverter, as in conventional control devices (Secondly, it is extremely unlikely that the inverter will malfunction and trip and stop). .

In addition, since there is no need to superimpose a synchronous pulse on the output of the reference oscillator, it is a simple circuit configuration that simply generates a pulse train, and this reduces the reliability of the reference oscillator as well as the reliability of the entire parallel operation system. will improve.

The embodiments of the present invention have been described above. In the above embodiments, the phase matching circuit 142 gives the phase matching signal to the N advancing counter every cycle, but it may be given every few cycles or every fixed period of time. You can also do this.

In addition, in explanation C2 of the above embodiment, the reference oscillator 41
does not include the control circuit of each inverter and is installed independently, but it is configured with a standby redundant system in which an oscillator is installed in the control circuit of each inverter and any one of them is selected and operated. You may.

〔Effect of the invention〕

As described above, the present invention (according to 2) is a synchronous control device for a plurality of parallel operating inverters that controls the output phase of each inverter using the output pulse of a common reference oscillator as a reference signal (according to 2) It is possible to provide a synchronized control device for a plurality of parallel operating inverters that is not affected by noise or the like that affects the output pulse train and has a simple configuration as a reference oscillator and is stable and highly reliable.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing an example of a conventional synchronous control device for multiple inverters running in parallel, Fig. 2 is a circuit diagram showing a specific example of the configuration of the phase matching circuit of the device shown in Fig. 4 is a block diagram showing the main circuit configuration of a plurality of parallel operating inverters and an embodiment of the synchronous control device according to the present invention C2, and FIG. 5 is a time chart showing the operation of the device.
FIG. 6 is a circuit diagram showing a specific example of the configuration of the phase matching circuit in the embodiment shown in the figure, and FIG. 6 is a time chart showing the operation of the embodiment shown in FIG. 41... Reference oscillator, 14.24-M4... Inverter, -01... Phase detection circuit, 142... Phase matching circuit, 143... N-adary counting counter. (7317) Representative Patent Attorney Kensuke Norichika (and 1 other person) 1st
Figure //') Figure 2 Figure 3 Link counter 7103 ' 0° False) Currer ``Complete call--!-''

Claims (2)

[Claims] (1) Synchronous control device 1 for a plurality of inverters operating in parallel, which controls the output phase of each inverter using the output pulse of a common reference oscillator as a reference signal. a phase detection circuit that detects the voltage phase of a common bus that combines the outputs of each inverter, and an output signal of the phase detection circuit ≦;
a phase matching circuit that responsively generates a phase matching signal during startup and operation of the inverter; and an N-adjustable clock that is initialized by the output signal of the phase matching circuit and operates using the output pulse of the reference oscillator as a clock pulse. A synchronous control device for multiple inverters running in parallel, consisting of a counter. (2) The phase matching circuit has a counter that starts counting the output pulses of the reference oscillator based on the output signal of the phase detection circuit, a set input for the second count output of the counter, and a reset input such as a stop command. 2. A synchronous control device for a plurality of inverters operating in parallel as claimed in claim 1, which is constructed of flip-flops and is C2 such that P=N/2.