JPS6062730A - Data input device - Google Patents

Abstract

PURPOSE:To input a data with the same number of times as the number of digits of the data desired to be inputted by discriminating the number of digits of the data inputted depending on the content of the most significant digit. CONSTITUTION:When one of key switches KS0-KS9 is depressed and the count value of a binary counter 6 reaches ''1'', a coincidence (a) signal is outputted from a coincidence detecting circuit 11, a latch circuit 15 is set, and a data representing a numeral 4 stored in a 4-bit register 18 is outputted selectively. Thus, the number of digits of the data generated through the operation of a ten-key 1 is 4-digit, then a coincidence signal (c) is outputted from a coincidence detecting circuit 20. On the other hand, when a numeral other than ''1'' is inputted by the first depressing operation, the coincidence signal (a) is not outputted and the data respresenting the numeral 3 stored in a register 17 is outputted. Thus, when 3-digit is inputted in this case, the coincidence signal (c) is outputted.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data input device for inputting data into equipment, and more particularly to a device for inputting data indicating reception frequencies into a receiver.

The reception frequency is set using the numeric keypad, which includes 10 key switches each corresponding to a decimal number from 0 to 9, and which generates data indicating the corresponding numerical value by pressing these 10 key switches. A conventional data input device used for inputting data generated by key operations on a numeric keypad in such a receiver is shown in FIG. In FIG. 1, one end of the key switch KS o =KS9 in the numeric keypad 1 is grounded. When these key switches KSo to KSQ are pressed, a low level signal corresponding to the data generated by key operations on the numeric keypad 1 is generated at the other ends of the key switches KSo to KS9. The data indicated by the low level signals generated at the other ends of these key switches KSo to KS9 is supplied to the data input device 2 as output data of the numeric keypad 1. In the data input device 2, output data from the numeric keypad 1 is supplied to an encoder 3 and an OR (logical sum) circuit 4. The encoder 3 corresponds to the pressed key switch when the output data of the numeric keypad 1 is supplied, and
(Binary Coded Decimal) It is configured to output encoded data. The output data of the encoder 3 is supplied to the register 5. Also, O
The R circuit 4 is configured to generate a pulse when a low level signal indicating output data of the numeric keypad 1 is generated.

The multiple pulses output from the OR circuit 4 are supplied to each clock input terminal of the register 5 and the binary counter 6. The register 5 is formed by four 4-bit shift registers whose serial input terminals are supplied with signals respectively corresponding to bits 2° to 23 forming the output data of the encoder 3. The four 4-bit shift registers in the register 5 are supplied with multiple pulses output from the OR circuit 4 as shift clocks. The corresponding parallel outputs of these four 4-bit shift registers form 4-digit BCD-encoded data, which is stored in the RAM.
(Randum Access Memory) 7. At the write command input terminal of the RAM 7 and the clear input terminal of the register 5, there is a signal corresponding to the third bit 22 counting from the least significant bit among the bits forming output data indicating the count value of the binary counter 6, that is, the binary counter 6. A signal that becomes high level when the count value of 4 reaches 4 is supplied. The signal corresponding to this bit 22 is also supplied to the clear input terminal of the binary counter 6.

The data outputted from the RAM 7 is sent to a PLL control circuit 8 consisting of a programmable frequency divider, etc. for variable control of the frequency of the local oscillation signal in a PLL (phase locked loop) circuit that generates the local oscillation signal, and a reception circuit. The signal is supplied as input data to a display circuit 9 that displays the frequency.

In the above configuration, when the key switch KS o = KS9 in the numeric keypad 1 is suppressed, the OR circuit 4 outputs a pulse, the data is shifted by one digit in the register 5, and then the output data of the encoder 3 becomes the least significant digit. is stored to form.

At the same time, the binary counter 6 counts up. When the count value of the binary counter 6 reaches 4, the output signal corresponding to bit 22 goes high to 5-bell, and the count value of the binary counter 6 is cleared and returns to zero. Therefore, bit 2 of binary counter 6
The output signal corresponding to 2 is the signal propagation time (propagation delay
It becomes a positive pulse with an extremely short time width corresponding to me). When this positive pulse occurs, that is, at the rising edge, RA
A write command is issued to M7, and the 4-digit BCD encoded data temporarily stored in register 5 is written.

Thereafter, the contents of the register 5 are cleared when the positive pulse disappears, that is, when the pulse falls.

By the above operation, key switch KS of numeric keypad 1 is
By pressing o = KS 9 four times in sequence from the key switch corresponding to the most significant digit of the data indicating the receiving frequency, the four-digit data generated one digit at a time starting from the most significant digit is temporarily stored in register 5. All digits are written into the RAM 7 at the same time, and the data is input to each part of the device such as the PLL control circuit 8 and the display circuit 9.

In a receiver using the conventional data input device as described above, when the reception frequency is 3 digits, the key switches KSo to KS9 of numeric keypad 1 are set to 4 in the same way as when the reception frequency is 4 digits.
The reception frequency could not be set unless the button was pressed twice, resulting in poor operability. That is, for example, the frequency of TBS station (954k
Hz) as the reception frequency, it was necessary to sequentially press four key switches corresponding to the numerical values 0.9 and 5.4 among the key switches KSo=KS9.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a data input device that allows data to be input into a device by manually operating keys the same number of times as the number of digits of data to be input.

The input data supply device according to the present invention includes a storage means for sequentially storing generated data numbers one digit at a time, and selectively selecting one of two different numerical values depending on the numerical value forming the most significant digit of the generated data. The data includes a reference value generating means for generating a reference value and a counting means for counting the number of digits of the generated data, and the data is stored in the storage means when the reference value and the count value of the counting means match. The structure is such that all digits are output simultaneously as input data, and data whose number of digits can be specified by the content of the most significant digit can be inputted by manual key operations the same number of times as the number of digits.

Hereinafter, embodiments of the present invention will be described in detail with reference to FIG.

As shown in FIG. 2, in the data input device 2 according to the present invention, an encoder 3, an OR circuit 4, a register 5, a binary counter 6, and a RAM 7 are connected in the same way as in the device shown in FIG. However, the data input device 2 according to the invention
, the output data of encoder 3 is sent to gate circuit 1
0 is also supplied. The gate circuit 10 has a -number configuration circuit 1
The output data of the encoder 3 is supplied to the coincidence detection circuit 12 in response to the supply of the one-number output signal α output from the encoder 1. - The number calculation circuit 11 is supplied with data indicating the count value of the binary counter 6 as counting means and data stored in the 4-bit register 13. In the 4-bit register 13, 4-bit BCD-encoded data indicating the numerical value 1 is stored in advance.

The negative number output circuit 11 is configured to output a one number output signal .alpha. when the data indicating the count value of the binary counter 6 and the data stored in the 4-bit register 13 match. Further, the data stored in the 4-bit register 14 is also supplied to the minus number configuration circuit 12. The 4-bit register 14 stores in advance 4-bit BCD encoded data indicating the numerical value 1. −
The output circuit 12 compares the output data of the encoder 3 supplied from the gate circuit 10 with the data stored in the 4-bit register 14, and outputs a match detection signal when the two data match. The structure is as follows.

The coincidence detection signal R- outputted from the coincidence detection circuit 12
The signal is supplied to the set input terminal of the latch circuit 15 such as an S flip-flop, and the occurrence of the coincidence detection signal S is stored in the latch circuit 15. For example, Q of this latch circuit 15
The output is supplied to a reference value generation circuit 16. In the reference value generation circuit 16, the output of the latch circuit 15 is supplied to the control input terminal of the changeover switch circuit 17. The data stored in the 4-bit register 18 is supplied to one input terminal of the changeover switch circuit 17, and the data stored in the 4-bit register 19 is supplied to the other input terminal of the changeover switch circuit 17.
The data stored in is being supplied. The 4-bit registers 18 and 19 contain B indicating numbers 3 and 4, respectively.
CD-encoded 4-bit data is stored in advance. The changeover switch circuit 17 selectively outputs the data supplied to one input terminal when, for example, a low level signal is supplied to the control input terminal, and outputs the data supplied to the other input terminal selectively when, for example, a high level signal is supplied to the control input terminal. It is configured to selectively output data supplied to the input terminal. The output data of this changeover switch circuit 17 is transmitted to the reference value generation circuit 16.
is supplied to the coincidence detection circuit 20 as an output. - The number calculation circuit 20 is also supplied with data indicating the count value of the binary counter 6. - The number output circuit 20 is configured to output a coincidence detection signal C consisting of a high level signal when the output data of the changeover switch circuit 17 and the data indicating the count value of the binary counter 6 match. The coincidence detection signal G output from the minus number output circuit 20 is transmitted to the clear input terminal of the binary counter 6, the clear input terminal of the latch circuit 15, the clear input terminal of the register 5, and the RAM 7.
is supplied to the write command input terminal.

In the above configuration, the key switch KS o = KS
When one of 9 is pressed and the count value of the binary counter 6 becomes 1, the coincidence detection circuit 11 outputs the coincidence detection signal α.
is output. Then, the output data of the p-encoder 3 is outputted from the gate circuit 10 and supplied to the coincidence detection circuit 12. At this time, if the output data of the encoder 3 corresponds to the numerical value 1, the coincidence detection circuit 12 outputs a coincidence detection signal S, and the latch circuit 15 enters the set state. Then, a high level signal from the latch circuit 15 is supplied to the control input terminal of the changeover switch circuit 170, and the changeover switch circuit 17 selectively outputs the data stored in the 4-bit register 18, that is, the data indicating the numerical value 4. Ru. Since this data indicating the numerical value 4 is supplied to the coincidence detection circuit 20, a coincidence is detected when the count value of the binary counter 6 reaches 4, that is, when the number of digits of the data generated by the operation of the numeric keypad 1 reaches 4 digits. The circuit 20 outputs a signal C consisting of a high level signal. Since this minus number output signal C is supplied to the clear input terminal of the binary counter 6, the count value of the binary counter 6 is cleared and returns to 0 when the minus number output signal C is generated. Then, the -number output signal C disappears, so the -number output signal C
is a signal that exists only in an extremely short period of time corresponding to the signal transmission time on the binary counter 6 and -number output circuit side. When this minus number output signal C is generated, a write command is issued to the RAM 7 when the minus number output signal C rises, that is, when the one number output signal C is generated, and the 4-digit data is stored in the register 5. is written into RAM7 at the same time.

At the same time, the latch circuit 15 is cleared. Thereafter, the contents of the register 5 are cleared when the minus number output signal C falls, that is, when the one number output signal C disappears.

Next, if a value other than 1 is generated as the most significant digit of the data indicating the reception frequency by the first suppression operation of the key switch KSo = KS9, the output signal α is not output and the latch circuit 15 remains in the reset state. Then, a low level signal from the latch circuit 15 is supplied to the control input terminal of the changeover switch circuit 170, and the changeover switch circuit 16 outputs the data stored in the 4-bit register 17, that is, the data expressed in BCD code and numerical value. Data indicating 3 is output. Therefore, in this case, when the number of digits of data generated by the operation of the numeric keypad 1 reaches three digits, the one number output signal C is output. Then,
The three-digit data stored in the register 5 is written into the RAM 7 at the same time by this minus number output signal C. Thereafter, when the minus number output signal C disappears, the contents of the register 5 are cleared.

By the above operation, the key switch KS o = K
The number of digits of this data is determined by the content of the most significant digit of the data indicating the reception frequency generated by the first suppression operation in S9. If it is other than 1, it is determined that the number of digits is three, and when data corresponding to the determined number of digits is generated, the data is input to the PLL control circuit 8 or the like.

In addition, in the above example, A
We have explained the case where the reception frequency can be displayed in 4 digits, such as an M/FM receiver.
If it is displayed in digits (25 kHz steps), the number of digits in the register 5 etc. may be changed.

Above, we have explained the case where data indicating the receiving frequency is input into the receiver.1 For example, there may be variations in the dimensions of a predetermined part of a molded product, such that the value is within the range of several H to over 10 W. When performing a correlation analysis to investigate the cause of this variation, data that can be used to identify the number of digits based on the content of the most significant digit, such as data indicating the dimensions of the specified part, is transferred to a device other than the receiver such as an arithmetic device. The present invention can also be applied when inputting information to a device.

As described in detail above, the data input device 12- according to the present invention is capable of determining the number of digits of input data according to the content of the most significant digit.
The system is configured to output all digits of data at the same time when the determined number of digits of data is generated, so you can input data by pressing the keys the same number of times as the number of digits of data you want to input. This makes it possible to improve the operability of the equipment.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a conventional data input device, and FIG. 2 is a block diagram showing an embodiment of the present invention. Explanation of symbols of main parts l...Numeric keypad 3...Encoder 4...OR circuit 5...Register 6...Binary counter 7...RAM 10...Gate circuit 11.12.2
0...-number configuration circuit

Claims (1)

[Claims] A data input device for inputting all digits of data to a device simultaneously, which are generated one by one starting from the most significant digit and whose number of digits can be specified based on the content of the most significant digit, and the data is input one by one from the most significant digit. a storage means for storing digit by digit; a reference value generating means for selectively generating one of two different numerical values as a reference value according to the content of the most significant digit;
The data includes a counting means for counting the number of digits of the data, and when the reference value and the count value of the counting means match, the data stored in the storage means is outputted simultaneously for all digits. input device.