JPS6062243A - Digital data expanding circuit - Google Patents

Abstract

PURPOSE:To expand compressed data easily by providing a shift register for reading transmitted compressed data and a counter in which transmitted range information is preset, and stopping reading operation when the counted value attains to a specific value. CONSTITUTION:The N-bit shift register 1 for reading the transmitted compressed data and the counter 2 in which the transmitted range information is preset are provided. Then, a specific number of the MSBs of the compressed data are fetched in the register 1 from the low-order digits, and the range information is preset in the counter 2. In this state, the compressed data is read in the register 1 successively and the counter 2 counts up from the preset value in response to the reading operation. When the counted value attains to the speciffic value, the reading operation of the register 1 is stopped and original binary code which is expanded to N bits is obtained from the register 1.

Description

[Detailed Description of the Invention] (a) Industrial Application Field The present invention is based on the invention, in which instantaneous compression (or quasi-instantaneous compression) is performed to reduce the bit transfer rate when PCM modulating an audio signal (analog signal). The compressed sample data is recorded on a magnetic tape or disk, or transmitted through a transmission medium such as radio waves, and the compressed sample data is reproduced, and the original PCM modulation is reproduced from the compressed sample data. This relates to a circuit method for decompressing sample data.

(B) Background of the Invention The principle of PCM will be briefly explained using FIG. 1. The audio signal (analog signal) is sampled at a fixed time interval T8, and the sampling signal is converted into an N (quantization bit number) bit binary signal by an A/D converter according to its level value as shown in FIG. converted to code. At each sampling point, the sample data converted to an N-bit binary code is compressed as necessary to reduce the bit transfer rate. Figure 6 shows, as an example, the method adopted in the audio intrusion method for television satellite broadcasting.
A method for compressing sample data with a quantization bit count of 14 bits into 10 bits and 5 ranges will be described. FIG. 6 shows a method for compressing sample data linearly compressed using a quantization bit count of 14 bits to 10 bits. If the MSB (most significant bit) of the 14 bits of one sample data is considered as a code representing the positive or page level, the remaining 16 bits represent the absolute value level. This absolute value level is divided into five ranges from 29 to 2 as shown in Figure 3, and each range is given a range number. At this time, if the original 14-bit sample data is a binary code expressed as a 2IS combination, the method for compressing it to 10 bits is to determine the 6-bit range bit according to the input level, as shown in Figure 3. Then, the upper 9 bits of the sample data are taken out, and 1 bit of the original MSB representing a positive or negative level is added to the beginning of the data. FIG. 4 shows an example of compressing 14-bit sample data to 10 bits. The data is a 2'S combination. In the example in Figure 4, the original sample data has bit information representing the absolute value level below the 6th bit counting from the MSB, so from Figure 6 the range number is 1 and the range bit is (001 ). In the example, the sample data compressed to 10 bits is counted from the MSB and the 12th bit and below are truncated. The compression method adopted for television satellite broadcasting is a quasi-instantaneous compression method, in which one range bit information is transmitted for a plurality of sample data. Therefore, in the quasi-instantaneous compression method, the range bit information is determined to be the highest level range bit among a plurality of sample data.

A compression operation is performed using the determined range bits. On the other hand, in the instant compression method, range bit information is added to one sample data, so in the example shown in Figure 4, the original 14-bit sample data is compressed to 13 bits. Become.

(c) Purpose of the Invention An object of the present invention is to construct a circuit for expanding compressed and transmitted data to the original number of bits using a relatively simple circuit.

2) Composition of the Invention In the data expressed by an N-bit binary code (2's combination), the MSB of this binary code is placed first, followed by the absolute value level of the binary code. By extracting (M-1) bits consecutively from the first bit of the represented bits and adding them, compressed data of JM bits is obtained, and range information bits corresponding to the absolute value level are obtained. When the information obtained in this manner is transmitted, the present invention is configured as follows when decompressing it to the original N-bit binary code based on the compressed data and range information.

An N-bit shift register for storing the transmitted compressed data and a counter to which the transmitted range information is preset are provided. The range information is preset, and then the compressed data bits are sequentially read into the shift register, and a counter is incremented in response to this read operation. When the counter counts up to a predetermined value, the read operation of the shift register is stopped, and the read operation of the shift register is stopped. The structure is such that the original binary code expanded to fiN bits is obtained from the shift register.

(e) Example 1 A case will be described in which 4-bit data is compressed to 10 bits and the range information is 5 ranges (5 bits) as shown in FIG. For example, the original 14-bit data (FIG. 4a) is compressed into 10-bit data and transmitted as shown in FIG. 4o1c. In this case, range number 1
-+, '1', range bit is 'oO-i'.

Now, the transmitted compressed data is shown in Figure 5 (a).
shall be.

In this case, the range number of this data is ・0・(
Therefore, if the range bit is 10001), Figure 5 (+
It is sufficient to obtain 14-bit data expanded as shown in 1). At this point, the lower three bits of blank space may be filled with 111 or 0# in order to match the data length. As a result, the lower 6 bits cannot necessarily be restored to their original state, but because they are lower bits, there is no large error.

The range number is %11 (range bit is 10011)"
In this case, it is sufficient to obtain expanded data as shown in FIG. 5(C). At this time, in the blank space between MSB and B2,
Although it is sufficient to insert a bit that does not represent information representing the absolute value level, in the case of 2/S combination data, this bit is the same bit as the MSB (see Figure 4, A and B).

Thereafter, in the same manner, if the range number is 4'' (range bit is .100'), it is sufficient to obtain expanded data as shown in FIG.

Such data expansion can be realized by the circuit shown in FIG. Compressed data (FIG. 7C) is taken into the 14-bit shift register (1).

A clock (FIG. 7b) synchronized with the compressed data (e) is applied to the counter (2) and counted. The flip-flop (3) is connected to the first data gate signal (seventh
This is for creating (Fig. d).

First, when a load signal (negative pulse shown in FIG. 7a) is generated, the 7 lip-flop (3) is set and its Q output becomes H level. This Q output becomes a first data gate signal (d) and is applied to the input sides of AND gates (4) and (5). On the other hand, 10-bit compressed data <
The second data gate signal (Fig. 87e) has the same width as c).
) is applied to the input side of the AND gate (4). Therefore, AND gates (4) and (5) are both in the driving state, compressed data (e) passes through this AND gate [4) and is applied to the shift register (1), and the clock (b) is applied to the shift register (1). ) passes through the AND gate (5 ratios and enters the shift register (
1) and counter (2). counter(
When 2) counts '14', its output is applied via the inverter (6) to the flip-flop (3) to reset it.

Now, the load signal (a) is also applied to the shift register (1) and counter (2). This load signal (a) causes the shift register (1) to take in four bits of the MSB of the compressed data (e) from the lower order. That is, all of the lower 4 bits are taken in so that they become the same code (111 or 501) as the MSB of the compressed data (C). On the other hand, a range bit is preset in the counter (2). For example, if compressed data (e) is necessarily the data shown in Figure 4 (a), the range number of this data is 11.
', and therefore its range bit (ool) is preset in the counter (2), which takes this value 1
1# starts counting.

Now, in this state, in synchronization with the start-up of the cycle (in progress),
The 10 bits below the MSB of the compressed data (C) are sequentially taken into the shift register (1), and this clock (b
) is counted by a counter (2). When all 10-bit compressed data (C) is taken into the shift register (1) [at this time, the value of counter f21 becomes 11 bits (1
+10)], and thereafter the second data gate signal (e
) is at the L level, so the AND gate (4) is closed. However, during the clock), the counter (2) is '14'.
Since it is applied to the shift register (1) until r is counted, the remaining 96 bits are '0! is the shift register (
After that, the flip-flop (3) is reset, the first data gate signal (d) becomes level, and one cycle ends. In this way, the contents of the shift register (1) become as shown in FIG. 5(c) in this example. In other words, it has been expanded to the original 14-bit data (of course, the lower 6 bits of the expanded 14-bit data are not necessarily the same as mentioned above).
.

When decompressing data with a range number of 14#, '1oo', that is, the value 141, is first preset in the counter (2), and from this value 1141 is counted until - (
In other words, the shift register (1) is driven, so when the compressed data (e) of 10 bits below the MSB is just read, the shift register (1) is stopped.At this time, It is clear from the previous explanation that the contents of the shift register (1) will be in the state shown in Figure 1M5 (see Figure 5).
The blank part contains the same code as the MSB.

The above explanation is based on the load signal, MSB for 4 bits.
It rarely happened when I imported 10-bit compressed data after importing the data, but even if I first import 5-bit IW and SB and then import 9-bit compressed data excluding the MSB, the same problem occurs. Kotoderoru. However, in this case, the counter (2
) counts 1161, Flip 70 Tsubu (3
) will be reset.

In addition, in the case of the instantaneous compression method, the range bit corresponding to each piece of compressed data is preset to color (2), but in the case of the quasi-instantaneous compression method, the range bit corresponding to that data is preset to color (2). The same range bits will be preset.

(f) Effects of the Invention According to the present invention described above, a data decompression circuit can be configured with a simple configuration. Then, depending on the number of compressed data bits, the number of range bits, etc., the number of bits of the shift register, the number of initial MSH acquisitions, the preset value to the counter, the counter value when resetting the clip/70 It is highly versatile because the values and the like can be set appropriately.

[Brief explanation of the drawing]

Figure 1 shows the principle of PCM, Figure 2 shows the data structure, Figure 6 explains the compression method, Figure 4 shows how the data is compressed, and Figure 5. 6 is a diagram showing the state of data expansion, FIG. 6 is a diagram showing the expansion circuit according to the present invention, and FIG. 7 is an operation waveform diagram thereof. (1) is a shift register, (2) is a color register. Figure 1 Figure 2 Nc, Figure 32 (a) (b)

Claims (1)

[Claims] 111 Sample the analog signal and set N bits to 1
The MSB (most significant bit) of this binary code is placed first, followed by the first bit of the binary code representing its absolute value level. Continuously from bit (M
-1) Bits (N) M) are extracted and added to obtain M-bit compressed data, and range information bits corresponding to the absolute value level are obtained, and the information obtained in this way is transmitted. a circuit for decompressing the compressed data into the original N-bit binary code based on the transmitted compressed data and range information; and an N-bit shift register for reading the transmitted compressed data. , a counter to which the transmitted range information is preset is provided, and the MSB of the compressed data bits is stored in the shift register.
A predetermined number of data bits are read, and range information is preset in the counter, and then the compressed data bits are sequentially read into the shift register, and in response to this reading operation, the counter is counted up from the preset value, and the range information is preset in the counter. , a digital data expansion circuit configured to stop the reading operation of the shift register when the counter counts up to a predetermined value, thereby obtaining the original binary code expanded to N bits from the shift register.