JPS6062115A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS6062115A
JPS6062115A JP16919683A JP16919683A JPS6062115A JP S6062115 A JPS6062115 A JP S6062115A JP 16919683 A JP16919683 A JP 16919683A JP 16919683 A JP16919683 A JP 16919683A JP S6062115 A JPS6062115 A JP S6062115A
Authority
JP
Japan
Prior art keywords
film
phosphorus
metal
chromium
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16919683A
Other languages
Japanese (ja)
Inventor
Masao Tsuruoka
鶴岡 征男
Junichiro Horiuchi
堀内 潤一郎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP16919683A priority Critical patent/JPS6062115A/en
Publication of JPS6062115A publication Critical patent/JPS6062115A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation

Abstract

PURPOSE:To bond both an inorganic insulator and metals and a metal excellently by using the evaporating source metal containing phosphorus. CONSTITUTION:An Al film 2 as an ohmic contact is formed to one part of the surface of a Si base body 1. The base body 1 and the surface of the film 2 are coated with a SiO2 film 3, and one part of the film 3 on the film 2 is not formed on a window. A Cr-Cu composite film 4 is bonded with the film 2 not coated with the film 3, and extended and bonded on the peripheral film 3. An evaporating source Cr for the film 3 contains phosphorus. When Cr and Cu for the film 3 are evaporated, phosphorus is evaporated together with Cr, the surface of the layer 3 is reduced while also being combined with Cr, Cr and Cu fill roles such as an inverter for the film 3 and a Cr layer, and adhesive force to the film 3 is ensured. The deacidifying action of phosphorus also contributes to adhesion between the film 2 and the Cr layer.

Description

【発明の詳細な説明】 〔発明の利用分野〕 本発明は一1半導体装置の製法に係シ、特に半導体基体
上に金属膜を物理蒸着する方法に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for physically vapor depositing a metal film on a semiconductor substrate.

〔発明の背景〕[Background of the invention]

半導体装置は、外部回路との接続のために、主として金
属から成る電極を有する。電極は、半導体基体とオーミ
ックコンタクト性を有する必要がおる。その平面構造は
、被接着生たる半導体基体の形態に応じて千差万別であ
シ、単純に半導体基体上に金属を重ねた物のみならず、
例えば、電極パターンの外周部で、電極形成半導体部を
外囲する酸化膜、像化膜、ガラス等の絶縁膜や8IPO
8膜に乗シ♀げる形状、あるいは電極形成半導体部より
離れた部分に外部接続部をもたらすために、絶縁膜上に
乗シ上げ延長する形状がある。斯る構造を製作する場合
の問題点に、半導体基体、絶縁膜や、5IPO8膜に対
する接着性、および複合構造を採る場合には異種金属相
互の接着性の良し悪しがある。この問題に、対処するた
め、金属の組み合わせは、当該金属相互の反応の難易や
反応の形態等にもとづいて勘案した「相性」によって選
択し、また、絶縁膜上に形成する場合、例えば無機絶縁
膜では、酸素と結合し易い金属を選択する等の手段を講
じている。斯様な配慮にもかかわらず、これら電極は、
しばしば、接着力の弱小、電気抵抗の過大が起こシ、半
導体装置の製造に障害をもたらしている。斯る障害の生
ずる原因の多くは、金属を物理蒸着形成する時点におけ
る被蒸着部分の表面酸化物と蒸着中の蒸発金属の酸化に
あることが判明している。
A semiconductor device has electrodes mainly made of metal for connection with an external circuit. The electrode needs to have ohmic contact with the semiconductor substrate. The planar structure varies widely depending on the form of the semiconductor substrate to be bonded, and is not limited to simply stacking metal on a semiconductor substrate.
For example, at the outer periphery of the electrode pattern, an oxide film, an imaging film, an insulating film such as glass, or an 8IPO film surrounding the electrode forming semiconductor part.
There is a shape that extends over the 8th film, or a shape that extends over the insulating film in order to provide an external connection part in a part remote from the electrode-forming semiconductor part. Problems in manufacturing such a structure include adhesion to the semiconductor substrate, insulating film, and 5IPO8 film, and in the case of a composite structure, adhesion between different metals. In order to deal with this problem, the combination of metals is selected based on ``compatibility'', which takes into account the difficulty of reactions between the metals and the form of the reaction, and when forming on an insulating film, for example, inorganic For the membrane, measures are taken such as selecting a metal that easily combines with oxygen. Despite such considerations, these electrodes
Weak or weak adhesion and excessive electrical resistance often occur, causing problems in the manufacture of semiconductor devices. It has been found that many of the causes of such problems are due to the oxidation of surface oxides on the part to be deposited at the time of physical vapor deposition of the metal and the oxidation of the evaporated metal during deposition.

〔発明の目的〕[Purpose of the invention]

本発明は、上記従来技術における欠点を克服するために
創出されたもので、目的とするところは複合電極を構成
する金属相互、半導体基体、無機質絶縁膜や5IPO8
膜と電極金属を物理蒸着によシ良好に接着させることが
できる半導体装置の製法を提供することにある。
The present invention was created in order to overcome the drawbacks of the above-mentioned prior art, and aims to solve the problems of metal interlayers, semiconductor substrates, inorganic insulating films, and 5IPO8 constituting a composite electrode.
It is an object of the present invention to provide a method for manufacturing a semiconductor device that can bond a film and an electrode metal well by physical vapor deposition.

〔発明の概要〕[Summary of the invention]

本発明は、リンが他の原子と化合物を作り易い性質を応
用したもので、特徴とするところは、蒸発源金属にリン
を含有させることにある。
The present invention takes advantage of the property of phosphorus to easily form compounds with other atoms, and is characterized by the fact that the evaporation source metal contains phosphorus.

〔発明の実施例〕[Embodiments of the invention]

以下、本発明を実施例によって説明する。 Hereinafter, the present invention will be explained by examples.

第1図において、1はシリコン基体で、シリコン基体1
の表面の一部分にオーミックコンタクトとして、アルミ
ニウム膜2がある。シリコン基体1表面とアルミニウム
膜2表面上に5j02膜3が覆い、アルミニウム膜2上
の5102膜3の一部は窓状に存在しない。5j02膜
3によって覆れていないアルミニウム膜2にはクロム−
銅複合膜4が接着し、周囲の5iOz膜3上に延在して
接着している。本構造は、クロム−銅複合膜4上に、半
田ボールを形成し、コントロールコラプス市ンデイング
に供するところのボールリミッティングメタラジ−であ
る。第2図は、第1図の一部をさらに詳しく描いたもの
で、アルミニウム膜2は、厚さ3μm、Bit)2膜3
は厚さ5μmでおる。クロム−銅複合膜4は0.15μ
m厚さのクロム41と0.65μm厚さの銅42の2層
から成る。
In FIG. 1, 1 is a silicon substrate;
There is an aluminum film 2 on a part of the surface as an ohmic contact. The 5j02 film 3 covers the surface of the silicon substrate 1 and the surface of the aluminum film 2, and a part of the 5102 film 3 on the aluminum film 2 does not exist in the form of a window. The aluminum film 2 not covered by the 5j02 film 3 is coated with chromium.
The copper composite film 4 is adhered and extends onto and adheres to the surrounding 5iOz film 3. This structure is a ball-limiting metallurgy in which solder balls are formed on a chromium-copper composite film 4 and subjected to controlled collapse assembly. FIG. 2 depicts a part of FIG. 1 in more detail, and the aluminum film 2 has a thickness of 3 μm.
The thickness is 5 μm. Chromium-copper composite film 4 is 0.15μ
It consists of two layers: chromium 41 with a thickness of m and copper 42 with a thickness of 0.65 μm.

−例では、真空蒸着によシ、クロム層41と銅層42を
蒸着した。蒸着源クロムは、0.1重量%のリンを含有
する。含リンクロムは、溶融クロムにリンまたはリンを
含有するクロムを混入させて製造した物である。電子ビ
ーム加熱により0.1μm厚さにクロムを蒸着し、続い
て0.05μm厚さ相当のクロムを蒸着する間中、0.
05μm厚さ相当の銅も蒸着し、接いて銅を0.6μm
厚さに蒸着した。以上の蒸着によればクロムと共にリン
が蒸発し、5LOz層30表面を還元すると同時に、ク
ロムとも結合し、あたかも、SiO2膜3とクロム層4
1のバインターの如き役を果し、81Ch膜3に対する
接着力を確保する。リンの脱酸作用は、アルミニウム膜
2とクロム層41間の接着へも寄与する。アルミニウム
膜2は蒸着前、酸処理によって清浄にされるが、空気中
の酸素と結合してアルミナ膜が形成されている。クロム
と共にリンが蒸着されるので、リンがアルミナと結合し
てスラグを形成し、アルミナに覆れない表面部を出現さ
せ、アルミニウムとクロムの直接接触をもたらす。
- In the example, the chromium layer 41 and the copper layer 42 were deposited by vacuum deposition. The source chromium contains 0.1% by weight of phosphorus. Phosphorus-containing chromium is produced by mixing phosphorus or chromium containing phosphorus into molten chromium. Chromium was evaporated to a thickness of 0.1 μm by electron beam heating, and then chromium was deposited to a thickness of 0.05 μm.
Copper equivalent to a thickness of 0.5 μm was also deposited, and the copper was bonded to a thickness of 0.6 μm.
Deposited to a thickness. According to the above vapor deposition, phosphorus evaporates together with chromium, reduces the surface of the 5LOz layer 30, and at the same time combines with chromium, as if SiO2 film 3 and chromium layer 4
1, and secures adhesive strength to the 81Ch film 3. The deoxidizing effect of phosphorus also contributes to adhesion between the aluminum film 2 and the chromium layer 41. Although the aluminum film 2 is cleaned by acid treatment before vapor deposition, it combines with oxygen in the air to form an alumina film. As phosphorus is deposited along with chromium, it combines with the alumina to form a slug, leaving surfaces uncovered by alumina and providing direct contact between aluminum and chromium.

他の例では蒸着源鋼に0.2重量%のリンを含有させた
In another example, the source steel contained 0.2% by weight phosphorus.

蒸着源鋼は、市販品の品位の低い物を分析をして選択し
た物である。前述の一例と同様にして、クロムと銅を蒸
着した。本例の場合、銅蒸着の際、蒸発し易さから、リ
ンの蒸発が先行し、クロム側はど多くリンがとりこまれ
る。 リンは0.1μmのクロムの上に蒸着されるが、
ゲッタ効果を及ぼして、クロム蒸着中に真空チャンバ内
の残留酸素と結合して生じたcr−oを還元することが
できる。
The evaporation source steel was selected after analyzing low-quality commercial products. Chromium and copper were deposited in the same manner as in the previous example. In the case of this example, when copper is deposited, phosphorus evaporates first due to its ease of evaporation, and a large amount of phosphorus is incorporated into the chromium side. Phosphorus is deposited on top of 0.1 μm chromium,
It can exert a getter effect to reduce the cr-o produced by combining with residual oxygen in the vacuum chamber during chromium deposition.

そのため、5i02膜3と接する部分で、クロムは酸素
を共有する形態で接着するので、理想的な接着をもたら
す。本例は金属膜を通して、間接的にリンが効く場合を
示している。
Therefore, the chromium adheres to the portion in contact with the 5i02 film 3 in a form that shares oxygen, resulting in ideal adhesion. This example shows a case where phosphorus acts indirectly through a metal film.

クロムと銅について実施例を述べたが、リンはアルミニ
ウム、チタン、バナジウム、ニッケル。
Examples have been given for chromium and copper, but phosphorus is aluminum, titanium, vanadium, and nickel.

コバルト、鉄、銀、金、モリブデン、タングステン等の
電極として用いられている大概の金属と反応してリン化
物を形成するので、実施例にかかわらず、これらの他の
金属に対しても、本発明が適用できることは勿論であシ
、また真空蒸着法以外の物理蒸着すなわちスパッタリン
グ法貸よびイオンブレーティング法も利用できる。
Since it reacts with most metals used as electrodes, such as cobalt, iron, silver, gold, molybdenum, and tungsten, to form phosphides, this book does not apply to these other metals, regardless of the examples. It goes without saying that the invention is applicable, and physical vapor deposition, sputtering, and ion blating methods other than vacuum deposition can also be used.

また、複合構造を採らない場合でも、電極となる金属の
蒸着源にリンが含有されていれば、蒸着後には、該金属
は半導体基体や半導体基体上に設けられている絶縁膜、
あるいは5IPO8膜と良好な接着を示す。
Furthermore, even if a composite structure is not adopted, if the vapor deposition source of the metal that becomes the electrode contains phosphorus, after vapor deposition, the metal can be applied to the semiconductor substrate or the insulating film provided on the semiconductor substrate.
Alternatively, it shows good adhesion with the 5IPO8 film.

更に、複合構造を採用する場合、全ての蒸着源金属にリ
ンを含有させておく必要はなく、接着憔の低い金属につ
いてのみにリンを含ませておいてもよい。
Further, when a composite structure is employed, it is not necessary to include phosphorus in all the vapor deposition source metals, and only metals with low adhesion may contain phosphorus.

〔発明の効果〕〔Effect of the invention〕

以上、本発明によれば、リンを含有する蒸発源を用いる
ことによシ、無機絶縁物および金属相互と金属を良好に
接着させることができる。
As described above, according to the present invention, by using an evaporation source containing phosphorus, an inorganic insulator and a metal can be bonded to each other well.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例によって得られる半導体装置
の部分的断面図、第2図は第1図の一部拡大図である。
FIG. 1 is a partial sectional view of a semiconductor device obtained according to an embodiment of the present invention, and FIG. 2 is a partially enlarged view of FIG. 1.

Claims (1)

【特許請求の範囲】 1、半導体基体上に金属を蒸着する半導体装置の製法f
おいて、蒸着源金属にリンが含有されていることを特徴
とする半導体装置の製法。 2、特許請求の範囲第1項において、半導体基体上の一
部に金属膜、絶縁膜、又は5IPO8膜が設けられてお
シ、これらの膜上又は半導体基体上にかけてリンを含有
する金属が蒸着されることを特徴とする半導体装置の製
法。 3、%許請求の範囲第1項において、リンが含有されて
いる蒸着源金属は真空蒸着、スノくツタリング、又はイ
オンブレーティング法で半導体基体上に蒸着されること
を特徴とする半導体装置の製法。 4、特許請求の範囲第1項において、蒸着源金属はアル
ミニウム、クロム、チタン、ノ(ナジウム。 ニッケル、コバルト、鉄、銅、銀、金、モリブデン、タ
ングステンのいずれか、又は、これらを成分要素として
含有する合金であることを特徴とする半導体装置の製法
。 5、特許請求の範囲第2項において、絶縁膜は半導体酸
化膜、窒化膜、ガラス等の無機絶縁膜でおることを特徴
とする半導体装置の製法。
[Claims] 1. Manufacturing method f of a semiconductor device in which metal is deposited on a semiconductor substrate
A method for manufacturing a semiconductor device, characterized in that the vapor deposition source metal contains phosphorus. 2. In claim 1, a metal film, an insulating film, or a 5IPO8 film is provided on a part of the semiconductor substrate, and a metal containing phosphorus is deposited on these films or on the semiconductor substrate. A method for manufacturing a semiconductor device characterized by: 3. Percentage of Claims Claim 1 provides a semiconductor device characterized in that the evaporation source metal containing phosphorus is deposited on a semiconductor substrate by vacuum evaporation, snobbing, or ion blating method. Manufacturing method. 4. In claim 1, the vapor deposition source metal is any one of aluminum, chromium, titanium, sodium, nickel, cobalt, iron, copper, silver, gold, molybdenum, and tungsten, or a component containing these. 5. In claim 2, the insulating film is an inorganic insulating film such as a semiconductor oxide film, a nitride film, or glass. Manufacturing method for semiconductor devices.
JP16919683A 1983-09-16 1983-09-16 Manufacture of semiconductor device Pending JPS6062115A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16919683A JPS6062115A (en) 1983-09-16 1983-09-16 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16919683A JPS6062115A (en) 1983-09-16 1983-09-16 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS6062115A true JPS6062115A (en) 1985-04-10

Family

ID=15881991

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16919683A Pending JPS6062115A (en) 1983-09-16 1983-09-16 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS6062115A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6372156A (en) * 1986-09-16 1988-04-01 Hitachi Ltd Semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6372156A (en) * 1986-09-16 1988-04-01 Hitachi Ltd Semiconductor device

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