JPS6060077B2 - Analog signal synthesizer - Google Patents

Abstract

PURPOSE:To generate a synthetic sound with neither discontinuous waves of a connection part nor variation in pitch frequency by selecting the shift amount of data when the sum of absolute values of level differences of connection-part sampling values between preceding and following phoneme waveforms becomes minimum. CONSTITUTION:In memory units 103 and 104, an analog input signal sampled according to clocks is stored, and binary signal converter 124 converts sampling values of the connection part of a preceding phoneme waveform and following phoneme waveform into binary signals of polarities equivalent to the input signal. Here, arithmetic processor 121 sums up absolute values of level differences and the shift amount of sampling data when the calculation value becomes minimum is selected among calculation values through its calculation operation, so that memory units will be clock-controlled by programs to adjust the time axis of the following connection phoneme element. Consequently, a synthetic sound can be obtained with neither discontinuous waveforms of the connection point nor variation in pitch frequency.

Description

[Detailed description of the invention]

The present invention relates to an apparatus for synthesizing analog signals such as audio, and an object of the present invention is to improve the quality of synthesized analog signals. In general, the quality of speech signals (words, phrases, speech) synthesized by combining and editing phoneme fragments, that is, words, syllables, or even shorter speech segments, is determined by the processing of the connections between phoneme fragments, which are the constituent units of speech. It can be said that it depends on For example, a sudden change in waveform that occurs at the junction of phoneme pieces,
That is, the discontinuity of the waveform causes harmonic noise, lowers the S/N of the synthesized sound, and reduces the clarity. It is also known that fluctuations in the pitch frequency, which is the fundamental frequency of vocal cord vibration, degrade the naturalness of synthesized speech. Human hearing is extremely sensitive to changes in pitch frequency (the detection limit is said to be 0.1%), and when the pitch frequencies of connected phoneme segments are discontinuous, the synthesized speech becomes difficult to hear and unnatural. Become something. The present invention makes it possible to obtain high-quality synthesized speech by recognizing the pattern of phoneme segment waveforms and combining each phoneme segment in a natural manner. There are methods of using segment waveforms cut out from natural speech, for example at mid-pitch intervals, or by extracting one segment waveform synthesized by another speech synthesizer, but the present invention is relatively simple. The object of the present invention is to provide a method for combining phoneme segments of a short time, specifically, several tens to hundreds of milliseconds, without discontinuities in waveforms at connections and without fluctuations in pitch frequency. In other words, such short-time phoneme segments should have similar waveforms at least at the joints of adjacent phoneme segments, and therefore, by slightly modifying the time axis of each phoneme segment, the joints can be made similar. It can be combined smoothly. The present invention roughly grasps the degree of waveform similarity in the form of a signal level for the connecting portions of phoneme segments to be combined, and based on this, makes appropriate temporal corrections to the time axes of the phoneme segments. FIG. 1 is a block diagram illustrating a conventional time axis expansion device. In the figure, 1 is the audio input terminal, 2 is the output terminal, 3 and 4
are N-bit analog shift registers such as BBD, and 5 is a reduced pass filter LpFl6, 7, 8.
and 9 are analog switches for controlling the audio signal from the input terminal 1 to the output terminal 2 via the analog shift register 3 or 4, L, F5. These analog switches are operated as shown in the figure by the Q and O outputs of a frequency divider circuit 11 that divides the write clock circuit CPlO of the analog shift registers 3 and 4 by MN (MN is an integer, and m will be described later). Opening/closing controlled. The analog shift registers 3 and 4 are alternately write clock controlled by AND gates 12 and 13 of the Q and O outputs of the clock circuit 10 and frequency divider circuit 11 via 0R gates 14 and 15, and are controlled by the read clock circuit CPl6. and frequency dividing circuit 11
The read clock is alternately controlled by AND gates 17 and 18 of the Q and O outputs of , and also via 0R gates 14 and 15. That is, for example, an audio signal in which the time axis applied to the input terminal 1 is compressed by m times (m>1) (such a compressed signal is, for example, the playback speed of a tape recorder, m
) is read into the analog shift register 4 via the analog switch 8 when the Q output of the frequency dividing circuit 11 is 1. The number of bits of the shift register is N, and when a number of sampling strings have been sequentially input as input audio signals, the Q output of the frequency dividing circuit 11 is inverted to O, and the switch 8 is closed. At the same time, the O output of the frequency dividing circuit 11 becomes O, and the switch 6
Open it and write to the analog shift register 3 in the same way. At this time, as is clear from the configuration in the figure, the analog shift register 4 is clocked by the read clock circuit 16 and read out via the switch 9 which is also controlled by the output. analog shift register 3
During the writing period, another analog shift register 4 reads in this way, and then the Q of the frequency divider 11
, O When the output is inverted, the analog shift register 4 is switched again.
writes, and 3 reads. Here, if the clock frequency of the write clock circuit 10 is f1 and the clock frequency of the read clock circuit 16 is F2, then if each clock frequency is determined so that The input compressed audio is output to the output terminal 2 with its time axis restored. The read clock frequency F2 is naturally determined to satisfy Nyquist's sampling theorem for the necessary output audio frequency band. In the conventional device as described above, the connection timing of the phoneme pieces that are alternately output from the analog shift registers 3 and 4 is automatically determined every MN/f 1 second by the output of the frequency dividing circuit 11 that divides the write clock 10 by MN. Therefore, as shown in FIG. 6, discontinuous waveform changes and pitch frequency fluctuations occur at the connection portion. As mentioned above, such discontinuities in the waveform and pitch frequency at the junctions of phoneme segments significantly reduce the sound quality and clarity. Next, the content of the present invention, which improves the drawbacks of such conventional devices, will be explained with reference to the block diagram of FIG. In the figure, 103 and 104 are analog switches 106,
Analog shift registers 107, 108 and 109 control the opening and closing, 110 and 116 are clock circuits for writing and reading frequencies f1 and F2, respectively, and 111 is an MN frequency dividing circuit. This is the same as the conventional device shown in the figure. In the present invention, as described above, the temporal correction is applied to the connecting portions of connected phoneme pieces, and this is carried out by the arithmetic processing unit (computer) CPU12l programmed by the ROM12O. The counter 122 is a circuit that counts phoneme pieces and rear ends in each period and provides timing instructions to the CPU 12l via the I/O boat 123, and the A/D converter 124 converts input signals according to the conversion command signal from the clock circuit 110. The memory circuit RAM125 following the CPU12l, which is a circuit for digitally converting the data, has the function of storing only the most significant digit of these A/D-converted digital code signals, and at the same time temporarily storing the arithmetic processing results of the CPU12l. It is something. The reason why only the most significant digit of the A/D converter output is used here is because, as mentioned above, for short-time phoneme segments of several tens to hundreds of milliseconds, the waveform of at least the joint of adjacent phoneme pieces is should be similar, and in order to suppress fluctuations in the fundamental pitch of the voice, the purpose is achieved by combining the zero-crossing points of the voice's fundamental pitch waveform with the least error. Therefore, the input waveform should be coarsened. This is because even when patterned, substantially the same result can be obtained as compared to the case where all digits of the A/D converter output are used through the calculation processing described later. Patterning the input waveform using only the most significant digit of the A/D converter output means that if the A/D converter output is a natural binary code, the input waveform is within the dynamic range of the A/D converter. Depending on whether it exceeds 112 or not,
[1] respectively,

An output of [0] is output in synchronization with the convert command signal. The same function can be achieved in other ways, for example by ANDing the output of the comparator 126 with the convert command signal using the N1 gate 127, as shown in the dashed line in FIG. can. In addition, the amplitude of the signal is saturated by an amplifier, the polarity is determined, and the AND signal is combined with the convert command signal.
You can also get the same functionality by taking . Next, the main part of an embodiment using such an amplifier for amplitude saturation is shown in FIG. In FIG. 3, 128 is an amplifier with a sufficiently large gain, and 129 is a clamp circuit. Now, when an input signal as shown in FIG. 4a is applied to the input terminals 1n and 101, the input signal is amplified and saturated by the amplifier 128, and the output of the amplifier 128 becomes as shown in FIG. 4b.
Furthermore, the lower end (or upper end) of the signal is clamped by the clamp circuit 129.
is clamped, the output of the clamp circuit 129 becomes as shown in FIG. 4C. The output of the clamp circuit 129 is then applied to the AND gate 127 together with the convert command signal. If this configuration uses only the most significant digit of the A/D converter, an A/D converter with a small number of output bits can be used, and a comparator or saturation amplifier can also perform the same function. I can do it. In other words, an A/D converter, a comparator, or the like can be used as a binary signal converter that converts an input signal into a binary signal corresponding to the polarity. These A/D converters, comparators, etc. can be constructed at low cost. In such a configuration, the amount of information processed by the computer is further reduced, and the ROM
Also, the configuration of the computer section can be made inexpensive, such as the capacity of RAM can be reduced. Well, first of all, the CPU
l2l is based on the output of the counting circuit 122, and outputs M samples from the last part of the input clock to the A/D converter output 1.
24, only the most significant digit is read from the I/0 port 123 and stored in the memory circuit 125. Next, when the output of the frequency divider circuit 111 is inverted, CPUl2l
Similarly, based on the output of the counting circuit 122, (M+r) samples are read from the leading edge of the input clock. Subsequently, the CPU 12l calculates the similarity between the rear end of the input phoneme segment and the following phoneme segment based on the program in the ROM 12O, and it is preferable to calculate the squared error of each sampling sequence. The sampling number sequence at the rear end of a phoneme is Xp (p=1, 2, 3, . . . M), and the sampling number sequence at the front end of the subsequent phoneme segment is Yp (p = 1, 2, 3, . . . M).
+r), the square error between the two waveforms is expressed as. This expresses the degree of similarity when Yp is shifted by k points and superimposed on the sampling waveform Xp. However, the arithmetic processing based on equation (2) actually requires a huge number of calculation steps, and requires a high-performance computer to perform calculations in a short period of time (at least several tens of milliseconds). Originally, equation (2) was used to examine the correlation between two waveforms with different amplitudes and levels, and therefore the standard deviations σX, σ
The error is calculated by normalizing the waveform with y and then calculating the sum of squares of the difference between the average level 'X and y. By the way, in the case of the speech synthesis apparatus of the present invention, the phoneme pieces handled have waveforms that are close in time, and therefore, it can be considered that the amplitude and level are originally similar. In this case, the difference between the two waveforms can be calculated using equation (2) instead. Furthermore, in the case of the present invention, it is only necessary to know the timing at which the similarity between the two waveforms is maximum, and therefore equation (3) can be further replaced with the following equation (4). Here Xp and YP+
Since k is the data of only the most significant digit of the A/D converter,
Either [1] or

It is [0]. That is, this is the integral of the absolute value of the difference between the corresponding sampling values, and the connection timing is determined by knowing k at which this is the minimum. That is, the arithmetic processing unit 121 calculates Ek for k=0, 1, . That is, the fifth
As shown in the figure, the sequence of M samples at the end of the preceding phoneme is:
It follows that overlapping from a portion shifted by k positions from the beginning of the succeeding phoneme has the least error. Then, the arithmetic processing unit 121 takes in (k+M+N) samples from the beginning of the subsequent phoneme, and sends them to A through the 1/0 boat 123.
Controls the ND gate 112 or 113 to stop the write clock. Since the capacity of the analog shift register 103 or 104 is N, N bits are stored in the analog memory from the (k+M+1)th as shown in the figure, and are sequentially read out at the next read timing. As is clear from the explanation, the last M samples of the preceding phoneme and (k+1) of the following phoneme
Since the M samples from the th to M samples overlap with each other with the least error, the phoneme pieces are continuously output in a completely natural form. As mentioned above, (k+M+N) samples of the subsequent phoneme are captured into analog memory,
Of these, M samples from the end are similarly sent to the A/D converter 1.
24, and is stored in the storage device 125 of the CPU 12l via the I/0 boat 123. This is necessary in order to check the similarity with (M+r) samples from the beginning of the subsequent phoneme and connect them. A time chart of the above processing is shown in FIG. 5C. The important thing here is that the analog shift register 103 or 104 has N bits, so even if a sample of more bits (M+k+N) is read, only the last N bits will be stored. be. Although the time length of a phoneme segment is at least several tens of milliseconds, the calculation of Ek shown in equation (4) can be processed with extremely few steps, and a low-speed so-called microcomputer can be used. In addition, FIG. 6 shows the reproduced audio waveform of the time axis expansion device according to the conventional method shown in FIG. 1, and FIG. This shows data actually processed for a single signal. Both of these data are m=2, f1=40KHz. ．． f2
=20KHz. ．． It was measured under the condition that N=768. In the above description, the present invention has been specified as a specific example of an audio time axis expansion device, but instead of using the analog shift register as described above, a RAM may be used as a storage means. Convert the waveform into a digital signal with an A/D converter, then input it to RAM,
Needless to say, the conventional technique of converting the RAM output into an analog signal using a D/A converter is used. As described above, it goes without saying that the technique of the present invention can be used in a synthesis device for analog signals such as various voices and sounds. As described above, the device of the present invention calculates the integral value of the absolute value of the difference between the sampling value at the rear end of the preceding analog signal element and the sampling value of the succeeding analog signal element at the connecting portion of the preceding analog signal element and the succeeding analog signal element. The time axes are corrected in order to overlap them so that they are minimized. More specifically, the present invention compares the similarity of waveforms near the rear end of the preceding analog signal element stored in the storage means and near the leading end of the subsequent analog signal element, and compares the similarity between the preceding analog signal element and the subsequent analog signal element. Subsequent analog signal segments may be clocked so that the analog signal segments are connected as smoothly as possible. That is, the data near the rear end of the preceding analog signal element and the data near the leading end of the succeeding analog signal element are relatively shifted and compared, and the following analog signal element is the most similar to the preceding analog signal element. The data of the subsequent analog signal segment is clocked out from the storage means so that the connection is smooth. Therefore, it is possible to obtain a composite analog signal without discontinuities in analog signal waveforms or fluctuations in pitch frequency at the connection parts as in conventional devices.

[Brief explanation of the drawing]

Figure 1 shows a block diagram of a conventional analog signal synthesizer●
2 is a block diagram showing an analog signal synthesis device of the present invention, and FIG. 3 is a main block diagram showing an embodiment in which an amplitude saturation amplifier is used as a binary signal converter used in the device of the present invention.・Diagrams: FIG. 4 is a drawing to explain the operation of the embodiment shown in FIG. 3, FIG. 5 is a drawing to explain the device of the present invention shown in FIG. 2, and FIG. 6 is a diagram showing the characteristics of the conventional device. FIG. 7 is a drawing showing the characteristics of the device of the present invention. 101... Signal input terminal, 102... Signal output terminal, 103, 104... Analog signal storage device, 10
6,107,108,109...analog switch,
110...Writing clock, 116...Reading clock, 121... Arithmetic processing unit, 124...A
/D converter (binary signal converter).

Claims (1)

[Scope of Claims] 1. An analog signal synthesis device that edits and synthesizes analog signal segment waveforms extracted from analog signal waveforms, comprising: (a) a storage device that samples and stores input signals according to a clock; and (b) the sampling value of the connection part of the preceding analog signal elemental waveform obtained by sampling the input signal and the sampling value of the connection part of the subsequent analog signal elemental waveform, respectively, corresponding to the polarity of the input signal. (c) a binary signal converter that converts into a binary signal; and (c) two of the preceding analog signal segment waveforms that are the output signals of the converter.
The level difference between the value signal and the binary signal of the subsequent analog signal segment waveform is calculated, the sum of the absolute values of the level difference is calculated, and the corresponding sampling data is sequentially shifted to calculate the absolute value of the level difference. The total calculation operation is performed each time the shift is performed, and the shift amount of the sampling data that minimizes the calculated value among the values calculated by the calculation operation is selected, and the subsequent connected analog signal is calculated based on the selected shift amount. An analog signal synthesis device of an analog signal segment editing type, comprising: an arithmetic processing unit programmed to clock-control the storage device in order to adjust the time axis of the segment. 2. The analog signal synthesis device according to claim 1, wherein the binary signal conversion device uses the zero level of the input signal (or the bias level when the input signal is subjected to a bias) as a comparison level. 3. The analog signal synthesis device according to claim 1, wherein the binary signal conversion device comprises an amplifier that saturates the amplitude of the sampled value.