JPS6059975U - Attachment for sequence check - Google Patents

Attachment for sequence check

Info

Publication number
JPS6059975U
JPS6059975U JP15195883U JP15195883U JPS6059975U JP S6059975 U JPS6059975 U JP S6059975U JP 15195883 U JP15195883 U JP 15195883U JP 15195883 U JP15195883 U JP 15195883U JP S6059975 U JPS6059975 U JP S6059975U
Authority
JP
Japan
Prior art keywords
level
logic
attachment
sequence check
dip switch
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15195883U
Other languages
Japanese (ja)
Inventor
川崎 隼雄
Original Assignee
株式会社東芝
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 株式会社東芝 filed Critical 株式会社東芝
Priority to JP15195883U priority Critical patent/JPS6059975U/en
Publication of JPS6059975U publication Critical patent/JPS6059975U/en
Pending legal-status Critical Current

Links

Landscapes

  • Testing Of Short-Circuits, Discontinuities, Leakage, Or Incorrect Line Connections (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図はオア回路を示すブロック図、第2図は本考案の
一実施例の単位回路構成を示す回路図、    □第3
図は同実施例の適用例を示す回路図である。 11・・・ディップスイッチ、12・・・抵抗ネットワ
ーク。
Fig. 1 is a block diagram showing an OR circuit, Fig. 2 is a circuit diagram showing a unit circuit configuration of an embodiment of the present invention, □3rd
The figure is a circuit diagram showing an example of application of the same embodiment. 11...DIP switch, 12...Resistance network.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 基板上にとりつけられたディップスイッチと抵抗ネット
ワークとからなり、出力端を上記ディップスイッチによ
り入力端、論理「1」レベル、論理「0」レベルのいず
れかに選択的に接続するとともに、論理「1」レベル、
論理「0」レベルの少なくとも一方と上記ディップスイ
ッチとの間に上記抵抗ネットワークを形成した単位回路
を所要個数備えたことを特徴とするシーケンスチェック
用アタッチメント。
It consists of a dip switch and a resistor network mounted on the board, and the output terminal is selectively connected to the input terminal, either the logic "1" level or the logic "0" level, by the dip switch, and the logic "1" level "level,
A sequence check attachment comprising a required number of unit circuits forming the resistor network between at least one of the logic "0" level and the dip switch.
JP15195883U 1983-09-30 1983-09-30 Attachment for sequence check Pending JPS6059975U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15195883U JPS6059975U (en) 1983-09-30 1983-09-30 Attachment for sequence check

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15195883U JPS6059975U (en) 1983-09-30 1983-09-30 Attachment for sequence check

Publications (1)

Publication Number Publication Date
JPS6059975U true JPS6059975U (en) 1985-04-25

Family

ID=30336595

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15195883U Pending JPS6059975U (en) 1983-09-30 1983-09-30 Attachment for sequence check

Country Status (1)

Country Link
JP (1) JPS6059975U (en)

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