JPS605985B2 - I/O interface control method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a channel device that controls the input/output interface in a data processing device.

When transmitting and receiving signals on the input/output interface between the channel device and the input/output control device in a data processing device, when the control sequence of the interface malfunctions, it is difficult to detect all of the malfunctions due to the large number of combinations. there were.

Further, there are disadvantages in that it is difficult to set a time period during which asynchronous signals such as interrupt signals are permitted to be accepted, and that the channel response time for asynchronous signals is too long. Furthermore, at the same time, there was also the drawback that the logic for determining priorities for signals sent onto the interface was fixed. The purpose of the present invention is to solve the above-mentioned drawbacks of the prior art by coding interface control signals and check signals, and in particular, to prevent sequence malfunctions by sending a signal (OUT signal) from the channel device to the control device. , when the W signal (signal from the control device to the channel device) corresponding to the OUT signal is already rising at the time the signal is sent, and when an asynchronous IN signal is not supposed to be sent but is in the middle of the sequence. The aim is to carefully check whether the expected signal is received from the control unit's pupil, but other unexpected signals are received at the same time.

Furthermore, another object of the present invention is to facilitate control of an input/output interface with many branches.

In order to achieve the above object, the present invention defines a coded input/output interface control signal and a check signal as a sequence word, and uses the sequence word as a sequence word when a channel is input into a sequence stack according to the order of the interface sequence. Prepare this before starting up the output control device.

After the channel is activated, the sequence word indicated by the -sequence counter is read into the sequence register to sequentially control and check the input/output interface signals. Also, the update of the sequence counter is 11
As a general rule, when an asynchronous signal or multiple signals rise at the same time, the sequence counter is updated according to the bit position of the sequence register in order to perform branch control, and subsequent processing is based on the sequence word at the branch destination. Follow the instructions. Hereinafter, the contents of the present invention will be explained in detail with reference to the drawings.

FIG. 1 shows an example of the bit structure of a sequence word used in the present invention.

In this example, each bit position of bit positions 0 to 4 of the 12-bit bit configuration indicates an OUT signal or an m signal. Bit position 5 is an OUT/IN control bit; when it is “0”, it means that the signals corresponding to bit positions 0 to 4 are calm signals (SIo to SL); when it is “1”, , the signals corresponding to bit positions 0 to 4 are OUT signals (S0o to S04)
It means that. The BR bit in bit position 6 is
When it is unclear from which bit position the IN signal occurs, the type of the W signal is used to determine whether to give permission to update the sequence counter, which will be described later. Bit positions 7 to 11 specify check signals, and each bit position from C4 to Co is S04.
This corresponds to signals from S○o or SI4 to SIo. FIG. 2 shows the configuration of an embodiment of the present invention in which asynchronous signals are not handled.

In a channel program, a series of interface control OUT signals,
The sequence word described in FIG. 1, which encodes the melon signal and the check signal, is transferred from the main memory or control memory into the sequence stack 1 in a predetermined order.
Thereafter, when actually starting up the input/output control device, the sequence word corresponding to the stack address indicated by the sequence counter 2 is read out from the sequence stack 1 and set in the sequence register 3. In the example in Figure 2,
Since the OUT/IN control bit at bit position 5 of sequence register 3 is “0”, it specifies waiting for the IN signal,
SI because bit position 0 is “1”. Specifies to wait for a signal. Also, since bit positions 8 and 9 are both “1”, when the channel specifies waiting for the SL signal, the S
I or SI2 signal is rising inappropriately, or SI. If the SI or SI2 signal rises incorrectly while waiting for a signal, the error flip-flop 7 is activated at timing T2.
By setting , you can check for sequence malfunctions. The check signals from bit positions 7 to 11 can be specified arbitrarily, and detailed checks are possible.
By freezing the error flip-flop 7 when the RROR-P signal 6 occurs, the FF analysis becomes easy. If the SL signal is normally sent from the control device and the SL signal is fired,
At timing T, the ADDI-P signal 5 is output, the adder circuit 10 increments the sequence counter 2 by 11, and transfers the sequence word stored at the next stack address from the sequence stack 1 to the sequence register 3. set,
Processing proceeds to the next interface control. The control method when bit position 5 is "1", that is, designating the OUT signal, is to
SO as specified. Send any signal from T. to SQ. The ADDI-P signal is output at the timing of , and processing proceeds to the next sequence. In this case, it is also possible to test the state of the IN signal by using a check code. Note that 4 is an OUT/IN control gate, and 11 is a timing generation circuit that generates timing signals of T and T2. FIG. 3 shows another embodiment of the present invention, in which the wait designation for the m signal in FIG. 2 is expanded so that it can be applied to a plurality of signals.

Note that check code-related circuits are omitted. For convenience and to simplify the following explanation, it is assumed that even if there are multiple wait specifications, only one signal is actually sent from the control device. As in the case of FIG. 2, a series of sequence words are stored in the sequence stack 12, and when actually starting up the input/output control device, the sequence word corresponding to the stack address indicated by the sequence counter 13 is stored. word is set in sequence register 14. In the example of FIG. 3, bit position 5 of the sequence word set in the sequence register 14 is "0" and bit positions 2, 3, and 4 are "1", so SI2, SI3, SL
It is expected that one of the three signals will be sent from the control device. Since bit position 6 is “1”, SI2 and SI
3. When any of the SI4 signals is sent, the ADD4-P signal 19, ADD8-P signal 18, and A
The DD16-P signal 17 is generated at timing T3.
When any of the above signals is generated, the sequence counter 13 is updated by the function of the adder circuit 20. The updated sequence counter matches the address of the sequence word prepared in the sequence stack 12 before the channel program performs the input/output operation.
Timing signals T, , T3 are generated by a timing generation circuit 22. Note that although the time-over monitoring of the interface signal is omitted in FIG. 3, a sequence word group that instructs processing after time-out is prepared at a predetermined sequence stack address, and when the melon signal times out, The sequence counter 13 is incremented by a predetermined count, and the sequence stack 1 is incremented in advance.
It is clear that processing can be continued by accessing the sequence word stored in 2.

Further, in the embodiment, whether or not to stop the timing when an error occurs can be determined by providing an external switch or a control bit corresponding to the external switch in the sequence word, but the details will be omitted.

As is clear from the above description, according to the present invention, signals in the transmission and reception of signals of an input/output interface can be checked in detail by specifying expected signals and expected signals for each signal.

Furthermore, asynchronous signals can be easily masked or allowed for arbitrary periods of time.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the bit structure of a sequence word used in the input/output interface control method of the present invention, FIG. 2 is a diagram showing an embodiment of the present invention when an asynchronous signal is not handled, and FIG. FIG. 2 is a diagram showing an embodiment of the present invention that handles asynchronous signals. In Figure 2: 1...Sequence stack, 2...Sequence counter, 3...Sequence register, 4...
...OUT/IN control gate, 7...Error flip-flop, 10...Adder circuit, 11...
・In the timing generation circuit in Fig. 3: 12...sequence stack, 13...sequence counter, 14...
...Sequence register, 15...OUT//IN control gate, 16...Branch control gate, 20
...Adder circuit, 21...Timing generation circuit. Figure 1 Figure 2 Figure 3

Claims (1)

[Claims] 1. In a channel device that controls an input/output control device, a sequence word consisting of a control signal and a check signal for the input/output interface between the channel device and the input/output control device is transmitted to the input/output interface. storing in a storage means according to the order of the control sequence, sequentially reading out the sequence words from the storage means by an addressing means;
The control signal is sent to the input/output interface, and at the same time, the check signal in the sequence word is compared with the signal sent from the input/output control device to check the operation of the input/output interface. I/O interface control method. 2. The input device according to claim 1, wherein the control signal line in the sequence word matches a signal sent from an input/output control device, thereby controlling updating of the address means. Output interface control method.