JPS6059800A - Jig for integrated circuit element - Google Patents
Jig for integrated circuit elementInfo
- Publication number
- JPS6059800A JPS6059800A JP58168818A JP16881883A JPS6059800A JP S6059800 A JPS6059800 A JP S6059800A JP 58168818 A JP58168818 A JP 58168818A JP 16881883 A JP16881883 A JP 16881883A JP S6059800 A JPS6059800 A JP S6059800A
- Authority
- JP
- Japan
- Prior art keywords
- jig
- integrated circuit
- circuit element
- present
- circuit device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Supply And Installment Of Electrical Components (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
本発明は多数のピンを有する集積回路素子、特にＤ Ｉ
Ｐ （Ｄｕａｌ Ｉｎｌ ｉｎｅ Ｐａｋａｇｅ ）
に使用する治具に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an integrated circuit device having a large number of pins, in particular a DI
P (Dual Inline Package)
Regarding jigs used for.
従来から集積回路素子をプリント板に装着したものをチ
ェックする際治具を用いて氾１１定器に接続することは
広く行なわれている。このテスト用治具ばＷ！、１図に
示す如（ＤＩＰ型集型口積回路素子１ン２を両側から挾
み前記集積回路素子のピン２と接触する部分に設けた接
触片３と治具本体４の頭上部に設けた電極５を結線した
構造のものが一般的である。Conventionally, when checking an integrated circuit device mounted on a printed board, it has been widely practiced to connect it to a flood control device using a jig. This test jig is W! , as shown in FIG. 1 (a contact piece 3 is provided on the head of the jig main body 4, and a contact piece 3 is provided at the part that sandwiches the DIP type integrated circuit element 1 and 2 from both sides and makes contact with the pin 2 of the integrated circuit element). A structure in which electrodes 5 are connected together is common.
上述の如き従来の集積回路素子用治具に於ては電極５及
び集積回路素子のピン番号ｆ：表示するものは何等付さ
れておらず、所要のビンを捜すにあたってはピンの１番
からあるいは最後からその都度截ぞえていた。然るに近
年集積回路の高密化が進み、ビン数も飛開に増え゛、現
在６０ビンにも及ぶものが存在するが、このようにビン
の数が多くなると前記治具の使用の際特定のビンを捜す
ため多くの時間を要すると云う欠点があった。In the conventional integrated circuit device jig as described above, there is no display attached to the electrode 5 or the pin number f of the integrated circuit device, and when searching for the desired bin, start from pin number 1 or I kept repeating it from the end. However, as integrated circuits have become more dense in recent years, the number of bins has increased dramatically, and there are currently as many as 60 bins. The disadvantage is that it takes a lot of time to search.
本発明は上述したような従来の集積回路素子用治具の欠
点を除去するためになされたものであって、治具の表面
あるいは側面に、それぞれの電極が集積回路のピンの何
番にあたるか容易にわかるようマーキングを施した集積
回路素子用治具を提供することを目的とする。 ゛以下
本発明を図面に示した実施例に基づいて詳細に説明する
。The present invention was made in order to eliminate the drawbacks of the conventional integrated circuit device jig as described above. An object of the present invention is to provide a jig for an integrated circuit element that is marked for easy identification.゛Hereinafter, the present invention will be explained in detail based on embodiments shown in the drawings.
第２図は本発明に係る集積回路素子用治具の一実施例を
示す斜視図である。FIG. 2 is a perspective view showing an embodiment of the integrated circuit device jig according to the present invention.
本図に於て５・５．フ゛°゛°°は前記治具０頭頂部１
設けた電極であるが、これらに対応する前記治具本体４
の上端部に切欠６，６．・・・・・・を設ける。In this figure, 5.5.゛°゛°° is the jig 0 top of the head 1
Although the electrodes are provided, the jig main body 4 corresponding to these
Notches 6, 6. ...... will be established.
この切欠き６，６．・・・・・・は例えばピン番号５，
１０．１５・・・・・・の如くピン番号を認識し易いよ
うに適当な間隔をもって設ける。This notch 6,6. For example, pin number 5,
10.15..., the pin numbers are provided at appropriate intervals so that they can be easily recognized.
又本発明は以下のように変形しても良い。Further, the present invention may be modified as follows.
第３図は本発明に係る集積回路素子用治具の他の実施例
を示す部分的な斜視図でおるが、前記マーキイグとして
治具本体４の側面に所定の間隔を以ってピン番号に該当
する数字７，７．・・・・・を印刷もしくは成形する。FIG. 3 is a partial perspective view showing another embodiment of the jig for integrated circuit elements according to the present invention. Applicable number 7,7. ... to be printed or molded.
又この場合前述の数字の代りに第４図の如く単なるライ
ン８，８．・・・・・・の印刷か成形でも良く、あるい
は第５図に示すように治具本体４の頭頂面の所定の位置
にドツトマーク９，９．・・・・・・を印刷あるいは成
形しても良い。Also, in this case, instead of the aforementioned numbers, there are simply lines 8, 8, . . . as shown in FIG. . . . may be printed or molded, or as shown in FIG. 5, dot marks 9, 9 . . . . may be printed or molded.
本発明は以上説明した如く構成するので、プリント板等
に装着した多くのピンを有する集積回路をこの治具を用
いて調整等を行う場合、所要の電極を捜すにあたって前
記マーキングを目付しにカウントすることができるから
容易に目標の電極ケみつけることができる。Since the present invention is constructed as described above, when using this jig to adjust an integrated circuit having many pins attached to a printed board etc., the markings are counted as a basis weight when searching for the required electrode. The target electrode can be easily found.
以上説明した如く本発明によれば多数のピンを有する集
積回路素子を装着した電子回路の調整、保守を行う場合
の作業能率を向上させるうえで著しい効果がある。As described above, the present invention has a significant effect in improving work efficiency when adjusting and maintaining an electronic circuit equipped with an integrated circuit element having a large number of pins.
第１図は治具と集積回路素子を示す断面図、第２図は本
発明の実施例を示す斜視図べ第３図は本発明の変形例を
示す斜視図、第４図、第５図はさらに変形例を示す斜視
図。
１・・・・・・・・・集積回路素子、２・・・・・・・
・集積回路素子のピン、３・・・・・・・・・治具の接
触片。
４・・・・・・・・・治具本体、訃・・・・・・・・を
極。
６・・・・・・・・・切欠き、７・・・・・・・・・番
号、８・・・・・・・・・ライン、９・・・・・・・・
・ドツトマーク特許出願人 東洋通信機株式会社FIG. 1 is a sectional view showing a jig and an integrated circuit element, FIG. 2 is a perspective view showing an embodiment of the invention, FIG. 3 is a perspective view showing a modification of the invention, and FIGS. 4 and 5. FIG. 3 is a perspective view showing a further modified example. 1......Integrated circuit element, 2......
・Pin of integrated circuit element, 3... Contact piece of jig. 4......Jig body, butt... 6・・・・・・・・・Notch, 7・・・・・・・・・Number, 8・・・・・・・・・Line, 9・・・・・・・・・
・Dot mark patent applicant Toyo Tsushinki Co., Ltd.
Claims (4)
前記治具の表面あるいは側面の該治具に設けた電極に対
応する所要の位置にマーキングを施したことを特徴とす
る集積回路素子用治具。(1) In a jig for an integrated circuit element having a large number of pins,
A jig for an integrated circuit element, characterized in that markings are provided on the surface or side surface of the jig at required positions corresponding to electrodes provided on the jig.
設けた突起、凹陥あるいは印刷であることを特徴とする
特許請求の範囲（１）記載の集積回路素子用治具。(2) The jig for an integrated circuit element according to claim (1), wherein the marking is a projection, a depression, or a print provided on the surface or side surface of the jig.
とする特許請求の範囲（１１又はい）記載の集積回路素
子用治具。(3) The integrated circuit device jig according to claim (11), wherein the marking is a bin number (r% sign).
ことを特徴とする特許請求の範囲（１）。 Ｃ）又は（３）記載の集積回路素子用治具。(4) Claim (1) characterized in that the markings are applied at predetermined bin intervals. C) or the integrated circuit device jig described in (3).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58168818A JPS6059800A (en) | 1983-09-12 | 1983-09-12 | Jig for integrated circuit element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58168818A JPS6059800A (en) | 1983-09-12 | 1983-09-12 | Jig for integrated circuit element |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6059800A true JPS6059800A (en) | 1985-04-06 |
Family
ID=15875069
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58168818A Pending JPS6059800A (en) | 1983-09-12 | 1983-09-12 | Jig for integrated circuit element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6059800A (en) |
-
1983
- 1983-09-12 JP JP58168818A patent/JPS6059800A/en active Pending
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