JPS6059771B2 - electronic circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an electronic circuit with a current switch configuration that improves the rise and fall characteristics of an output voltage.

As shown in FIG. 1, the current switch connects the emitters of pnp transistors Tl and T2 to a constant current source 11 in common, and connects a load resistor R between the collector of the transistor Ti and the power supply line 1. The collector becomes the output terminal.

The input voltage V] is added to the base of the transistor Ti, and a reference voltage ■■s (another input voltage may be applied) is applied to the base of the transistor T2. When an inverted output is not necessary and only one output is required, the collector of the second transistor T2 is often connected directly to the power source without connecting a load resistor as shown in the figure. The operation is well known; when the input voltage Vi changes to H (high) or L (low) level compared to the reference voltage s, the transistor Tl turns on or off, and vice versa, the transistor T2 turns off or on, and the output Voltage ■o becomes L or H. By the way, as is clear from the structure of a bipolar transistor, the collector is larger than the emitter, etc., and has a large capacitance to the substrate.
Therefore, the output voltage V. The rising speed from L to H is determined by this time constant. The rise of the output voltage Vo can be made faster by reducing the load resistance R, but if this is done, an increase in current consumption is unavoidable even though the logic amplitude is the same. Therefore, the inventor of the present invention previously proposed a current switch having an ECL configuration in which a pnp transistor is used as a load-off (Japanese Patent Application No. 1983-446). An example is shown in FIG. As is clear from FIG. 1, in this circuit, the emitter-base path 5 of the pnp transistor T3 is connected between the collector of the transistor T2 and the power supply line 1
Insert the transistor T. The collector of the transistor Tl is connected to the collector of the transistor Tl. The other circuit configurations are the same as in FIG. Note that 12 indicates the negative conductor of the power supply line. To explain the operation, when the input voltage Vi becomes H level than the reference voltage ■S, the transistor T1 is turned on, T2 is turned off, and the output voltage VO becomes L level, and when the input voltage Vi becomes L level, the transistor T1 is turned off, and T2 is turned off. When the transistor T1 turns off, that is, when the output voltage VO rises, the transistor T2 turns on, and the emitter of the transistor T3 becomes high.
Current flows through the transistor T2 through the base path.
Transistor T3 is also turned on, and its collector current (β times the base current) flows through the rising transistor T1.
flows into the collector. This has the effect of charging the collector capacitance of the transistor T1, and the collector capacitance is rapidly charged as it is charged through the load resistor R1, and the rise of the collector potential and therefore the H level output voltage becomes rapid. Although this circuit speeds up the rise of the output voltage VO without reducing the load resistance R1 by adding the Pnp transistor T3, there are still points to be improved regarding the fall characteristics of the output voltage VO. There is. That is, when the transistor T1 is turned on, and therefore the output voltage 0 falls from H to L, it is necessary to discharge the charge stored not only in the collector capacitance of the transistor T1 but also in the collector capacitance of the transistor L. Of course, since the on-resistance of the transistor T1 is small, it is fully expected that this discharge will occur quickly. However, transistor T1 is off,
In the steady state with T2 on, resistor R1 and transistors Tl and T
The potential at the connection point A of transistor T3 rises to approximately 0V (assuming 11.=0V), while the base potential of transistor T3 rises to 1
Since the value of the Pn junction between the emitter and the base is one step down from 1=O■, for example -0.8■, the collector and base are biased in the forward direction and the transistor T3 is saturated. Therefore, a large amount of charge is accumulated in the junction capacitance between the collector and base of the transistor T3, and it takes time to discharge the charge. That is, the fall of voltage VO tends to be slow. The present invention reduces the collector capacitance of the Pnp transistor T3 shown in FIG. 2 by clamping its collector potential and causing it to operate in a non-saturated manner.

This realizes a current switch with improved output voltage rise and fall characteristics, which will be described in detail below with reference to the illustrated embodiment. FIG. 3 shows an embodiment of the present invention in which a Schottky barrier diode SBD is used as a clamping diode.

In this example, a diode SBD is connected in the forward direction from the collector to the base of the transistor T3, and the other configurations are the same as in FIG. 2. As mentioned above, the input Vi is L
When transistor T2 is on, transistor T3
The base potential l is -0.8V. At this time, the transistor T1 is off, but since the diode SBD is provided, a part of the constant current 11 (the remainder is the base current of the transistors T2 and T3) flows through the path 11-R1-SBD-T2. Therefore, the potential at point A decreases to 0V or less due to the current flowing through the resistor R1, but the value is determined by the diode SBD. For example, if the forward voltage of diode SBD is 0.4V, 0.4V is lower than the base potential of -0.8V.
Clamped to high -0.4V. In this way, a forward voltage (4) is applied between the collector and base of the transistor T3. Since a voltage exceeding 8.8) is never applied, the transistor T3 operates in a non-saturation region. Therefore, since the collector charge is small, the falling characteristic is improved, and when the input Vl is changed from L to H, the output 2O changes rapidly from H to L (the collector charge described above is quickly discharged). Note that the potential at the output terminal O when the level is high is higher by the forward voltage of SBD due to the collector level of the transistor T2, but the collector level of the transistor T2 has nothing to do with the output level and is as shown above. A high level of VO is sufficient.

FIG. 4 shows another embodiment of the present invention in which a normal Pn junction diode D1 is used as the clamping diode.

In this example, the Schottky barrier diode SBD in FIG. 3 is replaced with a Pn junction diode D1, and a shifting resistor R2 is inserted between the base of the transistor T3 and the cathode (point B) of the diode D1. The Pn junction diode D1 has a forward voltage of 0.8V as well as between the collector and base of the transistor T3. Therefore,
Although it is difficult to avoid saturation of the transistor T3 even if a Pn junction diode is simply used instead of the SBD in the circuit of Fig. 3, it is possible to reduce the saturation of the transistor T3 by lowering the potential at point B using the resistor R2 as shown in Fig. 4. Since the potential at point A also decreases, transistor T3
saturation is prevented. For example, 0.4V by resistor R2.
If a voltage drop of
Even if the voltage is clamped to a high potential of -0.4V, a result similar to that shown in FIG. 3 is obtained. FIG. 5 shows a different embodiment of the present invention in which a resistor R3 is inserted between point A in FIG. 3 and the diode SBD to increase the amplitude of the output VO.

When the output VO is H, that is, when the transistor T2 is on, a current flows through the path 11-R1-R3-SBD-T2, and the collector of the transistor T3 is clamped to a desired potential by the diode SBD. At this time resistance R
Because of the potential difference of 3, the potential at point A does not fall to the collector potential of transistor T3, so the H level of output VO is kept high. This amplitude increasing resistor R3 can be similarly applied to the circuit shown in FIG. When a Schottky barrier diode is used as a clamp diode, there is no need for a shift resistor, which simplifies the circuit configuration and is also advantageous in terms of element formation.

However, it is generally difficult to provide a Pnp transistor with an SBD that clamps the collector potential with respect to the base potential. However, this can be easily implemented if the transistor is of lateral structure. That is, FIG. 6 shows an example of an element structure in which a Pnp transistor T3 and a Schottky barrier diode SBD are formed on the same land, where 2 is a p-type silicon semiconductor substrate, 4 is an n-type layer formed on the surface thereof and becomes a base region; 6 and 8 are p-type emitter and collector regions formed on the surface of the n-type layer 4; 10 is an inter-element isolation region;
2 is a surface insulating layer, and 14E, 14C, and 14B are an emitter electrode, a collector electrode, and a base electrode that are in ohmic contact with the regions 6, 8, and 4, respectively, and these constitute a Pnp transistor T3. In such a transistor structure, when the collector electrode 14C is brought into contact with a part of the n-type layer 4, a Schottky barrier diode SBD is formed there, and the circuit becomes equivalent to the circuit shown in FIG. According to the present invention as described above,
This has the advantage of improving the operating characteristics of the ECL-configured current switch and making it possible to speed up not only the rise but also the fall of the output voltage.

[Brief explanation of the drawing]

Figure 1 is a circuit diagram showing a general rent switch;
The figure is a circuit diagram of a current switch with improved output voltage rise characteristics, Figures 3 to 5 are circuit diagrams showing different embodiments of the present invention, and Figure 6 is an element structure showing the main part of Figure 3. It is a diagram. In the figure, Tl and T2 are the first and second transistors, T
3 is a Pnp transistor, SBD. ．． Dl is a clamp diode, R1 is a load resistance, and 11 is a constant current source.

Claims (1)

[Claims] 1. The emitters of the first and second npn transistors are commonly connected to a constant current source, the collector of the first transistor is connected to the power source via a load resistor, and the output is taken from the collector, and the The collector is the third pnp
In an electronic circuit having a current switch configuration connected to a power supply through a transistor, the emitter of the third transistor is connected to the power supply, the collector is connected directly or through a resistor to the collector of the first transistor, and the base is connected directly to the collector of the first transistor. or to the collector of the second transistor via a resistor, further connect the anode of the diode to the collector of the third transistor, and connect the cathode of the diode to the collector of the third transistor.
An electronic circuit characterized in that it is connected to the collector of a transistor.