JPS605976B2 - Methods and devices for organizing control stores - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to the structure of a control scheme for a digital electronic computer, and in particular for a microprogram computer in which various operations are performed under the control of a sequence of microinstructions (or microprograms).

The microinstructions are executed one after the other in a fixed order, and when the instructions that make up the program are executed, so-called elementary or original instructions call a sequence of microinstructions or microroutines. Data processing systems include at least one processor that receives, manipulates, processes and reconstructs data under the control of instructions, in this case microinstructions forming a microprogram. Traditionally, control schemes have been formed by logic networks made up of active and passive components arranged in a certain topographical pattern.

Therefore, the logic control circuitry is difficult to change, and changes have to be made by physically changing the circuitry. In order to obtain information that allows operations to be carried out to control the processor by means of the control memory, only one input operation can be performed and the logic circuitry can be replaced by a storage unit whose contents can be changed. The idea of microprograms makes it possible to explore the form of sequences of basic control signals to control the data processing methods, and to perform the functions of processing fixed or dynamic data.

These control signals are divided into "words" and placed in a control memory to represent states that control the flow of information between monitoring actions and sequential changes in signal states. This method of organizing the data processing scheme has the following drawbacks.

The number of microinstructions that are prepared from the beginning within a computer is limited and are tightly coupled to basic instructions. Changing or updating microinstructions requires changing the control store, which store is generally formed of a read-only store. However, it is necessary to perform operations to enable more efficient microinstruction execution than is initially provided. The selection effects required within each scheme require the existence of different microprogram shapes, and the organization of microprograms within the same scheme, i.e. the position of each microprogram, changes over time as a function of the action. I have to.

Three solutions are currently in use.

The first consists in creating a group of specific microprograms for each shape. The entire microprogram pair then needs to be reproduced for each shape. Since the operational nature of blocks of microinstructions does not change, what is changed is their location, which creates considerable problems in addressing and arranging microinstructions to make connections.
A second solution is to create each block of microinstructions to occupy a fixed location within the control store.

In this case, positions corresponding to unused selection items are left unoccupied, which results in wasted space. This solution requires a general layout for all microprograms, which is inflexible. Moreover, the range of connecting addresses should be large enough to span the entire control store, which wastes even more space as the useful content of the microprogram is reduced. The control store used to overcome this drawback should be an easily changeable read/write memory and be associated with a "dedicated memory for discussion."

Although this solution is effective, it is cumbersome and can only be used on high-performance computers. In a microprogrammed computer, microinstructions constitute one of the constant elements; in order to execute an instruction in a program, it is necessary to operate a sequence of microinstructions stored in memory, and these microinstructions performs control operations within the processor.

Microinstructions written by a programmer in a high-level language such as FORTRAN or COBOL allow several so-called basic instructions to be executed in a fixed order.
The object of the invention is to eliminate or reduce the above-mentioned disadvantages so that the control memory can be used rationally and its shape can be easily changed to other shapes.

According to the invention, the control scheme for the processor in the data processing scheme, which includes a main store, a control store and an arithmetic stage, is characterized in that an area of the main store is reserved to hold a microprogram. The object of the invention is also an addressing method that allows two store areas containing microprograms to be reached. Yet another object of the invention is to be able to protect microprograms loaded into the main store. Another feature of the invention is that the control method is that the microprogram addresses are segmented addresses. Initially, dividing the main store into specialized regions was used to separate particularly computational software from user programs.

These two parts of the store are limited by boundaries that cannot, in principle, be crossed by the user's program as far as reading is concerned, and only information relating to the calculation method can be read.

Because of this, any attempt to read anything into this area of the store resulted in an "ABORT" signal being issued. The current scheme has a ring protector (described in other applications), there is no good reason to restrict the calculation scheme to special areas of the store, and the details of the information about each process are separated from each other by safeguards. access to certain memory segments is strictly controlled. Conversely, the area containing the microprogram must be inaccessible by the user's program. Another feature of the invention is that the store is separated into two parts, each part is separated by a comparator and a hardware register, and the register has a limit separation value, so that the microprogram area can be You can only humble yourself in it.

In one scheme using the invention, all operations of the processor are performed through a microprogram.

These microprograms are retrieved from the control store at each process step to control the logic of the processor and are sequences of control "words." A word is made up of, for example, four octets (32 bits and 15 parity bits) and is sent to different points within the processor, such as the address control unit ACu, the operation unit SPu, the arithmetic logic unit ALu, and the store control unit RC. Simultaneous operations may be controlled. In reality, the main store is formed by four units, each with a capacity of 25 octets, and the dedicated control store has a maximum capacity of 12 octets, leaving an area of the same size in reserve for the firmware in the main store. . The most important microinstructions are contained in one or more read-only stores.

Conversely, if the microinstruction is used relatively infrequently and the access time is relatively unimportant to the overall process time, it is better to place the microinstruction in a central store, which may be slow but The price can be lower than if it is in a store dedicated to ordering.
For example, in a data processing system used for administrative purposes, microinstructions related to scientific application options may be provided to the main store. Special process firmware (FIR
The same applies to MWARE). Microprograms are about three times slower when they are in the main store than when they are in the read-only store. In general, it is an object of the invention to make firmware deployment extremely flexible and effective.

Other features and advantages of the invention will become apparent from the following description with reference to the accompanying drawings. One of the objects of this invention is to create a variety of shapes without having gaps in the store containing the microprogram and without changing the content of the microprogram at the point where each module meets. is called “translatability”.

In microprogram, data processing systems, each component can react with a set of so-called basic instructions, sometimes called machine language.

This set of instructions has corresponding system-specific microinstructions that control the operation of each stage of the machine. These microinstructions are written for a specific scheme and are called NATIVE MODE microinstructions. It is clear that several sets of microinstructions may be written based on a complete set of basic operations. The totality of this basic action may be called the "internal DOCTOR". In fact, it forms an interface between software and firmware. As mentioned above, native mode microinstructions form a special group, responsive to those specified by the internal doctor, stored in the control store, and independent of its topography. The table in Figure 1 (
Table) STI shows the structure of this control store and consists of blocks or segments A, B, C, D, E, F formed by dividing microinstruction words into families. Each segment is assigned a number called the original or base of the segment. The size of the segment is a secondary item of information, allowing addressing to be controlled by the microinstruction itself, but since the microinstruction's address is determined entirely arbitrarily at the base and offset within the segment, this No solution has been adopted.
Table STI in a store other than the control store contains the bases of all segments A, B, C, D, E, F. This table is loaded when the system is brought into its initial state. This method works with the software specified by the internal doctor after being initialized and segments A, B, C
, D, B, and F. However, data processing methods tend to be used by customers who perform fairly specific tasks, and it is clear that it is uneconomical to give customers machines that can perform tasks that they do not use. . However, conditions change over time. Furthermore, the customer purchasing the machine may already be using other forms of data processing. Therefore, you must choose the appropriate software. However, converting one software to another requires considerable work and may take years to accomplish. So what the customer can do is change the emulate mode,
That is, controlling the new machine with the old software and using modes and hardware from other patent applications. For the reasons mentioned above, the structure of the control store is shown in Table S in Figure 1.
Table ST0, i.e. AI, E,
If segments D, C, B, F (G) are to be used, a certain number of segments must be shifted and segment A must be replaced by segment AI.

In the microinstruction addressing mode that is a feature of this invention, there is no problem in shifting one segment relative to another. The table of segments with the basic base for the fact control store can be changed to the desired shape. The main store's segment table is a discussion/write store, . Given that the microsegment segment is a discussion-only store (control store), the shape of the discussion-only store can be changed by changing the discussion/write store. This has considerable advantages as the shape in question can be changed simply by physically moving the plate containing the segments. According to another feature of the invention, the segment or segment A is changed by physically changing the board in the control store, or by reading block A instead of block AI if block A is in the main store. .

This can be easily done by reading a disk memory or a set of punched cards. Table ST
is in the form of table STO in the central store. One object of this invention is to perform shape changes very quickly so that the system can perform multiple tasks, the tasks differing as a function of the instructions, and
Commands are conveyed as various words or groups of different commands.

The base of the segment called in the program in FIG. 1 is provided in register MB, which always contains the base of the last segment to which the microinstruction is passed.
Register MB is also shown in FIG. 2 and shows how addresses are formed. In principle, the table ST should be recorded in the main store, but for practical reasons regarding the hardware structure, the beginning of the table is contained in the work store (SPu), which is stored by a very fast register bank. It is formed. Each segment base takes 8 bits, or 1 octet, in table ST. The table ST is changed when the shape changes. A problem table is generated for each shape of the scheme. In this way, the content of the micro-work is independent of the location of the address.

On the one hand, different commands (n equals 4 and m from 1 to 4)
On the other hand, given the number of each shape resulting from different choices within each code, it is impossible for the microprogram module to make each shape as a function of the addresses of neighboring modules. The content can be made location independent in various ways, especially by segmenting the microprogram. Segmentation is the separation of a microprogram into segments.

A segment is a sequence of microprogram words, and all pairs can be shifted by translation without changing their content. A segment is defined by its original or base address and its size.

Absolute address mode' whose base address is simply 0
It is. All interrupts are directed to absolute mode addresses. In this case the contents of register MB are not taken into account. In principle each segment can have any base address and be of any size, but these are chosen to be multiples of some value to make bit addressing economical.

The value is called "PAGE". A segment is located at an address that is a multiple of a page, and its size is a multiple of a page. (The maximum number of segments is limited only by the maximum size of the entire microprogram, the address part. A page should be small enough so that no space is wasted (at the end of the page) as a result of subdivision. should be.

FIG. 2 is a table showing how microprograms are addressed, which is done by microprogram words and not by position numbers. The absolute address for a shape in a segmented address is obtained by adding the base of the segment and the offset within the segment. The base address of the segment is given in register Mold1. The segment base value is added to the page number in adder 2. The page number is given by the first eight bits of the address in address register RA4. The output of adder 2 is connected to address calculation stage 3. This stage 3 also receives an offset within the segment, the offset being in register RA4 (last 8 bits of address RA). The base contained within register MBI comes from the segment table described above. Here the address of the base of the segment is contained in a table stored in a microprogrammed portion of the main store, and it is necessary to change the segment table to obtain a new configuration of the system without hardware manipulation. This double addition gives the possibility of translating a segment and therefore making the contents of the segment independent of its position in the control store (1) and at the same time independent of its position by other segments (b) with different configurations. It allows. Easy translation of such microprograms (translatability of microprograms is considered to be completely new).Other features include effective protection of data contained in limited segments of the central store and reduction of the size of microinstruction address words. Register 4 is made from several pages with the current relative address, i.e. the address of the microinstruction, and the offset or distance of the instruction from the origin of the page,
This position is called a "concatenation."

Address calculation stage BA3 calculates the address of the next instruction and writes it into register NEXA7. This address is moved to register 4 and the microinstruction responsive to this address NEXA in firmware F is loaded into supervisory register RD9 where it is effectively executed. In normal operation, stage BA3 adds 1 to the current address to obtain the next address, and the operation continues as long as the page or segment is not changed. When a page or segment is changed, a new address is calculated by adding the base of the segment and the relational address within the segment. The calculations performed in stage 3 cause sub-microprograms or sub-microroutines to perform. In this case, the address to be returned into the main sequence, ie the next address, is stored in the register SM5. The microprogram is returned to the address in register SM when the submicroprogram is executed. Interruption by one signal while the microprogram is being executed is connected to register 7 or address connection stage 3. In this case, the microprogram in the IM 6 records the address of the microinstruction that would have been sent if it had not been interrupted, so that it is possible to return to this address. Interruptions occur, for example, when accepting data transmitted from a peripheral device. According to Makoto's invention, stage goods represent a control store made up of a discussion-only store and a portion of the main store. The microprogram word contains connection instructions, so that every microprocessing call returns from one segment to another and the original segment to register SM5, and can be done at as many levels as desired.

It is likewise possible to return to the separation point (register m6) after an interruption. It is also possible to have the same overlapping structure of microprocessing calls as suspended levels within suspended microprograms. As an example, the following format is already in use: Machine 1 Machine 2 Page size 1 no 2 km lk octets octets (2 pages of machine 1) 16k of largest segment o=32 16k o=16=critical point
Page Maximum page capacity 215
Words = 217 words 216 words = 256k28k octets In machine 1, the intra-page address is formed with 7 bits, and in machine 2 it is formed with 8 bits.

There are two types of connections: [a - Connections within a page, this is done only to absolute addresses, since this is not related to the position of the segment.

'b} Connections outside the page are made in consideration of the contents of the register MB.

These connections are described in the manufacturer's microprogram language manual.

Conditional or unconditional connections are generally of the two types mentioned above.

Only very specific connections (multichannel) have destinations outside the page (destinations are within several pages) that are always used. The purpose of this is to make it easy to locate the microprograms that follow these connections. According to the invention, the method for organizing microprograms is characterized in that the microprograms are contained in two types: a special store and a main store.

This feature provides quick access to special stores (for better performance) and flexibility in how microprograms are loaded into the main store.

These microprograms can be provided by any peripheral device. This arrangement allows microprograms to be tested before being recorded in a particular store, thereby eliminating defects in the microprograms. Microprograms may be placed partially or completely in a discussion-only store, which allows the use of non-durable microprograms.

Having a non-durable microprogram is connected to the initial state of the machine (BOOTSTRAP) and the stability or intermediate fault test of the machine.

Segmentation techniques are suitable for dividing hardware locations between special stores and primary stores. In practice, you can start with a certain value on the segment base, put the segment in the main segment, and put anything below this value into a special store. Segmentation can be facilitated because translating a segment from one store to another simply requires changing the base address in the segment table. A segment is not allowed to be in two stores simultaneously or partially, as this makes no sense from an operational point of view.

FIG. 3 is an arrangement showing the principle that a microprogram can be called for both lecture and discussion. As previously explained, address register RA4 contains the current address in register RD9, which is the address of the instruction being executed.

When an instruction is executed, register RA is given the address of the next microinstruction. This address is calculated in the manner described with respect to FIG. That is, the result is first adding the base and page numbers and then offsetting within the page. Table ST loads register MB and contains an information bit or combination of information bits specifying whether the segment for which invocation is desired is in a particular store or in the main store. This bit appears again in the absolute address and is applied to register RA after being calculated in stage 3 (FIG. 2). The bit in question is a structurally large bit, ie, the first bit from the left of the address. If this bit is, for example, 0, the microinstruction is in the issue-only store, and if it is 1, the microinstruction is in the main store. The bits are provided to a special logic circuit 12 for a call to the main store 11. As a result of the bits or bit combinations being decoded in special logic circuitry 12 for access to the main store, instructions whose addresses are in register RA4 are retrieved from the main store and read along the 32 bit channel. Assume that the decode is applied to monitor register RD9 to indicate that the instruction is in the main store. In the opposite case, the instruction is retrieved from the special store 13, which is always addressed for practical reasons. 32-bit instructions are recorded in supervisory register 9.

The address at the output of register RA is multiplexed by multiplexer 10. The simultaneous existence of programs and microprograms within the main store creates a problem of relative location, which is the same as that of the user system and the application program.

In reality, application programs should not be able to change data in microprograms that are an inherent part of processing and machines. Microprograms in the control store cannot be changed unless the program has access to this store. This is possible because absolute addresses are blanketed within the main store. A division is therefore made between the hardware zone and the software zone. This separation is called the BAR or base address register. Hardware is included in the zone extending from 0 to BAR, and software is included in the zone extending from BAR to MS (main store limit). Software access is possible between the BAR and the MS call and is not allowed outside. This disturbance is performed by special circuitry. This particular circuit is shown in FIG. 3 and consists primarily of a BAR register 15 and a barricade comparator 16. Main store 11 may be addressed from software or hardware. This mode of addressing was previously described and is not subject to control. On the other hand, addresses sent directly from software or indirectly through a table are compared with the address value contained in the BAR register 15, and access is possible only when the address value is greater than the BAR value. This is especially the case for retrieving data from the main store 17, reading programs 18 and accessing channel programs 19. In this way the user program does not have access to the hardware area of the main store. When the address communicated to the main store is less than BAR, the instruction for this address cannot be reached and a contingency signal 14 is issued. It is clear that this invention is not limited to the embodiments described above, and that various modifications can be made within the scope of this invention.

[Brief explanation of the drawing]

Figure 1 is a layout diagram showing the principle by which the control store is organized, Figure 2 is a layout diagram showing how the segment addresses of the microprogram are formed, and Figure 3 is a layout diagram of the equipment that directs and protects the firmware. be. 1...Register, 2...Adder, 3.
...Stage, 4, 5, 6, 7...Register, 8
"""Stage, 9...Monitoring register, 10...
...Multiplexer, 11...Main store, 1
2...Logic circuit, 13...Special store, 1 4
...Signal, 1 5...BAR register, 1
6... Comparator, 17... Main store, 18...
...Program, 19...Channel program. FIG-I FIG-3 FIG-2

Claims (1)

Claims: 1. In order to organize a control store containing all microprograms of a microprogrammed data processing device capable of operating with different instruction codes, said data processing device is configured to Reads included in /
The control store includes at least one read-only store and a control processor connected to a peripheral device and controlled by microinstructions contained in the control store. The microinstruction is divided into a group of segments, each segment is divided into pages, and the absolute address of the microinstruction in the control store is the base of the segment plus the page origin. , and the resulting result is obtained by binding the offset of the start of the microinstruction relative to the start of the page. 2. A control store according to claim 1, characterized in that the base of the segments is contained in a table provided in the main store when the data processing device is initialized. How to organize. 3. The method of claim 2, wherein each table in the main store has the shape of a corresponding segment in the control store. 4. A device for carrying out the method according to claim 1, comprising: a register connected to an adder for storing the base of the segment and receiving the address of the page from the address register containing the address of the process being executed; an address calculation stage connected to said adder on the other hand and an address register for calculating an absolute address as a result of the data combination, the output of said address calculation stage being a microinstruction following the microinstruction being executed; Apparatus for organizing a control store, characterized in that it is connected to a register for storing the address of the control store. 5. In an apparatus for carrying out the method of claim 1, the address of the instruction to be executed is in an address register, which address register is connected to a special logic circuit for accessing the main store. . Apparatus for organizing a control store, characterized in that at least one bit of an address is decoded within said circuit, said address being passed simultaneously to said main store and to a special read-only store. 6. A data processing system comprising a read/write main store, a special read-only store, an operation stage, and a peripheral, the special read-only store containing microprograms grouped into segments. In a method for controlling central processing of a device, when said data processing device is brought into its initial state, a microprogram is provided to said main store with a segment table, and data input/output operations and processing thereof are performed by said store and A method for controlling the central processing of a data processing device, characterized in that it is controlled by a group of microprograms contained in said special read-only store.