JPS6058479B2 - How to display characters, etc. - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a method for digitizing, for example, characters, numbers,
The present invention relates to a method for displaying characters and the like by displaying graphic signals on a cathode ray tube or the like.

Generally, when a dotted character or graphic signal is displayed on a television screen or the like, it is displayed with jaggedness peculiar to digital characters.

In order to make such jaggedness, that is, bit change points, less noticeable, there is a method of increasing the clock frequency when converting into dots to obtain finer resolution, or a method of representing one pixel with several bits and converting it into multiple values. is used. However, this method increases the capacity of the refresh memory for display and the capacity of files for storage, which leads to a decrease in processing speed and an increase in costs. The present invention eliminates so-called "blurring" caused by surrounding information.
By applying the above operation, it is possible to eliminate the jaggedness peculiar to digital characters even if a refresh memory with a relatively small capacity is used.

FIG. 1 shows an embodiment of a device that implements the display method according to the present invention.

In the figure, 11 is an input terminal for the signal to be converted;
12 and 13 are shift registers for delaying one horizontal period, 14, 15, and 16 are shift registers for taking out two specific bits, and 17 is a shift register for applying weights n1, N2, and n1 to each bit. After
An arithmetic circuit 18 that calculates the sum outputs ゜゜1r if the calculation result of the arithmetic circuit 17 is larger than a predetermined value N3, and outputs "゜00゛" if it is smaller than a predetermined value N4. In the case of , there is a conversion circuit that outputs 0r to 10, and 19 is an output terminal for the converted signal.
In FIG. 2, a shows a state in which a signal to be converted applied to the terminal 11 is displayed, and b shows a state in which a signal after conversion is displayed.

Note that 21a to 27a and 21b to 27b indicate scanning lines, respectively. Fig. 3 shows a device to which the output of the device shown in Fig. 1 is added and further corrected to produce a smooth display. 31 is a refresher that stores one field of information for screen display.・A memory, 32 is a delay line consisting of a shift register for delaying the image signal output from the memory 31 by one horizontal period, and 33 is a switch for switching between the delayed signal and the original signal for each field. circuits, 34 and 35 are shift registers for serial-to-parallel conversion of image signals; 36 is a circuit that converts the output signals of the conversion circuit 34 and shift register 35 into predetermined values; 37 is a D/A converter; 38 is a An image signal delayed by one horizontal period, 39 is delayed by . 40 is a clock for driving the delay line 32 and shift registers 34 and 35 for serial/parallel conversion; 41 is a command signal for switching the switching circuit 33 for each field; The signal that does not pass through line 32 is serially transmitted, and the signal that passes through delay line 32 in even fields is
The signal is supplied to the parallel conversion circuit 34.

42 indicates a D/A converted output signal.

Figure 4a shows the output when no correction is performed at the video signal output section, and the output in the odd field is 51c.
, 53c, and 57c, and outputs in even fields are shown at 52c, 54c, and 56c.

The display memory is for field screens, odd fields,
Exactly the same signal is output for both even fields. In FIG. 4b, 51d, 53d, and 55d show the corrected outputs in the odd field, and 52d, 54d, and 56d show the corrected outputs in the even field. Next, the operation of the above embodiment will be explained.

First, in FIG. 1, a signal input from the input terminal 11 passes through the shift register 14 to specify 2 bits, a signal delayed by one horizontal period passes through the shift register 15 to obtain specific 2 bits, and a signal further delayed by one horizontal period is converted to two specific bits. Take out two specific bits through the shift register 16,
These bits are El, e2, e3, e,, e5, e6
shall be. As shown in FIG. 2A and b, e1 to E6 are E3 and e4 of line 23a corresponding to E7 and e8 of line 23b for which a signal is to be created, and line 22a (7) El corresponding to the upper and lower 2 bits thereof. , e2 and E5, e6 of line 24a. This signal is applied to the arithmetic circuit 17, and each bit is multiplied by previously determined weights n1, N2, n1 to obtain the sum shown in the following equation. Here, e1 to E6 are “0”
'' or 6°r'', and the values of n1, . . . are given as n1=1 and τ=3, for example.

This calculation result is added to the conversion circuit 18, and the calculation result is ? If m is larger than the predetermined value N3, it is determined as ゜1゛;
If the value is smaller than the predetermined value, it is determined as "00", otherwise it is determined as "01" or "10", and E
7 and E8 are determined. For example, the values of N3 and N4 are N
3=7 and N4=2. When two bits are completed in this way, the next two bits are used to determine the pattern.
That is, every two bits are judged and all modified patterns are determined. In this way, the pattern shown in FIG. 2a is converted into the pattern shown in FIG. 2b, which is sequentially stored in the refresh memory 31 shown in FIG. 3 to form one screen of information.

If the contents of this refresh memory 31 are displayed, the jaggedness of the displayed characters will be improved due to the visual integration effect. In this embodiment, a field memory is used as the refresh memory 31, and when displayed as is, the fourth
The display pattern shown in the figure is obtained, but smoothing correction is further performed to obtain the display pattern shown in FIG. 4b. The operation will be explained below. Display refresh memory 3
1 has a configuration of 1024 dots in the horizontal direction and 256 lines in the vertical direction, and the output from the display refresh memory 31 is applied to the delay circuit 32 for one horizontal scanning period. This delay circuit 32 is constituted by a 1024-bit shift register, and applies 1024 clock pulses 40 to delay one horizontal scanning period. Signal 3 delayed by 1 horizontal period
8 and the undelayed signal 39 are applied to the switching circuit 33, switched every field, and applied to the serial/parallel conversion circuit 34.

These signals 38 and 39 are shown at 51c and 53 in FIG. 4a.
c or 53c and 55c... These signals are output by serial/parallel conversion circuits 34 and 35 as signals temporally shifted by one bit, and are applied to a conversion circuit 36. The signal applied to the conversion circuit 36 is 53c or 55c for odd fields.
・Only the signal is both serial ●Parallel conversion circuit 34
and 35 to obtain an output of 51d or 53d. In the even field, the signal 52c in FIG. 4a is applied to the serial-to-parallel conversion circuit 34, and the undelayed signal 39, that is, 54 in FIG. 4a, is applied to the serial-to-parallel conversion circuit 35. The outputs of the serial/parallel conversion circuits 34 and 35 are signals temporally shifted by one bit, and correspond to A1 to A4 and inputs shown in FIG. 5, which shows the outline of the operation of the conversion circuit 36, respectively. The conversion circuit 36 outputs the final output E based on the signals A1 to A1.
Determine. That is, to obtain one dot of information EO, information A1 to A8 above and below it are used. For example, A1~
If the signal of ~ is “1111111r”, “゜11r” is output as EO, and the D/A converter 37 outputs “゜7”.
Convert to the level of ゛.

The contents of the conversion circuit 36 are determined so that if A1 to A8 are ゜゜00000000゛, it is converted to the level ゜"0゛, and if A1 to A8 are ゜10101010゛, it is converted to the level ゜゜4゛. The result is a smooth pattern as shown in Figure 4b. Note that as the conversion circuit 36, a read-only memory ROM that operates at high speed can be used. As is clear from the above description, according to the present invention, the portion of a pattern such as a character to be "blurred" can be blurred by, for example, "10" or "0"
By converting to a pattern such as 1゛, it is possible to remove the jaggedness peculiar to digital characters, and it is possible to display characters, etc. that are easy to read.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of a device using the method for displaying characters, etc. according to the present invention, FIGS. 2A and 2B are waveform diagrams of signals before and after conversion in FIG. 1, and FIG. The figure is a block diagram of a device for further smoothing the configuration in Figure 1, Figures 4A and b are signal waveform diagrams before and after smoothing correction according to Figure 3, and Figure 5 is the pattern conversion of Figure 3. FIG. 3 is a diagram for explaining a circuit. 12, 13... Shift register for one horizontal period delay, 14, 15, 16... Shift register for taking out 2 bits, 17... Arithmetic circuit, 18.
... Conversion circuit.

Claims (1)

[Claims] 1 In a display method for characters, etc. that creates signals for displaying dotted characters and figures, 2 bits of information on a certain line and 2 bits of information on each line before and after the 2 bits, respectively. The weights of n1, n2, and n1 are given and added, and the added values are predetermined values n3, n4.
, the 2-bit signal is obtained by determining "11" when the value is larger than n3, "00" when the value is smaller than n4, and "10" or "01" otherwise. 2
A method for displaying characters, etc., characterized by creating a signal to be displayed bit by bit.