JPS6057924A - Manufacture of semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To form a conductor wiring finely on a shallow P-N junction by forming an alloy layer of a semiconductor and a first conductor thin-film and a second conductor thin-film on a semiconductor substrate and selectively removing the second conductor thin-film by utilizing the difference of etching rates. CONSTITUTION:A buried region 31, and epitaxial layer 32 and SiO2 films 33, 34 for isolation are shaped on a P type silicon substrate 30. A collector region 35, a base region 36, an emitter region 37 and a graft base region 41 are formed. An Mo film 42 and an SiO2 film 43 are formed, and MoSi2 alloy layers 44-46 are shaped through heat treatment in N2 gas. An Al film is formed, and conductor wirings 47-49 are formed through selective etching. When mask alignment is displaced, the emitter region 37 is etched even through over-etching because the ratio of the etching rates of Al to MoSi2 by CCl4 gas is approximately 1.5, an emitter-base juction is not exposed, and a distance between the emitter and the graft base can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a method for manufacturing semiconductor integrated circuits, particularly semiconductor integrated circuits in which fine integrated wiring is formed.Conventional structures and problems thereof are shallow. When forming a semiconductor integrated circuit having a p-n junction, such as a high-speed bipolar transistor, silicon
: Polycrystalline silicon between the board and the 2nd and q-body wiring.
) form a film. A detailed example is shown in FIG.

An n4 type buried region 2 is formed in a p type silicon substrate 1, and an n type epitaxial layer is formed. Then, an isolation region 4 and a collector region 6 are formed by the S102 film.

and emitter region 6. An active base region 7 is formed.

Then, on the base, emitter, and collector contact regions, a polySt film with a thickness of about 0.37ttn 8°9.1
form 0. Thereafter, a graft base region 11 is formed. Then, wires 12, 13 and 14 are formed.1
5 is an S102 film.

FIG. 2 shows an enlarged view of the emitter/base region that is removed during the manufacturing process of the structure shown in FIG. )(distribute+t6!'s"'
i I'<3: - CCl2. for etch. A gas such as BCl2 is used.

However, since the etching gas for forming p,t Fe+iI+ has a high etching speed for the polySi film, if the mask alignment of the At wiring is misaligned and the polySt film 9 is exposed, as shown in FIG. The emitter region 6 is also etched to form the four portions 2o. This exposes the emitter-base junction and deteriorates transistor characteristics. Therefore, the edge 23 of the M wiring 12.13 is lower than the edge 21.22 of the poly Si films 8, 9.
．． 24 is approximately 0.5111n, and poly
The At wiring overlaps the Si film. In this way, even if mask misalignment occurs, the poly-Si film will not be exposed. Then, since the distance y between the At wirings 12 and 13 needs to be 1.5 to 2 μm or more, adding the overlap amount The area increases and the base-collector capacitance increases.

After forming the twisted emitter 6, a polySt film 9 is formed.
Since there is a natural oxide film 23 on the surface of the emitter region 6, the emitter resistance becomes large (L, resistance 17+): (There is a problem that the fluctuation range of the target becomes large.

Furthermore, since the emitter diffusivity is shallow, the poly3i film 9
The Al--Si alloy must be formed so that it does not reach the eminent, intermediate, and base combination. However, as shown in Figure 1, the thickness is about 0.3μ)? ? of polys
+ A step l occurs due to the films 8, 9, and 10, resulting in a fine AL
It becomes difficult to form a pattern.

OBJECTS OF THE INVENTION It is an object of the present invention to provide a method of manufacturing a semiconductor integrated circuit that can form fine conductor wiring on a shallow pn junction without complicating the process.

Structure of the Invention In the present invention, a first conductive thin film is formed by exposing a predetermined region of a semiconductor substrate for bonding to a conductive wiring. Then, by heating, an alloy layer of the semiconductor and the first conductor thin film is formed on the exposed 1'-conductor substrate. Thereafter, the first conductor thin film on which no alloy layer was formed was removed, and the substrate was removed! Second, a second i, PI3 ki • body thin film is formed. Thereafter, the second conductor thin film is selectively removed using an etching gas or etching liquid that etches the alloy layer at a slower etching rate than the second conductor thin film, thereby forming a conductor wiring. Manufacturing a semiconductor integrated circuit. It's a method.

DESCRIPTION OF EMBODIMENTS An embodiment in which the present invention is applied to a bipolar LSI is shown in FIGS. 3A to 3D.

First, an n+ type buried region 31 is formed on a P type (111) silicon substrate 3o, and an n type epitaxial layer 32 is formed.

And S i0 for isolation between elements and isolation between base and collector
Two films 33 and 34 are formed. And Shin-shape Flexor Area 3
6. A base region 36 with a diffusion depth of approximately 0.4 μm, an emitter region 3 with a depth of approximately 0.2 μ'nr after ion implantation.
form 7. and Si3N with a thickness of about 0.111rn
4 films 38f: Formed. Then, the photoresist film 39 is left in a region other than the emitter/base separation region, and the Si3N4 film 38 and n+ type emitter region 37 are etched using the photoresist film 39 as a mask (FIG. 3A).

Next, the exposed silicon substrate in the emitter/base isolation region is oxidized to form an 8102 film 4° with a thickness of about 0.2 μ7+1. Then, a graft base region 41 is formed by implanting boron ions. Then, the Si3N4 film 38 is removed. After that, a thickness of approximately 0.031t was formed by sputtering.
tn MO film 42 is formed. Furthermore, on top of that, the thickness is approximately 0.
．． A 3102 film 43 having a thickness of 1571 m is formed by the CVD method (FIG. 3B).

Then, when heat-treated in N2 gas at about 6o○℃, the exposed graft base 41, emitter 37, and collector 35 are exposed.
Mo 312 alloy layer 44. is made of silicon and Mo film 42.
45.46 are formed (Figure 3C).

Then, the substrate was immersed in an H2O2 aqueous solution (at 11t, M
The O film 42 is removed, and the Mo Si 2 films 44, 45 .
46 remains unremoved. Then, an A7 film or an At-8t alloy film with a thickness of 1/Jtn is formed by a lithography method, and selective etching is performed using the photoresist film as a mask to form the base conductor wiring 47. For Emi'7ta? , 9 body wiring 48. A collector Z and FT body wiring 49 are formed.

Emitter, graft base distance [reducing t/(
7. First, the distance m between the base conductor wiring 47 and the emitter conductor wiring 48 is made to be the same as the distance between the emitter and the graft base (FIG. 3D).

If the mask alignment is misaligned in f11, CCt
For example, if At is dry-etched using the 4th gas,
As shown in the figure, the conductor wiring 48 does not completely cover the surface of the emitter 37 and a portion of the MoSi2 film 45 is exposed. However, the etching rate of At using CCt4 gas or active sputter etching
Since the etching rate ratio of 2 and 2 is about 1.5, even if the At- etching is completed and over-etching is performed, the emitter region 37 will be etched and the emitter-base junction will not be exposed. Therefore, even if the emitter contact is not completely covered with the M electrode due to misalignment of the mask, no leakage occurs between the emitter and the base 1g, so the distance between the emitter and the graft base can be reduced.

Therefore, the cell size of the transistor is reduced by /J%, the base resistance is reduced, and the base-collector capacitance is also reduced.

JP-A-Sho GO-57924 (3) In addition, MoSi2 between the A2 electrode 48 and the Eminoku 37
Because of the film 45, At-
Due to the formation of the 8i alloy, no leakage current flows between the base and emitter. Further, a Mo Si 2 film 44.
Is the thickness of 45.46 200 to 600 thin and there are convexities on the emitter, base, and collector? 1 will never occur. Therefore, since the surface becomes flat, a fine At pattern can be easily formed.

Furthermore, an alloy of the emitter resistor 37 and the MO film 42
Since the S x 2 film 46 is formed, the emitter resistance does not increase.

Effects of the Invention According to the present invention, conductor wiring on a shallow pn junction can be formed finely without complicating the process.

[Brief explanation of drawings]

Figure 1 is a cross-sectional structural diagram of a conventional par-f polar LSI;
The figure is a cross-sectional structural diagram of the transistor portion of a conventional bipolar LSI, Figures 3A-D are cross-sectional views of the manufacturing process of the bipolar LSI of the present invention, and Figure 4 is a cross-section of the present invention 9/Mi-Nigagaru transistor. It is a structural diagram. 3o... Silicon substrate, 32... N-type epitaxial layer, 42... Mo film, 44, 4
5.46...MoSi2 film, 47, 4s,
49------At wiring.

Claims (2)

[Claims] (1) Predetermined area ゛1'J for bonding with conductor wiring
, a step of exposing a 9-body substrate, a first z on the substrate,
Form an rI thin film. step, heating the substrate: heating the first layer on the exposed semiconductor substrate surface;
A process for forming an alloy layer of a thin film and a semiconductor,
1ffl tt+. a step of removing the first conductor thin film; a step of forming a second conductor thin film on the NIF-based substrate; and a step of etching the first conductor thin film using an etching gas that etches the alloy layer at a slower rate than the second conductor thin film. 2 of 2. 1. A method for manufacturing a semiconductor integrated circuit, characterized in that r: K''v is formed by selectively removing a conductor thin film. (2) The first conductive thin film is MO and the second conductive thin film is Al.
- or r, 1, Al-3i alloy,
A method for manufacturing a name product circuit.