JPS6057597B2 - electronic musical instruments - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an electronic musical instrument that plays repeated sounds such as an arpeggio, and particularly relates to control of the sound production of each repeated sound.

For example, when performing an automatic arpeggio performance in which multiple keys are played in sequence, one note at a time, and this sequence is repeated, the previously sounded note may overlap with the newly sounded note. This is undesirable because the repeated sound effect that should be obtained by sequentially pronouncing each sound will be weakened.

That is, in order to obtain the effect of crisply repeating sounds when each sound is successively produced, it is preferable that the previously produced sound be surely erased before a new sound is produced.

This invention has been made in view of the above-mentioned points, and when a plurality of sounds selected by pressing a key etc. are to be repeatedly produced in order, the previously produced sound is erased before a new sound is produced. This is to prevent repeated sounds from overlapping each other.

The electronic musical instrument of the present invention has a function (such as automatic arpeggio) that can automatically repeat the pronunciation of multiple tones, and when a certain note is to be produced during the process of repeated pronunciation, the sound It is configured such that the pronunciation of the sound that was being pronounced before can be erased. In other words, it is configured to be able to control the pronunciation of a pre-sound that is separate from the sound that is to be produced (or information related to that sound) based on the sound that is about to start being produced. For example, this electronic musical instrument is equipped with a plurality of sound generation channels, and a plurality of sounds to be automatically and repeatedly sounded are each assigned to an appropriate sound generation channel. Then, when trying to start producing a note assigned to a certain channel, the amplitude envelope of the preceding note that is assigned to another channel and is being sounded (or attenuated) in that channel is forcibly changed. Control is performed so that the process ends immediately. Hereinafter, the present invention will be explained in detail based on the embodiments shown in the accompanying drawings.

The embodiment shown in FIG. 1 is an example in which the present invention is applied to an electronic musical instrument 10 that can perform automatic performances such as arpeggios.

Automatic performance such as an arpeggio is to sequentially produce notes corresponding to one or more keys pressed on the keyboard (the lower keyboard is used in the following example) at predetermined time intervals, one note at a time. This is an automatic performance in which the sound is controlled so that the pitches of these tones repeatedly change over a predetermined octave range, and this is hereinafter referred to as a "chord pyramid" performance. This is because multiple notes played in the form of chords on the keyboard are sounded one by one over one to several octaves, and the pitch of the generated sound is shaped exactly like a pyramid. Depends on how it rises or falls. It's a nickname. In FIG. 1, the control or processing for playing the chord pyramid is performed by the chord pyramid device 1.
1.

Further, an envelope clear signal generation control circuit 12 related to the present invention is provided within the code pyramid device 11. The pressed key detection circuit 14 detects the ON or OFF operation of the key switch of each key arranged on the keyboard 13, and outputs information identifying the pressed key. Sound generation assignment circuit 15
receives key information identifying the pressed key from the pressed key detection circuit 14, and assigns the sound of the key represented by this key information to one of the channels corresponding to the maximum number of simultaneous sounds (for example, 1 key). The chord pyramid device 11 sequentially detects the lower keyboard tones for playing chords (chord pitches) one note at a time among the tones assigned to each channel, and outputs one sound corresponding to the channel to which the detected one note is assigned. Generates signal CON. When this signal CON is generated, the envelope clear signal CCV of the corresponding one channel falls to 0, causing the envelope waveform generation circuit 22 to generate an envelope waveform signal E■.In the tone forming series 16, the envelope waveform signal EV 1 detected based on
Pronounce the musical tone corresponding to the note. In this manner, in response to the sequential detection by the chord pyramid device 11, the lower keyboard tones are sequentially generated one by one in the tone forming sequence 16, resulting in a repeated tone like an arpeggio, that is, a chord pyramid tone. The signal CON is a signal that instructs the start of the sound generation of each sound in the repeated sound, and serves to start the sound production of the sound assigned to the channel in which the signal CON is generated.

In this embodiment, a signal C for instructing the start of sound generation is used.
The ON function also serves to prohibit sound generation for channels other than the channel in which the signal CON is generated. The envelope clear signal generation control circuit 12 provides the signal CON with such a function of inhibiting sound generation for other channels. The envelope clear signal generation control circuit 12 inputs the signal CON, sets the envelope clear signal CCV of the channel where the signal CON is generated to 6601, and sets all the envelope clear signals CCV corresponding to other channels to ``1''. . In the envelope waveform generation circuit 22,
In the channel where the envelope clear signal CCV falls to 0, an envelope waveform signal EV for controlling the musical tone amplitude envelope is generated, and the clear signal CCV falls to 0.
In the channel rising to 4r', the envelope waveform signal EV can be generated. Therefore, the envelope waveform signal EV of the sound (front tone or archaic tone) that was produced immediately before the signal CON was generated is erased.
For example, assume that the first channel is assigned a C note, the second channel is assigned an E note, and the third channel is assigned a G note, and the second
As shown in Figures a-c, each sound ClE. ．． Suppose that the pronunciation of G is repeated. In Fig. 2, when the sound of E is started, the signal CON is generated in the second channel to which the sound E is assigned, and this erases the sound (envelope) of the previous sound, C. Ru. Furthermore, when starting to produce the G note (or C note), a signal CON is generated in the third channel (or the first channel) to which the G note (or C note) is assigned, and this causes the pre-tone The pronunciation of the E sound (or G sound) is deleted. In this embodiment, each sound generation channel of the electronic musical instrument 10 is formed in a time-sharing manner, and the sound generation assignment circuit 15 outputs a key code K representing the pressed key assigned to each channel.
C is output in a time-division manner.

For example, as shown in Table 1, the key code KC includes 2-bit keyboard codes K2, Kl that represent the keyboard type, 3-bit octave codes B3, B2, and 3-bit octave codes that represent the octave range.
It is composed of a total of 9-bit codes including Bl and note codes N4, N3, N2, and Nl representing 12 note names C-B of one octave. In this embodiment, in order to be able to produce multiple sounds at the same time, various counters, processing circuits, storage devices, etc. are shared in a time-sharing manner using dynamic logic, so the operation of the device is regulated. The time relationship of the clock pulses used is extremely important.

FIG. 3a shows the main clock pulse 01. This pulse F5l controls the time division operation of each channel, and has a period of, for example, 1 μs. Since the number of channels is 12, the 1 μs width time slots successively separated by the main clock pulse F5l correspond to the first channel to the twelfth channel in order. As shown in FIG. 3b, each time slot is referred to as a first channel time to a twelfth channel time in order. Each channel time occurs cyclically. Therefore, the key code KC representing the key to which the pronunciation is assigned by the pronunciation assignment circuit 15 is
are sequentially output in a time-division manner in accordance with the time of the assigned channel. For example, the first channel is assigned the note C in the second octave range of the pedal keyboard, the second channel is assigned the note G in the fifth octave range of the upper keyboard, and the third channel is assigned the note G in the fifth octave range of the upper keyboard. C
Assuming that a sound is assigned, and the E note in the fourth octave range of the lower keyboard is assigned to the 4th channel, and no sound is assigned to the 5th to 12th channels, the sound generation assignment circuit 15 calculates the time of each channel. The contents of the key code KC, which is outputted in a time-divisional manner in synchronization with the above, are as shown in FIG. 3c. The outputs from the fifth channel to the twelfth channel are all ゜゜0゛. Further, the sound generation assignment circuit 15 outputs an attack start signal (or key-on signal) AS in a time-divisional manner in synchronization with the time of each channel, which indicates that the sound should be generated in the channel to which the pressed key is assigned the sound generation.

Furthermore, the keys assigned to each channel are released,
As a result, a decay start signal (or key-off signal) DS indicating that the generated musical tone is to be attenuated is output in a time-division manner in synchronization with the time of each channel. These signals AS and DS are used for amplitude envelope control (sound production control) of musical tones. Furthermore, the sound generation allocation circuit 15 receives a decay end signal D from the envelope waveform generation circuit 22 indicating that the sound generation in that channel has ended.
F, and based on this signal DF, clears various memories related to the channel and outputs a clear signal CC that completely cancels the sound generation assignment. In the example of Figure 3c,
The keys assigned to the 1st and 2nd channels are currently being pressed, the keys assigned to the 3rd and 4th channels have been released and their sound is attenuated, and the time slot for the 4th channel is At time t1, the sound generation ends and a decay end signal DF is generated, and at time slot T2, which is delayed by 12 channels, a clear signal C is generated.
When C is output, signals AS, DS, DF, and CC are generated as shown in FIG. 3d-g. Note that since the clear signal CC is output at time slot T2, the attack start signal AS and decay start signal DS of the fourth channel are erased. At this time, the key code KC of the fourth channel time in FIG. 3c is erased, but is drawn as is for convenience of explanation. As shown in FIG. 3, the channels to which the various signals KC, AS, DS, and CC outputted from the sound generation allocation circuit 15 belong can be distinguished based on the channel time.

The above-mentioned sound generation assignment circuit 15 or key press detection circuit 14
A detailed circuit example is not particularly shown.

These circuits 14 and 15 are, for example, disclosed in Japanese Patent Application No. 47-125513 (Japanese Unexamined Patent Publication No. 49-8
No. 4215) The title of the invention is "Key data signal generator" or Japanese Patent Application No. 125514/1984
No. 216) The device disclosed in the specification of the invention entitled "Key Assigner" can be used. Of course, devices other than those disclosed in the specification of the above-mentioned application, such as Japanese Patent Application No. 50-9915? (Japanese Unexamined Patent Publication No. 52-23324) Name of the invention: Key coder Patent application No. 100878/1987 (Unexamined Japanese Patent Application No. 52-24517) Name of the invention: Key press detection circuit 14, sound generation assignment by "channel processor" etc. Although the circuit 15 can be configured, it will not be specifically described here. Key code KC output from pronunciation assignment circuit 15
The attack start signal AS, the decay start signal DS, and the clear signal CC are respectively supplied to the tone forming series 16.
The key code KCl, the decay start signal DS and the clear signal CC are also supplied to the code pyramid device 11.

In the musical tone formation sequence 16, the key code KC supplied from the sound generation assignment circuit 15 is used as an address designation signal to read out numerical information specific to the musical tone frequency of the key corresponding to the key code KC from the frequency information storage device 17. Ru.

The frequency information storage device 17 is constituted by, for example, a read-only memory in which frequency information F (constant) corresponding to the key code KC of each key is stored in advance, and when a certain key code KC is added, the frequency information F (constant) is stored in advance. Reads the frequency information F stored at the address specified by the code.

Since the frequency information F is regularly accumulated in the accumulator 18 and the amplitude of the musical sound waveform is sampled at fixed time intervals, the frequency information F is a digital value proportional to the musical tone frequency of the key. For example, Japanese Patent Application No. 48-41964 (Japanese Unexamined Patent Publication No. 49-130213)
It is a binary value signal as disclosed in the specification of the invention titled "Electronic Musical Instrument". The value of the frequency information F is uniquely determined when the value of the musical tone frequency is specified at a certain sampling rate.

For example, when the value QF (q=1, 2, 3, . . . , q = 1, 2, 3, ...) reaches 64 in w-adic number, the sampling of one musical sound waveform is completed. , and the total channel time is 12μ for one cycle
If this accumulation is performed every s, then the value of the frequency information F is determined by the following equation.

f is the frequency of the musical tone. The value of F may be stored in the storage device 17 in correspondence with the musical tone frequency f to be obtained. The accumulator 18 is a counter that accumulates the frequency information F of each channel at a constant sampling rate (at a rate of 12 μs for each channel time), obtains an accumulated value QF, and reads it out at every sampling time (12 μs). Advances the phase of the power tone waveform.

When the cumulative value QF reaches 64 in decimal notation, it overflows and returns to O, completing the reading of one waveform. In order to accumulate the data F of each channel in a time-divisional manner, the accumulator 18 may be configured with a multi-bit adder and a 12-stage shift register corresponding to the number of channels. The musical waveform memory 20 divides the sound source waveform into a plurality of (for example, 64) sample points, and sequentially stores the amplitude value of each sample point in each address.

The value QF, which is the output of the accumulator 18, becomes an input that specifies the address to be read from the tone waveform memory 20. As the cumulative value QF increases in the accumulator 18, the address specifying the sample point amplitude to be read is sequentially advanced, and the sequential sample point amplitude values of the musical sound source waveform are read out one after another from the waveform memory 20.

A foot change circuit 19 inserted between the accumulator 18 and the musical waveform memory 20 is connected to the foot change circuit 19 which is connected to the foot change circuit 19 which is inserted between the accumulator 18 and the musical waveform memory 20.
The digit of the advance signal QF can be appropriately shifted in accordance with the octave switching designation signal -F.

Therefore, the output QF of the accumulator 18 is input to the waveform memory 20 as is if octave switching is not specified, and if octave switching is specified, it is doubled, quadrupled, eight times, etc. depending on the number of octaves. . is converted into a value and input to the waveform memory 20. By converting the value QF into double, quadruple, etc. values in the foot change circuit 19, the output Q of the accumulator 18 is
2 times, 4 times, 8 times the address actually specified by F,
The sample point amplitude value of the address advanced by . . . is read out from the waveform memory 20. If the address is 2 times, 4 times, or 8 times (in the example, 12 ps in a fixed sample period), this means that the phase advance of the musical sound source waveform to be read out is 2 times or 4 times. Or 8 times... This means that the musical tone frequency obtained is 2 times, 4 times, or 8 times...
...and the pitch of musical tones is one, two, or three octaves...
It means that it can be switched as follows. An octave change designation signal VF for designating the number of octaves to be changed in the foot change circuit 19 is provided from the chord pyramid device 11.

The musical sound waveform memory 20 includes a sound source waveform memory that stores, for example, a sawtooth waveform containing many harmonic components, and the sound source waveform is read out in response to an address signal from an accumulator 18 via a foot change circuit 19. . The timbre circuit 21 is a circuit that applies the read sound source waveform to, for example, a voltage-controlled filter to form a timbre. The pitch of the musical tones generated in the musical tone shape 7 series 16 is determined by the content of the key code KC from the sound generation assignment circuit 15 and the octave switching designation signal VF from the chord pyramid device 11, and the sound generation timing of the generated sound. responds to the fall of envelope clear signal CCV applied from code pyramid device 11 when attack start signal AS is occurring. The sound generation of musical tones in the musical tone forming sequence 16 is controlled by an envelope waveform signal E① supplied from an envelope waveform generating circuit 22.

That is, a sound source waveform signal having a maximum amplitude corresponding to the magnitude of the envelope waveform signal EV is read out from the musical waveform memory 20. An example of the configuration of the envelope waveform generating circuit 22 is schematically shown in blocks in FIG. The envelope waveform memory 23 stores in advance the amplitude envelope of musical tones corresponding to changes in volume over time, and the read address is advanced in accordance with the count output of the envelope counter 24. Advance the envelope counter 24 (that is, advance the read address of the envelope waveform memory 23)
A clock for this is applied to the counter 24 via AND circuits 25 and 26. An attack start signal AS is applied to the other input of the AND circuit 25.
Further, when the count content of the counter 24 reaches the final address of the envelope waveform memory 23, the final address detection logic 27 generates an output “゜1゛”, which prevents the clock from being sent to the AND circuit 26.The envelope clear signal CCV 24, the counter 24
is cleared, and the read address of the envelope waveform memory 23 becomes 0. When the clear signal CCV falls,
When the attack start signal AS is applied, the counter 24 starts counting from address 0, and the envelope waveform signal EV is read from the envelope waveform memory 23. When a chord pyramid performance is performed, the sound generation timing is controlled by the envelope clear signal α■, but when a normal performance is performed, the sound generation timing is controlled by the normal clear signal CC. ．． That is, when the clear signal CC falls from ゜゜1゛ to ゜゜0゛ and the attack start signal AS rises from ゜゜0゛ to "゜1゜" by pressing a key, the counter 24 starts operating and the envelope waveform signal EV
is generated. The final address detection logic 27 detects the final address. If a decay start signal DS representing a key release is generated when the sound N is detected, a decay end signal DF is generated via the AND circuit 28, and the sound generation assignment circuit 15
supplied to When performing a chord pyramid, the normal clear signal CC at channel time 1 of the lower keyboard is not used by the envelope waveform generation circuit 22, and in other cases, the clear signal CC is not used by the envelope waveform generation circuit 22. However, this point is not particularly illustrated. Of course, the envelope counter 24 is configured to perform a counting operation in a time-division manner, and the envelope waveform signal EV is generated in a time-division manner for each channel. The envelope waveform generating circuit 22 generates a sustained tone envelope waveform as shown in FIG. 4, for example.

Therefore, even if envelope waveform memory readout B is stopped at the time of the final address N, the amplitude level of the final address continues to be read out, so that sound generation continues. In this embodiment, the chord pyramid performance is performed using the lower keyboard.

Therefore, the chord pyramid device 11 sequentially selects the key codes of the lower keyboard from among the key codes KC supplied from the sound generation assignment circuit 15 in order of pitch at each predetermined sound generation timing, and assigns the selected key codes KC of the lower keyboard. One (1 μs wide) signal C synchronized with the channel time
ON is generated, and the envelope clear signal CCV is caused to fall to "0" based on this signal CON.In the tone forming series 16, the amplitude envelope of the musical tone is controlled based on this signal CC■. , among the lower keyboard tones assigned to each channel, only the lower keyboard tone of the channel in which the signal CON is generated is made into a musical sound.Detailed examples of the chord pyramid device 11 are shown in FIGS. 6 to 8. The parts shown in FIGS. 6 to 8 are interconnected to form the code pyramid device 11.The method of illustrating the circuit elements adopted in the circuits shown in FIG. 6 and later will be explained with reference to FIG. Figures 5a and 5b show how to illustrate AND circuits and OR circuits when the number of inputs is large. One input line is drawn on the input side of the circuit, and multiple signal lines are connected to this input line. The intersection point between the signal line of the signal to be input to the circuit and the input line is surrounded by a circle.Therefore, in the case of the example shown in figure a, the logical formula is Q=A-
B-D, and in the case of the example shown in figure b, the logical formula is Q=A+B
+C. FIG. 5c shows a shift register (delay flip-flop) for delaying a 1-bit signal, and the number in the block (such as "1" or "2") represents the number of delay stages. If no shift clock is specifically shown, a 1 μS main clock pulse 01 (FIG. 3a) is used. Figure 5d shows a multi-stage shift register.
"S/R (1211)" and the denominator (R) shown in fractional form
The number (for example, 1) represents the number of bits of the signal, and the number (for example, 12) for the numerator (S) represents the number of stages of shift. If the shift clock is not specifically shown, the main clock pulse f! 51 is used. The key press detection sound generation assignment circuit 15 in the chord pyramid keyboard outputs a key code KC related to the key that is currently being pressed or is producing a damped sound after the key is released.
are repeatedly output in synchronization with the allocated channel time, and among these, note codes N1 to N4 and octave codes B1 to Equation are supplied to the coincidence detection circuit 31 via the delay flip-flop group 30 in FIG. be done.

The other input of the coincidence detection circuit 31 is given the counting output of a code pyramid counter 32 consisting of a 7-bit up/down counter (modulo 27=128). As will be described later, the counter 32 is configured to advance by one step every 12 μs, and the counted contents do not change during 12 μs, which is one cycle of the total channel time. Key code N1~
When the count contents of B3 and the counter 32 match, a match detection signal COIN is outputted from the match detection circuit 31 for a time width of 1 μS of the key code. This coincidence detection signal COI
Since N is issued regardless of the type of keyboard, AND circuit 3
3, the coincidence detection signal COIN corresponding to the desired keyboard
Select. In this embodiment, the lower keyboard is used to perform a chord pyramid performance, so the other input line 34 of the AND circuit 33 is supplied with a signal representing a key depression on the lower keyboard. That is, the AND circuit 35 detects that the contents of the keyboard codes K, , K2 of the key code KC represent the lower keyboard (K2 = ゜"1-K, = ゜゜0゛), and the lower keyboard detection signal LE is detected. is input to the shift register 36. Also, the Decay start signal DS is inverted by the inverter 37, and when the inverted output is ゜“1゛, it indicates that the key is being pressed. In addition to 1 in shift register 36
Look at the AND condition with the stage-delayed lower keyboard detection signal. Thus, at the channel time to which the key code of the key pressed on the lower keyboard is assigned, the output of the AND circuit 39 is "6r5", and the AND circuit 33 becomes operational via the line 34.At this time, the output of the AND circuit 33 is enabled via the line 34. key code N
If 1 to 8 match the contents of the counter 32, the coincidence detection signal COIN is applied to the AND circuit 40 via the AND circuit 33. The AND circuit 40 is activated by a gate signal from a line 41 only at a predetermined sound generation timing.

Therefore, the coincidence signal CON selected by the AND circuit 40 corresponds to the sound generation timing. The gating signal provided on line 41 is generated from code pyramid system control 42. The code pyramid system control unit 42 mainly controls the counting and scanning operation of the code pyramid counter 32, and as will be described later, during the counting and scanning of the counter 32, the AND circuit 40 is enabled to operate by the gate signal on the line 41. . The lower keyboard key press signal LE from the AND circuit 39 is the shift register 43 in FIG. 7, and the OR circuit 4.
4 and is input to the AND circuit 45.

This lower keyboard key press signal pressure/section indicates that a key is pressed on the lower keyboard used to perform a chord pyramid performance. In FIG. 7, the OR circuit 46 which inputs the outputs of all 12 stages of the shift register 43 is activated if even one key on the lower keyboard for playing the chord pyramid is pressed (more precisely, the output is assigned to a certain channel). If so, the signal “°1” is output as a direct current.

Also, if no key is pressed on the lower keyboard, OR circuit 46
The output of is the signal ゜゜0゛, and at this time, the inverter 47
The output power is 1. When starting a chord pyramid performance, when the lower keyboard key press signal LE-section associated with the first pressed key or the earliest assigned key among multiple pressed keys is first input into the shift register 43, before that Since no key is pressed on the lower keyboard, the corresponding shift register 43
The signals of all delay output stages of are "0".

Therefore, the output of the AND circuit 45 becomes "1" for a period of 1 μS when the signal LE- is first input to the shift register 43.
It becomes ゛. The output ゜゜1゛ of this AND circuit 45 sets a flip-flop consisting of NOR circuits 48 and 49. When the signal "1" related to the first lower keyboard, key press signal pressure, and section is shifted to the final stage position of the shift register 43 after 12 μS, the signal "1" appearing on the output line 50 of the final stage Flip-flop 4 above
8 and 49 are reset. Therefore, the key press initial pulse LKDP, which is the output of this flip-flop (the output of the NOR circuit 48), is a signal that becomes ゜1゛ for only 12 μs at the beginning of the key press for playing the chord pyramid. The output of the OR circuit 46 and the signal pressure ? are applied to the circuit 44, and when a key is pressed on the lower keyboard, a pressed key display signal LKD, which is a DC signal of ゜゜1゛, is sent.
Output.

Note that the key press display signal LKD (=゜゜1
When ")" is issued, the expiry time setting circuit 51 operates, and a predetermined short expiration time is set in consideration of variations in key press operations.

After the expiry time has expired, the expiration time setting reset signal WR
becomes "0", and the reset by the signal WR is released. At the start of the performance in FIG. Used as reset signal KONR.

This key press initial reset signal KONR is for resetting the contents of all 12 channels of a predetermined counter at the initial key press. Here, the predetermined counter is
It is equipped with a 12-stage shift register and an adder, and can time-divisionally perform counting operations for each channel.The tempo clock frequency dividing circuit consists of a 12-stage 3-bit shift register 63, 6 adders, and an AND circuit group 65. 66
, the octave storage circuit 67 and the up/down control memory 68 in FIG. A basic tempo clock pulse CPL for the code pyramid is supplied from a timing signal generation circuit (not shown), and includes delay flip-flops 69, 70, an inverter 72, and an AND circuit 7.
1, the rising portion of the pulse CPL is shaped into a pulse with a width of 12 μs.

In other words, when the waveform of the rising portion of the pulse CPL is delayed and outputted by the first delay flip-flop 69 in accordance with the timing of the system clock pulse SYl with a period of 12 μS and applied to the AND circuit 71, the inverted output of the delay flip-flop 70 at the next stage is Since it is still “1”, AND circuit 71
The following conditions hold true. 12μ with delay flip-flop 70
The waveform of the rising portion delayed by s is inverted and outputted by the inverter 72, and when the input of the AND circuit 71 becomes ゜゜0゛,
The output of the AND circuit 71 falls to "0", and therefore a 12 μs wide pulse synchronized with all channel times is obtained at the rising edge of the pulse CPL. The frequency of this 12 μs wide pulse is equal to the basic tempo clock pulse CPL. Needless to say, they are the same.The AND circuit 73 receives the above-mentioned lower keyboard key press display signal LKDl and the chord pyramid performance selection signal CPV given in response to the closing of the chord pyramid performance selection switch (not shown). When ゜゜1゛,
The basic tempo clock pulse CPL whose waveform has been shaped to have a width of 12 ps from the AND circuit 71 is selected and added to the counting power of the adder 64 of the frequency dividing circuit 66.

Frequency dividing circuit 6 by 12 stage shift register 63
6 is designed so that counting can be performed for each channel in a time-division manner, but since counting pulses are given with a width of 12 μs, all channels have the same counting content.

In this embodiment, the frequency divider circuit 66 is designed to divide the frequency by 11, and when the most significant bit of the 3-bit half adder 64 overflows, a 12 μs wide carry signal sent to the line 74 is generated as the sound generation timing pulse T. It will be an EP. Therefore, the sound generation timing pulse TEP is a pulse having a width of 12 ps, which is divided into the frequency 118 of the basic tempo clock pulse CPL. The generation period T of this sound generation timing pulse TEP corresponds to the sound generation interval between each generated sound in a chord pyramid performance.

Therefore, from the time when the lower keyboard key is pressed for the first time and the basic tempo clock pulse CPL of 12 ps width can be selected from the AND circuit 73, approximately T has elapsed. After a period of time, the sound generation timing pulse TEP is output. By the way, the sound generation timing of the first note to be sounded at the start of the chord pyramid performance does not depend on the sound generation timing pulse TEP, but depends on the fall of the time limit setting reset signal WR.

This is because if you wait for the first sound generation timing pulse TEP to appear, there will be a time delay that is clearly noticeable to the human ear between the key press operation and the first sound. By sounding the first chord pyramid sound immediately at the end of the allotted time, the responsiveness between the key press operation and the start of the chord pyramid sound generation is improved, and performance performance is improved. Holding time setting circuit 51 (seventh
When the "holding time" set in FIG.

When this reset signal WR is "1", the code pyramid counter 32 and the coincidence code storage circuit 75 in FIG.
and delay flip-flops 76, 77, and 78 are reset, and control or processing operations for playing the chord pyramid are prohibited. In FIG. 6, when the duration setting reset signal WR falls from ゜゜1゛ to ゜゜0゛ (9th
(see Figure a), the delay flip-flop 79 of the code pyramid system control section 42, the AND circuit 80, and the inverter? A negative differentiation circuit consisting of 81 generates a differentiation pulse of 1 μs width in synchronization with the falling edge of signal WR. That is, the AND circuit 80 outputs a start pulse STAT (=゜゜1゛) with a width of 1 μs. (See Figure 9b). In the code pyramid system control unit 42, a delay flip-flop 77 is used to control the scan counting operation of the code pyramid counter 32, and a delay flip-flop 76 is used to secure processing operation time when a carry signal is output from the counter 32. It is for the purpose of Further, the duration setting reset signal WR disables the AND circuit 83 via the NOR circuit 82 (FIG. 8) and resets the up/down control memory 68. When the memory 68 becomes "0", the counter 32 and the octave counter 84 are set to the up counting state.The reset signal WR is applied to the octave counter 84 via the OR circuit 85 and the AND circuit 86. The counter 84 is reset. Upon expiration of the time limit, the reset signal WR becomes '6'.
When the value reaches 0, the reset of the code pyramid counter 32 is released and the counter 32 can perform a counting operation.

Therefore, in the coincidence detection circuit 31, it becomes possible to compare the key code N1 to expression given based on the pressed key with the count contents of the code pyramid counter 32, and signal processing for generating the code pyramid sound is performed. become. The first sound pronunciation will be explained with reference to the time domain column 1T in FIG.

When the start pulse STAT becomes ゜゜1゛ with the end of the holding time, the output H2 of the delay flip-flop 77 is ``0'', so its inverted signal tile is ``1'', and the output of the AND circuit 87 is ``1''. The output becomes “1” and the signal 66r2 is sent to the delay flip-flop 77 via the OR circuit 88.
is loaded. AND circuit 89 is flip-flop 7
(1) Counter 3 is a circuit for circulating the memory of 7.
(2) The carry signal CARY is not outputted from the carry detection circuit 90 of No. 2 (the output of the inverter 91 is “゜1゛”), and (2) the coincidence signal CON is not outputted through the AND circuit 40 (the output of the inverter 92 is “゜1゛”). Output is “1”)
, The logical value of the output of the flip-flop 77 ゜゜1゛ is stored in circulation (FIG. 9c).

When the output H2 of the flip-flop 77 becomes "1", the code pyramid counter 32 becomes capable of scanning and counting. That is, the AND circuit 93 of the code pyramid system control unit 42 determines that (1) the output signal of the flip-flop 77 is In 66r9, (2) When the system clock pulse SYl is given on the condition that the coincidence signal CON is not outputted (the output of the inverter 92 is "゜1゛), the count pulse J1 synchronized with the pulse SYl is outputted. (Figure 9e).

This count pulse J1 is supplied to the counting terminal of the code pyramid counter 32 via the OR circuit 94. The system clock pulse SYl is 1 as shown in FIG. 9d.
It is generated in synchronization with a certain channel time (for example, the first channel time) at a period of 2 μs. Therefore, during the period in which the output H2 of the delay flip-flop 77 for counting operation control is "1", the count pulse J1 of the counter 32 is used to perform one step every 12 μS until the coincidence signal CON is generated. Counting continues. Since the contents of the up/down control memory 68 (see FIG. 8) are initially "0", the up count signal U is "0", and the down count signal D is "0". The counting mode of the code pyramid counter 32 starts from up counting.

Therefore, the contents of the code pyramid counter 32 increase sequentially from 0. The count contents of the counter 32 are compared with the key codes N1 to B3 in the coincidence detection circuit 31, and the key codes N1 to B3 are one for all 12 channels.
The contents of the counter 32 do not change for 12 μs, whereas the contents of the counter 32 appear in a time-division manner once during 2 μs. Therefore, each time the contents of the counter 32 advance by one step, comparison with the contents of all key codes N1-B assigned to all channels is repeated. By the way, the key codes consisting of note codes N1 to N4 and octave codes B1 to B3 have values increasing in the order of pitch of the key, as shown in Table 1 above (note that bit N
1 is the least significant bit and bit 8 is the most significant bit).

In other words, the value of a key code associated with a lower pitch key is smaller, and the value of a key code associated with a higher pitch key is larger.
Therefore, when the increasing contents of the counter 32 match the value of the key code related to the lowest note among the key codes N1 to B3 assigned to the 12 channels, the first match detection signal COIN is output to the match detection circuit 31. issued from (
Figure 9 h). As described above, if this is for the lower keyboard, the coincidence detection signal COIN is applied to the AND circuit 40 via the AND circuit 33. The gate line 41 of the AND circuit 40 is supplied with the output signal of the flip-flop 77, which indicates that the counter 32 is in the scanning counting operation. Therefore, when the code pyramid counter 32 outputs the coincidence detection signal COIN (regarding the lower keyboard) while the code pyramid counter 32 is scanning and counting, the AND circuit 40 outputs the coincidence signal CONC.
"1") is output (FIG. 9 1). Due to the coincidence signal CONf) 64F1, the output of the inverter 92 becomes "0", and the circulating AND circuit 89 becomes inactive. Flip flow after 1μS. Knob 77 output H2
The temperature becomes 0゛.

As a result, the scanning count of the counter 32 is stopped, and the AND circuit 40 is also rendered inactive. Therefore, the coincidence signal CON indicates the key codes N1 to B3 that match the contents of the counter 32.
Only one shot is issued with a width of 1 μs corresponding to the allocated channel time. For example, on the lower keyboard, D3 note, G3 note,
If three eight-tone keys are pressed (almost simultaneously),
The first coincidence signal CON is generated corresponding to the key code of the D3 tone, which is the lowest tone among them.

The following description will be made assuming that the keys of the three notes mentioned above are being pressed. Further, when the coincidence signal CON becomes ゜゜1゛, the signal ゜゜0゛ output from the inverter 92 is output from the inverter 95.
join. Therefore, the inverter 95 outputs the coincidence signal CON
The output becomes "゜1" in synchronization with .This output "1" becomes the read command signal 10AD2 of the coincidence code storage circuit 75 (FIG. 9j). When the read command signal 10AD2 is applied to the matching code storage circuit 75, the current count contents of the code pyramid counter 32 are read into the matching code storage circuit 75 and stored. Therefore, the count data having the same contents as the key codes N1-♂ that generated the coincidence signal CON is stored in the coincidence code storage circuit 75. For JD3 sound, key code B39B29Bl9N49N3tN2,
The same data ゛010000r゛ as Nl is stored.
The coincidence signal CON is applied from the AND circuit 40 to the delay flip-flop 96 for timing adjustment shown in FIG. 1μ
The delayed coincidence signal CON is sent to the octave storage circuit 67.
AND circuits 97 and 98 are enabled.

It is also applied to the circuit of FIG. 7 via line 99. Each bit output Ql, Q2 of an octave counter 84 (FIG. 8) is added to the AND circuits 97 and 98, and the counter 84 is connected via an OR circuit 85 and an AND circuit 86 in response to a time setting reset signal WR. Since it has just been reset, the count outputs Ql and Q2 are 00. When the content of the octave counter 84 is 0, it means that the sound should be produced in the octave range corresponding to the pressed key. The octave storage circuit 67 operates as an octave counter 84 as a 2-bit circular shift register with a total of 12 stages, including 2-stage shift registers 100, 101 and 10-stage shift registers 102, 103.
It is used as a storage circuit to store the count contents for each channel (however, the storage contents of all channels are the same).

The contents of the octave counter 84 read into the octave storage circuit 67 by the coincidence signal CON are taken out from the seventh output stage of the shift registers 102 and 103, and the octave command signal 0CT■1,0CT
It is supplied as V2 to the octave encoder 104 in FIG. Note that AND circuits 105 and 106 in FIG. 8 are circuits for circulating the memories in shift registers 100, 102 and 101, 103.

That is, when the coincidence signal CON occurs, the count contents of the octave counter 84 are read into the octave storage circuit 67 via the AND circuits 97 and 98, and the memory is rewritten; however, when the coincidence signal CON is not generated, the inverter 107
AND circuit 105, 1 by the output ゜゜r3 (αN)
The memory of the octave memory circuit 67 is held through the octave memory circuit 67. When the first match signal CON is generated from the circuit shown in FIG. 6 as described above, this match signal C
The ON signal goes through the circuit shown in Fig. 8 to the circuit shown in Fig. 7, which controls the generation of the rear signal CCV, which is necessary for generating the chord pyramid sound, and also controls the generation of the octave switching designation signal ■F (■F1
~■F,) are rewritten according to the contents of the octave counter 84.

In the octave encoder 104 of FIG. 7, the octave command signal 0 supplied from the octave storage circuit 67
σ■1,0CTV2 is encoded as shown in Table 2 below.

In Table 2, an octave slide amount of 0 indicates an octave range according to the key pressed, and an octave slide amount of 1, 2, or 3 indicates a range 1 octave, 2 octaves, or 3 octaves above the octave range according to the pressed key. The octave change designation signals VFl~■F are applied to line 10 when the chord pyramid performance selection switch (not shown) is closed.
On the condition that the selection signal CP■ of 8 is ゜゛1゛, the octave command signal 0CTV is output in the encoder 104 consisting of an AND circuit group 109 and an OR circuit group 110.
1,0 Generated according to the contents of CTV2. Note that in order to output the octave switching designation signal VF only when the lower keyboard tone is used for chord pyramid performance, the lower keyboard detection signal LE, which is delayed by 11 μs in the shift register 36 of FIG.
l is added to the condition of the encoder 104 via line 111. There is a delay of exactly 12 .mu.s from the time when the key code that has caused a match in the match detection circuit 31 is input to the code pyramid device 11 until the octave change designation signals F1 to VF3 associated with that key code are output.

That is, 2 μS in delay flip-flops 30 and 96.
1 9μS1 at the 7th stage of shift registers 100, 102 and 101, 103 and octave encoder 1
1μS in the delay flip-flop group 112 on the output side of 04
1 total of 12 μs. The reason why the lower keyboard detection signal LE is delayed by 11 μS by the shift register 36 to become LEll is for the same reason. As mentioned above, in the case of the first note, the octave command signal 0σ■1, 0C゛■2 is "00゛, so the octave change designation signal ■F only has bit ■F1 as a signal "゜1゛" and is pressed. Instructs what to pronounce in the octave range of the key.

1 μS wide coincidence signal CO provided via line 99
N is the envelope clear signal in Figure 7. It is added to the generation control circuit 12 and the AND circuit 113.

When performing chord pyramid performance, the selection signal CP
The AND circuit 113 is enabled to operate by V(7)66r'. Therefore, the coincidence signal CON is output from the AND circuit 1.
13 and is added to the 10-stage shift register 114 via the OR circuit 52.
The coincidence signal CON outputted from the envelope clear signal CCV becomes the envelope clear signal CCV. As in the case of the octave switching designation signal VF, the key code N1~ that generated the coincidence signal CON
Clear signal CC corresponding to coincidence signal CON 12 μS after B3 is input to code pyramid device 11
V is output. That is, the delay flip-flop 30
and 2μS1 at 96 and 10PS1 at shift register 114
This is because it will be delayed. Therefore, the key code KC input to the tone forming sequence 16, the channel time of the octave change designation signal VFl and the clear signal CC2 are completely synchronized. In the envelope waveform generating circuit 22 (FIG. 1) of the tone forming series 16 to which the clear signal CCV is applied, when the clear signal CC■ is applied to the envelope counter 24, the count contents of the corresponding channel are cleared to zero.
Therefore, when the clear signal CCV falls (more precisely, the signal C
The signal CCV becomes 66 at the channel time 12 μS after the channel time when C becomes ゜゜1゛ with a width of 1 μS.
08), the envelope counter 24 starts counting, and the envelope waveform signal EV of a sustained sound type as shown in FIG. Become. Based on the generation of this envelope waveform signal EV, the sound assigned to the channel (in the above example, the first
A musical tone (D3 tone) is generated from the musical tone formation series 16. As mentioned above, in the case of the first note, the octave slide amount is 0, so the octave change designation signal F is the tone forming series 16 at the same channel time as the clear signal CCV.
, the value of the output QF of the accumulator 18 is not changed.

Therefore, the first tone D3 is generated in the octave specified by the key press specified by the key code KC. Since the pronunciation code pyramid basic tempo clock CPL from the second note onwards forms the basic tempo of notes that can be clearly perceived by the human ear, the chord pyramid counter 32 processes the basic tempo clock CPL of 12 μS until the coincidence signal CON is output. This is sufficiently longer than the time required for counting scan.

Therefore, as described above, the first chord pyramid performance
The clock pulse C in the frequency dividing circuit 66 starts from the time when the sound generation starts (the time when the first coincidence signal CON is output).
It is safe to assume that PL counting will begin. Therefore, approximately after TO time from the start of the first sound, the frequency dividing circuit 66
A carry signal is sent to line 74 (Fig. 7) from
This is applied to the AND circuit 115 of the code pyramid system control section 42 (FIG. 6) as a sound generation timing pulse TEP having a width of 12 μs (FIG. 9k). This sound generation timing pulse TEP is repeatedly generated every TO time. T.O.
is eight times the period of the clock pulse CPL. From the second tone onward, the counting scan of the code pyramid counter 32 is started in response to the generation of the sound generation timing pulse TEP, and when the coincidence signal CON is output, the chord pyramid tone is generated.

Incidentally, a timing chart of the coincidence signal CON generation control regarding the second and third sounds is shown in the main and π time domain columns of FIG. In FIG. 6, the sound generation timing pulse TEP with a width of 12 μs is synchronized with the system clock pulse SYl with a width of 1 μS and a period of 12 μS, and the AND circuit 1
15 is selected.

The sound generation timing pulse TEPl (9th
1) is added to the OR circuit 94 and the AND circuit 116.

As mentioned above, when the coincidence signal CON related to the first tone was output, the memory of the delay flip-flop 77 became 66053, so the signal '' which is the other input of the AND circuit 116
H2 (a signal obtained by inverting the output H2 of the flip-flop 77 with an inverter) is "1". Since the sound generation timing pulse TEP1 with a width of 1 μs is applied thereto, the signal is output from the flip-flop 7 via the AND circuit 116 and the OR circuit 88.
Signal 1 is added to 7. Therefore, after 1 μS, the output signal H2 of the flip-flop 77 becomes “1”, and the AND circuit 8
It is stored in circulation through 9. When the signal H2 becomes "1", the counting and scanning operation of the chord pyramid counter 32 is restarted as described above.By the way, the chord pyramid counter 32 stops counting when the coincidence signal CON regarding the first note is issued. The same count value as that of the key code N1 to N8 of the first tone (D3 tone) was held.The counting and scanning operation was performed again using this previous matching code, and the AND circuit 40 was activated by the signal H2. There is an inconvenience that the same match signal CON as the previous match code is output immediately when the gate of 9 f), this count pulse J2 (=TEPl) is applied to the counting power of the code pyramid counter 32 via the OR circuit 94.When the signal H2 becomes "゜1゛," Due to the presence of the sound generation timing pulse TE. P
l (count pulse J2) by 1 μs. Therefore, when the signal H2 becomes "゜1゛", the counter 3
Immediately before the code 2 enters the count scanning mode, one count pulse J2 is applied, and the contents of the code pyramid counter 32 are advanced by one step from the previous matching code. In this way, the contents of the chord pyramid counter 32 advance from the previous matching chord by one step to the next note (the second note).
The match detection operation for the pronunciation of the sound) is restarted.

When the counted value of the chord pyramid counter 32 reaches a value that matches the key code of the pressed key (G3 note) of the pitch above the previous note (D3 note), that G3 note is 1μS corresponding to the allocated channel time
A width match signal CON is output.

Similarly to the above, the signal H2 becomes "゜0゛" and the counter 3
2 is stopped, and the matching code reading command signal LOAD2 is sent to the matching code storage circuit 7 via the inverter 95.
given to 5. Therefore, the memory circuit 75 stores the key codes B3, B. , Bl, N4, N3, N2, Nl
The same data as ゜゜0101000゛ is rewritten. In this way, the coincidence code storage circuit 75 stores the coincidence signal C.
Each time ON is generated, new data (matching key code) is rewritten. When the coincidence signal CON is generated,
As mentioned above, the 1 μs wide clear signal CCV is sent to the AND circuit 113 and the OR circuit 52 in synchronization with the channel time to which the key code that generated the coincidence signal CON is assigned.
, is generated via the shift register 114, and sound generation is started in the corresponding channel of the musical tone forming sequence 16.

Note that the octave switching designation signal F does not change unless the count of the octave counter 84 (FIG. 8) changes. As described above, each time the sound generation timing pulse TEP is generated from the frequency dividing circuit 66 (FIG. 7), - that is, the time T.

The counting scan of the counter 32 is restarted at the period of , and the coincidence signal CON is generated. When the counter 32 is incrementing in the counting scanning operation (the up count signal U is "1"), the - contents of the counter 32 match in order from the key code related to the bass key, so in the above example, The coincidence signal CON for the second note is generated based on the key code of the G3 note, and the coincidence signal CON for the third note is generated based on the key code of the B3 note.Therefore, when the counting mode of the chord pyramid counter 32 is up counting. are pronounced in order starting from the lowest note.

When counting down, sounds are produced in order from the highest tones. Here, the sound generation interval is macroscopically the same as the period L of the sound generation timing pulse TEP. 2nd note, 3rd note・
・In response to a 1 μS width coincidence signal CON generated in synchronization with the channel time to which the G3 tone, eight notes, etc. are assigned (clear signal C
In response to the falling edge of CV), an envelope waveform signal EV is generated in order (at each time TO) to generate G3 tone, B3 tone,
... are pronounced in order.

When the envelope clear signal generation control coincidence signal CON is generated, a new musical tone is generated in the channel where the signal CON was generated.

That is, the envelope counter 24 (FIG. 1) is reset by one clear signal α in synchronization with the coincidence signal CON, but the clear signal CC of the channel concerned
Since V immediately falls to ゜゜0゛, it is counted up sequentially from address 0 to N, and the envelope waveform signal E■
is read out. At this time, the coincidence signal CON acts to continuously generate a clear signal CCV for other channels. Since the persistent signal CCV continues to reset the content of the channel in the envelope counter 24, the envelope waveform signal EV of the channel is not generated. Therefore, musical tones cannot be generated on channels other than the channel in which the coincidence signal CON is generated. An envelope clear signal generation control circuit 12 (FIG. 7) is used to perform control to continuously generate an envelope clear signal CC2 in a channel other than the channel in which the coincidence signal CON is generated. In the envelope clear signal generation control circuit 12, 12
The stage shift register 54 is for storing the channel in which the coincidence signal CON is generated, and stores the signal "1" corresponding only to the channel of the latest coincidence signal CON, and stores the signal "0" in the other channels. shall be.

Each stage of the shift register 54 corresponds to 12 sound generation channels. 11 stage shift register 55
stores for 11 channel times that the latest coincidence signal CON was applied via line 99, and based on this memory stores the old coincidence signal CON in the shift register 54 (when the latest coincidence signal CON occurred). (memory of 11 channels other than the channel) will be deleted.

The match signal CON applied from the circuit of FIG. 8 via line 99 is applied to shift register 54 via OR circuit 53 and simultaneously applied to shift register 55. During a period of 11 bits from when the coincidence signal CON is read into the first stage of the shift register 55, the signal "゜1゛" is sequentially shifted from the first stage to the 11th stage (final stage) of the shift register 55. Therefore,
During this 11-bit time, the output of the NOR circuit 56 inputting the outputs of all 11 stages of the shift register 55 becomes ゜゜0゛. The output of the NOR circuit 56 is sent to the shift register 5
4 is added to the memory holding AND circuit 57. Therefore, during the 11 bit time from when the coincidence signal CON is read into the first stage of the shift register 54, the NOR circuit 5
The AND circuit 57 becomes inoperable due to the output 6401 of 6, and all memories of 11 channels corresponding to this 11 bit time are erased. That is, the latest coincidence signal CO
The contents of the shift register 54 corresponding to all the remaining channels (11 channels) except the channel in which N occurs become ゜゜0゛. When 12 bit times have elapsed since the match signal CON was read into the first stage of the shift registers 54 and 55, the signal "R5" corresponding to the match signal CON is read into the last stage of the shift register 54 (
12th stage).

At this time, the shift in the shift register 55 is completed and the outputs of all 11 stages become "60", so the output of the NOR circuit 56 becomes "1", and the AND circuit 57 for memory retention becomes operable. , the latest coincidence signal C
A signal 46r5 corresponding to ON is read from the last stage of the shift register 54 to the first stage of the shift register 54 via the AND circuit 57 and the OR circuit 53. Thereafter, the output of the NOR circuit 56 continues to be ``1'' until the next match signal CON is generated, and the AND circuit 57 for memory retention continues to be operable. Therefore, in all 12 stages of the shift register 54, , a signal ゜゜1゛ is stored and held corresponding to one channel in which the latest coincidence signal CON is generated, and a signal ``゜0゛'' is held corresponding to the other 11 channels. The storage output of shift register 54 is supplied via OR circuit 53 to line 58 in a time-division manner.

The signal on line 58 is inverted by inverter 59 and applied to AND circuit 60. The other inputs of the AND circuit 60 are a chord pyramid performance selection signal CPV indicating that a chord pyramid performance is being performed, and a shift register 36 ( The lower keyboard detection signal LE2 from the second stage in FIG. 6) is added. Therefore, the AND circuit 60 becomes operable during the chord pyramid performance during the channel time to which the lower keyboard tone for the chord pyramid performance is assigned, and outputs a signal obtained by inverting the signal applied from the line 5)8. That is, the output of the AND circuit 60 is 12 bit time (12 μs) at the timing of the channel where the latest coincidence signal CON occurs.
The signal "0" is repeated every time, and the signal "1" is maintained at the timing of other lower keyboard tone assignment channels. The output of this AND circuit 60 passes through an OR circuit 52 and a shift register 114, and then outputs an envelope clear signal CCV.
is output as Note that the memory retention AND circuit 57 of the shift register 54 receives a reset signal KON when the key is pressed.
R, and a clear signal C given from the sound generation allocation circuit 15.
A signal obtained by inverting C by an inverter via a 2-bit delay flip-flop 61 is added, and the memory in the register 54 is cleared at the beginning of key depression and at the end of tone assignment. FIG. 10 schematically shows an example of the generation of the envelope clear signal CCV.
This figure shows how the coincidence signal CON is generated in the order of channel CHl, second channel CH2, and third channel CH3. Figure 10b-d shows each channel C.
This figure shows how the envelope clear signal CCV is generated in Hl, CH2, and CH, respectively.
In c and d, the times of channels CH1, CH2, and CH3 are independently extracted and shown. The continuous envelope clear signal CCV generated via the AND circuit 60 based on the output of the envelope clear signal generation control circuit 12 (FIG. 7) described above is shown by hunting in FIG. 10 B, c, and d. The signal of the section is “1”.The AND circuit 113 is activated in synchronization with the coincidence signal CON which instructs the start of sound generation.
One envelope clear signal C generated via
CV is the portion of the signal ゜゜1゛ in FIGS. 10B, c, and d that is not subjected to hunting. First, pronunciation channel C
When the coincidence signal CON is generated in the channel time of Hl, one envelope clear signal CC■ synchronized with this signal CON is sent to the AND circuit 113, the OR circuit 52,
It is output via the shift register 114.

At the same time, the signal ゜゜1゛ is stored in the shift register 54 of the envelope clear signal generation control circuit 12 corresponding to the channel CHl.
At the time of , the output of the AND circuit 60 becomes ゜゜0゛, and the clear signal CCV in that channel CHl becomes “
It falls to 0゛. Therefore, in response to the fall of clear signal CCV in channel CH1, envelope waveform signal EV is generated in channel CH1 (10th
Figure e). At this time, since the clear signal CCV is continuously generated in the other channels CH2 and CH3 via the AND circuit 60, the envelope waveform signal EV is not generated. Next, when the coincidence signal CON is generated at the timing of channel CH2, while the signal "1", which is a delayed version of the coincidence signal CON, is in the 11-stage shift register 55 (FIG. 7) (therefore, the output of the NOR circuit 56 is is “゜0゛)
, the signal ゜“1” (the one in which the previous coincidence signal CON was stored) stored at the timing of channel CHl is 12
It is output from the final stage of the stage shift register 54.

However, due to the output of the NOR circuit 56, the AND circuit 5
7 becomes inactive, so the memory of the previous coincidence signal CON is canceled. Therefore, at the timing of that channel CHl, the clear signal C is sent via the line 58 and the AND circuit 60.
CV is now produced continuously (see the hunting part in FIG. 10b), and the pronunciation of the pretone assigned to channel CHl is canceled. In other words, clear signal CCV
As a result, the contents of the envelope counter 24 (see FIG. 1) become 0, and reading of the envelope waveform signal EV from the envelope waveform memory 23 is inhibited. On the other hand,
Since the coincidence signal CON is cyclically stored in the shift register 54 at the timing of the channel CH2 related to the new sound to be generated, the output voltage of the AND circuit 60 becomes "0" at the timing of the channel H2, as shown in FIG. 10c. As shown in , the clear signal CC2 of channel CH2 falls to "0". Therefore, the envelope waveform signal E2 is generated in the channel CH2. As described above, when a new sound is to be produced on a certain channel, the sounds produced on other channels are deleted before that. In the above embodiment, since the envelope waveform signal EV has a sustained tone envelope shape,
It is very effective to erase the previous sound when pronouncing a new sound.

However, it is desirable to apply the present invention not only to sustained tone envelopes but also to percussion envelopes. That is, if the sound interval TO of the repeated sound is shorter than the decay time of the percussion envelope, the decay part of the previous sound overlaps with the rise part of the new sound, as shown by the broken line in FIG. 10f.
If this invention is adopted, the front tone and the new tone are clearly separated as shown by the solid line in FIG. 10f. Octave slide control (Part 1) The octave slide amount specified by the octave switching designation signal VF is determined by the octave counter 84 (Fig. 8).
It corresponds to the content of

Octave counter 84 is chord pyramid counter 3
When a carry signal CARY is issued from 2, the count is advanced by one. Therefore, the octave of the generated sound does not change and remains constant until the code pyramid counter 32 completes one counting scan (counts by the modulus number and generates the carry signal CARY). And carry signal CA
When RY is issued, the octave of the generated sound changes. A carry signal -8C, ARY is generated from a carry detection circuit 90'' (FIG. 6).

The carry detection circuit 90 includes an AND circuit 117 and a NOR circuit 118 to which the up count command signal U and all bit outputs of the counter 32 are input, respectively. AND circuit 11
7 is " of the signal U representing the up counting operation of the counter 32.
When the output of the counter 32 reaches the maximum value (that is, all output bits are ゜゜1゛), a carry detection output ゜"1" is generated.This AND circuit 11
The output '6r3 from 7 passes through the OR circuit 119 and becomes the carry signal CAR when the counter 32 is up by L.
It becomes Y. Further, the NOR circuit 18 is enabled to operate by ゜゛0゛ of the signal U representing the down counting operation of the counter 32 (the down counting command signal D is "6r"), and the counter 32
When the output becomes the minimum value (that is, all output bits are ゜゜0゛), a carry detection output ゜゛1゛ is generated.The output 66r゛ from this NOR circuit 118 passes through the OR circuit 119 and is used when the counter 32 counts down. Carry signal C at
Become ARY. Therefore, the code pyramid counter 32
is in the up counting state, the coincidence signal CO regarding the key code of the highest key among the keys specified by the key code KC.
T from the time I rolled N.

A carry signal CARY is issued (by the AND circuit 117) during the counting scan of the counter 32 which is restarted after a certain period of time. Further, when the counter 32 is in a down counting state,
T from when the match signal CON related to the key code of the lowest key among the keys specified by the key code KC is output. In the process of counting and scanning of the counter 32, which is resumed after a certain period of time, a carry signal CARY is output from the NOR circuit 118. When the carry signal CARY is output, the counting and scanning of the counter 32 is temporarily stopped, and when the processing of the carry signal is completed, the counting and scanning starts again. is started. Now, of the three notes D3, G3, and Y33 that are pressed simultaneously on the lower keyboard, the eighth note, which is the highest note, is the third note.
Assume that it is pronounced as a sound.

At this time, an eight-note key code is stored in the matching code storage signal 75 (FIG. 6). When the sound generation timing pulse TEP is generated after T time from the start of sound generation of the third note and applied to the chord pyramid system control section 42, the signal H2
becomes 46r1, and the counting scan of the code pyramid counter 32 is restarted. In other words, the key code N for the B3 note
The count clock J2 is given to the counter 32, which has stopped at the same value as 1 to B3, and the contents of the counter 32 become the value obtained by adding 1 to the eight-tone key code, and then the timing of the system clock pulse SY1 Count pulse J1 is now given. The counter 32 is incremented by this count pulse J1, but B3.
Key codes N1 to B3 with values greater than the sound key code
is not supplied in this case (at least for the lower keyboard), the count value of the counter 32 reaches the maximum value 111111r' without generating the coincidence signal CON. Then, the carry signal CARY is sent via the AND circuit 117.
is issued (Fig. 9 m). When the carry signal CARY becomes "1", the output of the inverter 91 becomes "0", the AND circuit 89 becomes inactive, the memory of the delay flip-flop 77 is erased, and the signal becomes "0" after 1 μs. (See the 41 hour area column in Figure 9).

Furthermore, if the system clock pulse SYl occurs while the carry signals CARY are out, the AND An output ゜゜1゛ is generated from the circuit 120 and is stored in the flip-flop 76 via the OR circuit 121.

After j1 μs, the output H1 of the flip-flop 76 becomes 66r.
', since the system clock pulse SYl is "0", the signal ゜゜1゛ is circulated and stored through the AND circuit 122. When the system clock pulse SYl occurs 12 μS later, the AND circuit 122 is disabled. Since the operation is performed, the memory of the flip-flop 76 is cleared.

Therefore, as shown in FIG. ), the AND circuit 123
When the following conditions are met, a 12 μs width octave switching pulse T is generated.
RIG is issued (see Figure 9 0).

This octave switching pulse TRIG is passed through the line 124 to the delay flip-flop 1 for timing adjustment shown in FIG.
In addition to 25, an octave rise/fall control circuit 126
are added to each AND circuit 127-133. If the octave slide amount (content of the octave counter 84) currently being played does not reach the value set with the octave slide amount setting switch (not shown), an output ゜゜1゛ is generated in the AND circuit 127, and the OR circuit 134 is output. A signal ``1'' is applied to the AND circuit 135 via the AND circuit 135. Since the system clock pulse SYl is applied to the AND circuit 135, a 1 μs wide signal ``1'' is applied from the AND circuit 135 at the timing of the pulse SYl. It is output and added to the counting power of the octave counter 84. Therefore, the octave counter 84 is incremented by one. Note that when the system clock pulse SYl is generated when the signal H1 generated based on the carry signal CARY is ゜゜1゛ and the signal H2 is ゜゜0゛, the AND circuit 136 (Fig. 6) generates a signal as shown in Fig. 9g. A count pulse J3 is generated.

This count pulse J, is applied to the code pyramid counter 32 via an OR circuit 94. Further, a signal 6'r1 is output from the AND circuit 137 (FIG. 6) under exactly the same conditions as the AND circuit 136, and is stored in the flip-flop 77. Therefore, 1 μs when count pulse J3 occurred
Afterwards, the signal becomes ゜゜1゛, and the counting scan of the counter 32 is restarted. If the up count command signal U is still applied, the counter 32 is incremented from the minimum value 0.

When the contents of the counter 32 match the key code of the lowest note (D3 note), a match signal CON is output. This starts the production of the fourth sound. Note that when the AND circuits 97 and 98 of the octave storage circuit 67 (FIG. 8) become operational due to the coincidence signal CON regarding the fourth note,
Since the count content of the octave counter 84 has been incremented by 1, data ゜60r゛ representing an octave slide amount of 1 is stored in the circuit 67. Therefore, the octave switching designation signals VFl, VF2, and ■F3 become ゜゜01σ゛, and the D3 note related to the key code that generated the coincidence signal CON is slid up one octave to become the D4 note. Therefore, the D4 sound is produced as the fourth sound. Since the contents of the octave counter 84 do not change until the next carry signal CARY is output, the fifth and sixth notes are
Although the coincidence signal CON regarding the G3 note and the 8-note key code is output as the sound, even if the content of the key code KC output from the pronunciation assignment circuit 15 (FIG. 1) is for the G3 note and B3 note, The octave change designation signal ■F in the foot change circuit 19 causes the tone G4 to be one octave higher.
, B4 sound respectively.

Therefore, G, the sound, and the eighth sound are sequentially pronounced as the fifth and sixth sounds. Octave Slide Control (Part 2) The maximum octave slide amount is set according to the performer's wishes using an octave slide amount setting switch (not shown).

Depending on the setting of this switch, octave slide amount setting signals 0SE1 and 0SE2 (FIG. 8) are applied. The relationship between the signals 0SE1 and 0SE2 and the octave slide amount is as shown in Table 3. In Table 3, the meanings of octave slide amounts 0, 1, 2, and 3 are the same as in Table 2 above.

The octave slide amount setting signals 0SE1 and 0SE2 are applied to one input of an adder 139 of an octave comparison circuit 138 (FIG. 8). Signal 0SE1 is the lower bit, 0SE2
has the weight of the upper bit. Octave comparison circuit 1
38 is configured as a subtracter, and converts the counting output of the octave counter 84 into an octave slide amount setting signal 0S.
Subtract from E1,0SE2. By performing complement calculation in the adder 139 (the lower bit is always given "゜1゛" from the line 140), subtraction is performed, so the count output of the octave counter 84 is transmitted to the inverter 141, 142, and are applied to other inputs of the adder 139. That is, the octave comparison circuit 138 converts the octave slide amount setting binary numbers ゛0SE2, 0SE1゛ to the current performance octave slide amount ゜゜0CTV2, 0CTV1. Subtract ゛. When the current octave slide amount reaches the set value, the solution of the subtraction becomes "゜00゛", so the output of the adder 139 becomes ゜゜0σ゛. It is detected that the slide amount has reached the set octave slide amount, and an output "゜1゛" is generated. The output of this NOR circuit 143 ゛“1” is the OR circuit 144
And it is applied to the octave rise/fall control circuit 126 as an octave slide amount match signal 0SEQ via a delay flip-flop 145 for timing adjustment. Also,
When the current octave slide amounts 0CTV1 and 0CTV2 are 0, the AND circuit 146 operates and the octave slide amount 0 detection signal ZR becomes .degree.

This detection signal Δ is the octave rise/fall control circuit 126
used in Up mode and turn mode "Up mode" is a system in which the notes corresponding to multiple keys pressed on the lower keyboard are sounded one by one in order from the bass side, and this sequential sound is repeated over one or more octaves. , which produces the effect of repeated rises in pitch.

"Turn mode" is a format in which the above-mentioned tones are sounded in order from the low end, and then in order from the treble end, producing the effect of repeating the rise and fall of the pitch over one or more octaves. . In this embodiment, one of the above-mentioned "up mode" or "turn mode" can be selected. When selecting the up mode, close the up mode selection switch (not shown) and set the selection signal UM/TM to "0".

As a result, the up mode selection signal UM becomes ゜"1゛5 via the inverter 147 (FIG. 8), and the line 14
The turn mode selection signal TM of No. 8 becomes 640°. When the turn mode is selected, contrary to the above, the up mode selection signal UM becomes ゜゜0゛ and the turn mode selection signal TM becomes ゜゜1゛. Special signal processing for turn mode or up mode is not specifically described.

Therefore, the AND circuits 149, 150, 151, 152, the OR circuit 53,
154, 155, NAND circuit 156, adder 157, delay flip-flops 78, 158, 159, 160, signals H, π, TP, lOADl, OCRE, etc. will not be described.

These are explained in detail in the specification of Japanese Patent Application No. 51-78574 (Japanese Unexamined Patent Publication No. 53-4524) titled "Electronic Musical Instrument." In the above example, the chord pyramid is played. Although this invention is applied to an electronic musical instrument that performs automatic arpeggio performance, it is not limited to this.
The present invention can generally be applied to cases in which a plurality of sounds are automatically and repeatedly pronounced.

As explained above, according to the present invention, when one or more sounds are repeatedly pronounced, the previous sound that has already been pronounced is surely erased when starting to pronounce each sound, so that the repeated sounds are not overlapped. The sound is no longer pronounced, and the effect of repeating the sound crisply can be obtained.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the electronic musical instrument of the present invention, FIGS. 2 a to c are graphs showing the waveforms of each sound when three sounds are repeatedly produced according to the invention, and FIG. 3 is the first
4 is a graph showing an example of the envelope waveform stored in the envelope waveform memory of FIG. 1. FIG. 5 is a diagram illustrating various circuit elements. Figures 6, 7, and 8 are detailed circuit diagrams showing the detailed example of the code pyramid device in Figure 1 divided into three parts, and Figure 9 is a diagram explaining the method in Figure 6. Timing chart showing an example of the operation of the code pyramid system control unit of
FIG. 0 is a schematic timing chart showing an example of the generation of the envelope clear signal CCV and how the envelope waveform signal EV is generated or erased by the envelope clear signal CCV. 11... Code pyramid device, 12...
Envelope clear signal generation control circuit, 15...
・Sound generation assignment circuit, 16...Musical tone formation series, 2
2... Envelope waveform generation circuit, 32...
. . . Code pyramid counter, 42 . . . Code pyramid system control unit.

Claims (1)

[Claims] 1 having a key code generating means for generating a plurality of key codes corresponding to musical tones to be produced specified by a key pressed on a keyboard, and a plurality of musical tone forming channels, and having a plurality of musical tone forming channels; musical tone forming means for allocating a plurality of key codes to one of the plurality of musical tone forming channels and respectively forming musical tones corresponding to the assigned key codes in each musical tone forming channel; key code selection means for sequentially selecting one key code from a plurality of key codes according to predetermined conditions; provides sound generation control information that instructs the musical tone generation channel to which the assigned key code is assigned to generate musical tones, and provides generation control information that instructs other musical tone generation channels to prohibit the generation of musical tones; An electronic musical instrument comprising musical tone control means for controlling generation of musical tones formed in each musical tone generating channel of the musical tone generating means for each musical tone generating channel.