JPS5941591B2 - electronic musical instruments - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an electronic musical instrument in which a period of time during which a key operation is not performed is set at the beginning of the key operation, so that the responsiveness to the key operation is adapted to human senses.

In keyboard-type electronic musical instruments, there is a limit to the temporal accuracy of key operations by human fingers.

When attempting to press a plurality of keys at the same time, it is usually unlikely that the plurality of keys will be pressed at the same time (simultaneously down to the microsecond (μs)). No matter how much you try to press them at the same time, due to differences in the length of each finger, dominant finger, and other factors, the difference in pressing time between each key is estimated to be less than 10 milliseconds (milliseconds). It's time. This also applies when attempting to release multiple keys at the same time. In other words, the times of Gurus S to Ten Gurus S appear to be the same time for humans. However, 1μs
In electronic musical instruments, where information is processed by distinguishing signals in units of degree, key presses that a person intended to perform at the same time (
Even a time difference that occurs when a key is pressed (or a key is released) may manifest itself as a difference in the timing of the key press (or key release). In other words, even if multiple keys are pressed at the same time (simultaneously according to human senses) with an error of several Ms to tens of Ms, the electronic musical instrument will respond as if the keys were pressed separately. If a plurality of keys are pressed at the same time, there is a risk that the processing that the performer expected will not be performed. Such inconveniences are particularly problematic when processing for automatic performance is performed.
For example, when trying to make multiple keys pressed one note at a time in an arpeggio format starting from the low note, the electronic musical instrument's internal circuit may respond to the high note first due to variations in key presses. It may happen that a note is emitted first, or that only the one note to which the circuit within the electronic musical instrument responds first is repeatedly emitted several times first. For example, a chord is formed by multiple notes pressed at the same time.
When detecting keys, there is a possibility that an incorrect code may be detected using fewer keys than the number of keys actually pressed due to variations in key operations at the beginning of a key press operation and at the beginning of a key release operation. It can happen. This invention has been made in order to eliminate the above-mentioned inconveniences, and is designed to prevent the circuit within an electronic musical instrument from responding to key operations for a predetermined period of time after the first key operation on the keyboard. purpose.

The length of this predetermined time is preferably a time that humans perceive as simultaneous, for example, several Ms to several tens of ms. Of course, it is not desirable to have an obvious response delay that is so long that it can be perceived by humans. below,
The above-mentioned predetermined time set from the time of the first key operation to the time of response will be referred to as "waiting time". The first time a key is operated means when a key is pressed, starting from a state in which no key is pressed on the keyboard, and exiting that state by pressing a key. Further, the time of key release indicates the time when any of the keys that have been pressed until now is released from a state in which keys are continuously pressed. Since the circuit within the electronic musical instrument does not respond to key operations during the waiting time, at the end of this waiting time, all key operations performed during this waiting time are treated as having been performed at the same time.
That is, variations in key operations for multiple keys during the waiting time are ignored. According to this invention, the first key operation on the keyboard is detected, a waiting time is started based on this detection, and during this waiting time, the use of key press information given from the keyboard is substantially prohibited. do.

When the waiting time ends, the key press information given from the keyboard becomes usable, so the plurality of keys pressed during the waiting time are available for use as if they were pressed at the same time.
Here, "use" means selecting appropriate one-note information from the key press information, detecting a chord (chord) based on the key press information, or generating musical tones based on the key press information. This refers to the general processing of key press information in electronic musical instruments. Hereinafter, the present invention will be explained in detail based on the embodiments shown in the accompanying drawings.

The embodiment shown in FIG. 1 is an example in which the present invention is applied to an electronic musical instrument capable of realizing an automatic performance similar to an arpeggio.

Automatic performance, similar to an arpeggio, is a system in which the notes corresponding to one or more keys pressed on the keyboard are sounded one by one at predetermined time intervals, and the pitches of these notes span a predetermined octave range. It is an automatic performance that changes repeatedly,
This will be referred to as the "Code Pyramid" performance below. This is because multiple notes played on the keyboard in the form of chords are sounded one by one over one to several octaves, and the pitch of the generated sound is exactly like the shape of a pyramid. The name comes from the way it rises and falls. In FIG. 1, a chord pyramid device 10 performs control for playing chord pyramids and processes key press information.

The key operation detection section 11 and the waiting time setting circuit 12, which are related to the main parts of the present invention, are provided in the code pyramid device 10, and are activated by the waiting time setting signal WR generated during the waiting time. Tsute code pyramid device 10
The use of the key press information within the system, that is, the signal processing operation based on the key press information, is temporarily prohibited.
First, the overall structure of the electronic musical instrument shown in FIG. 1 will be outlined, and then the details of the chord pyramid device 10, particularly the key operation detection section 11 and the waiting time setting circuit 12, will be explained. The key press detection circuit 14 detects the on or off operation of the key switch of each key arranged on the keyboard 13,
Outputs information identifying the pressed key.

The pronunciation assignment circuit 15 receives information identifying the pressed key from the pressed key detection circuit 14, and assigns the pronunciation of the key represented by this information to one of the channels corresponding to the maximum number of simultaneous pronunciations (for example, 12 notes). Assign to. The sound generation assignment circuit 15 has a memory location corresponding to each channel, stores a key code KC representing a certain key in the memory location corresponding to the channel to which the sound of a certain key is assigned, and stores the key code KC stored in each channel. KC is sequentially output in a time-division manner. Therefore, when a plurality of keys are pressed on the keyboard 13, each pressed key is assigned to a separate channel, and a key code KC representing the assigned key is stored in the memory location corresponding to each channel. It is ★￥ru. Each storage location can be configured by a rotating shift register. For example, as shown in Table 1, the key code KC that specifies each key on the keyboard 13 is the 2-bit keyboard code K2, Kl that represents the keyboard type, the 3-bit octave code B3, B2, Bl that represents the octave range, and 4-bit note code N4 that represents the note name within one octave
, N3, N2, Nl, and the total number of channels is 12.
It is preferable to use a shift register with 12 stages (9 bits per stage). In this embodiment, in order to be able to produce multiple sounds at the same time, various counters, logic circuits, storage devices, etc. are dynamically configured to be shared in a time-sharing manner, so that the operation of the device is regulated. The time relationship of the clock pulses used is extremely important. FIG. 2a is a graph showing the main clock pulse φ1, which controls the time-division operation of each channel and has a period of, for example, 1 ItS. Since the number of channels is 12, the 1 μS width time slots successively separated by the main clock pulses φ, correspond to the first to twelfth channels in sequence. Figure 2b
As shown in the figure, each time slot is referred to as a first channel time to a twelfth channel time in order. Each channel time occurs cyclically. Therefore, the key code KC (
i.e. the key code stored in the shift register)
are sequentially output in a time-division manner in accordance with the time of the assigned channel. For example, the first channel is assigned the C note of the second octave range of the pedal keyboard, the second channel is assigned the G note of the fifth octave range of the earth keyboard, and the third channel is assigned the note G of the fifth octave range of the upper keyboard. C
Assuming that a sound is assigned, and the E note in the fourth octave range of the lower keyboard is assigned to the fourth channel, and no sound is assigned to the fifth to twelfth channels, the sound generation assignment circuit 15 calculates the time of each channel. The contents of the key code KC, which is output in a time-divisional manner in synchronization with the time, is as shown in FIG. 2c. The outputs from the fifth channel to the twelfth channel are all 0''.The sound generation assignment circuit 15 also sends an attack start signal (or key-on signal) indicating that the pressed key should be sounded in the channel to which the sound is assigned. ) Output AS in a time-divisional manner in synchronization with each channel time.

Furthermore, the keys assigned to each channel are released,
As a result, a decay start signal (or keyo 7 signal) DS indicating that the sound generation should be attenuated is output in a time-divisional manner in synchronization with the time of each channel. These signals A
S and DS are used for amplitude envelope control (sound production control) of musical tones. Furthermore, the sound generation assignment circuit 15 receives a decay end signal DF indicating that the sound generation in that channel has ended from the envelope generation circuit described later, and based on this signal DF, clears various memories related to the channel and completes the sound generation assignment. A clear signal CC is output to clear the signal. In the example of Figure 2c, the first
The keys assigned to the channel and the second channel are currently being pressed, the keys assigned to the third and fourth channels have been released and their sound is attenuated, and in the fourth channel, the keys assigned to the time slot t1 are being pressed. Assuming that the decay end signal DF is generated when the sound generation ends, and the clear signal CC is output at the time slot T2 delayed by 12 channels, each signal AS, DS, DF is output as shown in FIG. , CC occurs. Note that since the clear signal CC is output at time slot T2, the attack start signal AS and decay start signal D of the fourth channel
S is deleted. At this time, the key code KC of the fourth channel time in FIG. 2c is erased, but is drawn as it is for convenience of explanation. As shown in FIG. 2, the channels to which the various signals KC, AS, DS, and CC output from the sound generation allocation circuit 15 belong can be distinguished based on the channel time.

The above-mentioned sound generation assignment circuit 15 or key press detection circuit 14
Detailed circuit examples of these circuits 14 and 1 are not particularly shown.
5, for example, the already published patent application 1972-
No. 125513 (Japanese Unexamined Patent Publication No. 49-84215) Name of the invention "Key data signal generator" or Patent application No. 1984-1
The device disclosed in the specification of No. 25514 (Japanese Unexamined Patent Publication No. 49-84216) entitled "-Key Assigner" can be used. Of course, devices other than those disclosed in the specification of the above application, such as Japanese Patent Application No. 5099152 (
The key press detection circuit 14 and the sound generation assignment circuit 15 can be configured using Japanese Patent Application No. 50100878 (key coater) (channel processor). Not detailed.

The key code KC, attack start signal AS, decay start signal DS, and clear signal CC outputted from the tone splitting circuit 15 are respectively supplied to a tone forming series 16, which outputs the key code KC, decay start signal DS, and clear signal CC. is supplied to the code pyramid device 10. In the musical tone formation sequence 16, the key code KC supplied from the sound generation assignment circuit 15 is used as an address designation signal to read out numerical information specific to the musical tone frequency of the key corresponding to the key code KC from the frequency information storage device 17. Ru.

The frequency information storage device 17 is constituted by, for example, a read-only memory in which frequency information F (constant) corresponding to the key code KC of each key is stored in advance, and when a certain key code KC is added, the frequency information F (constant) is stored in advance. Reads the frequency information F stored in the address specified by the code.

Since the frequency information F is regularly accumulated in the accumulator 18 and the amplitude of the musical waveform is sampled at regular intervals, the frequency information F is a digital value proportional to the musical tone frequency of the key. For example, Japanese Patent Application No. 48-41964 (Japanese Unexamined Patent Publication No. 49-130213)
It is a binary value signal as disclosed in the specification of the invention titled "Electronic Musical Instrument".

The value of the frequency information F is uniquely determined when the value of the musical tone frequency is specified at a certain sampling rate.
For example, the value QE obtained by successively accumulating the frequency information F in the accumulator 18 (however, q-1, 2, 3...)
Assuming that sampling of one musical sound waveform is completed when becomes 64 in decimal, and assuming that this accumulation is performed every 12 μs, which is one cycle of the total channel time, then F-1
The value of frequency information F is determined by the formula 2×64×f×10−6.

f is the frequency of the musical tone. The value of F may be stored in the storage device 17 in correspondence with the musical tone frequency f to be obtained. The accumulator 18 is a counter that accumulates the frequency information F of each channel at a constant sampling rate (at a rate of 12 μs for each channel time), obtains an accumulated value QE, and reads it out at every sampling time (12 μs). Advances the phase of the power tone waveform.

When the accumulated value QF reaches 64 in decimal notation, it overflows and returns to 0, completing the reading of one waveform. In order to accumulate the data F of each channel in a time-divisional manner, the accumulator 18 may be configured with a multi-bit adder and a 12-stage shift register corresponding to the number of channels. The musical waveform memory 20 divides the sound source waveform into a plurality of (for example, 64) sample points, and sequentially stores the amplitude value of each sample point in each address. The value QF, which is the output of the accumulator 18, becomes an input for specifying the address to be read from the tone waveform memory 20. As the accumulated value QF increases in the accumulator 18, the addresses specifying the sample point amplitudes to be read out are sequentially advanced, and the sequential sample point amplitude values of the musical sound source waveform are successively read out from the waveform memory 20.

A foot change circuit 19 inserted between the accumulator 18 and the musical waveform memory 20 controls the frequency of the two outputs from the accumulator 18 in order to access the waveform memory 20.
The digit of the advance signal QF can be shifted appropriately according to the octave switching designation signal FF.

Therefore, the output QF of the accumulator 18 is input to the waveform memory 20 as is if octave switching is not specified, and if octave switching is specified, it is doubled, quadrupled, eight times, etc. depending on the number of octaves.・・・・・・・・・
is converted into a value and input to the waveform memory 20. In the foot change circuit 19, the value QF is doubled, quadrupled, etc.
By being converted to the value of ......, the output QF of the accumulator 18 has advanced by 2 times, 4 times, 8 times, etc. from the address actually specified. The sample point amplitude value of the address is read from the waveform memory 20. During a certain sample period (12 μs in this example), the address doubles, quadruples, or eight times...
...This means that the phase advance of the musical sound source waveform to be read out is twice, four times, or eight times...
This means that the resulting musical tone frequency will be doubled, quadrupled, or eight times higher, and the pitch of the musical tone will be one octave, two octaves, or three octaves. Octave means that it can be switched in the following manner. An octave change designation signal FF for designating the number of octaves to be changed in the foot change circuit 19 is provided from the chord pyramid device 10.

The musical sound waveform memory 20 includes a plurality of sound source waveform (sine waveform) memories each storing each harmonic waveform.
Accumulator 1 via foot change circuit 19
Each harmonic waveform is read out simultaneously according to the address signal from 8. The harmonic coefficient circuit 21 is a circuit that individually controls the relative amplitude of each read harmonic waveform, and the amplitude-controlled harmonic waveforms are added to obtain a musical waveform of a desired tone. In this manner, the tone forming series 16 uses the harmonic synthesis method to obtain a tone with a desired timbre. The pitch of the sound generated in the musical tone formation sequence 16 is determined by the contents of the key code KC from the sound generation allocation circuit 15 and the octave switching designation signal FF from the chord pyramid device 10, and the sound generation timing of the sound is determined. When the attack start signal AS is generated, the code pyramid device 1
It responds to the fall of the envelope clear signal CCF given from 0. The production of musical tones in the musical tone forming sequence 16 is controlled by an envelope signal EV supplied from an envelope generating circuit 22.

That is, a sound source waveform signal having a maximum amplitude corresponding to the magnitude of the envelope signal E is read out from the musical sound waveform memory 20. An example of the configuration of the envelope generating circuit 22 is schematically shown in the block diagram of FIG. The envelope memory 23 stores in advance the amplitude envelope of musical tones corresponding to changes in volume over time, and the read address is advanced in accordance with the count output of the envelope counter 24. A clock for advancing the envelope counter 24 (that is, advancing the read address of the envelope memory 23) is applied to the counter 24 via AND circuits 25 and 26. The other input of the AND circuit 25 receives the attack start signal A.
When the counted contents of the counter 24 reach the final address of the envelope memory 23, an output "1" is generated from the final address detection port 27, and the AND circuit 26 blocks the clock from being sent. When the envelope clear signal CCF is given to the counter 24, the counter 24 is cleared and the read address of the envelope memory 23 becomes O.When the clear signal CCF falls, if the attack start signal AS is given, The counter 24 starts counting from address 0, and receives the envelope signal EV from the envelope memory 23.
is read out. When a chord pyramid performance is performed, the sound generation timing is controlled by the envelope clear signal CCF, but when a normal performance is performed, the sound generation timing is controlled by the normal clear signal CC. That is,
When the clear signal CC falls from ``1'' to ``O'' due to key depression, and the attack start signal AS rises from ``0'' to ``1'', the counter 24 starts operating and the envelope signal E is generated. When the final address detection port 27 detects the final address N, if the take-up start signal DS indicating key release is generated, the take-off end signal DF is generated via the AND circuit 28 and sent to the sound generation assignment circuit 15. Note that when performing a chord pyramid performance, the normal clear signal CC at the channel time of the lower keyboard is not used by the envelope generation circuit 22, and in other cases, the clear signal CC is supplied to the envelope generation circuit 22. However, this point is not particularly illustrated.Of course, the envelope counter 24 is configured to perform counting operation in a time-division manner, and the envelope signal EV is counted in a time-division manner for each channel. generated.

The envelope generating circuit 22 generates a percussion envelope waveform as shown in FIG. 3, for example.

In the percussion envelope shown in FIG. 3, when the counter 24 is cleared, a count pulse is added to the counter 24, and the count value of the counter 24 reaches 1, the level of the maximum value at address 1 is read out. .

Thereafter, the level attenuates until reaching the final address N, and at the final address N, the level becomes O and the sound disappears. In this embodiment, chord pyramid performance is performed using the lower keyboard.

Therefore, the chord pyramid device 10 sequentially selects the key codes of the lower keyboard from among the key codes KC supplied from the sound generation assignment circuit 15 in order of pitch at each predetermined sound generation timing, and the selected key code KC of the lower keyboard is assigned. One (1 μs wide) envelope clear signal CCF is generated in synchronization with the channel time being used.
The musical tone forming sequence 16 controls the amplitude envelope of musical tones based on this signal CCF, and of the lower keyboard tones assigned to each channel, only the lower keyboard tone of the channel in which the clear signal CCF is generated is generated. A detailed example of the code pyramid device 10 is shown in sections in FIGS. 5-7. The parts shown in FIGS. 5 to 7 are interconnected and code 1:! ′? A mid-range device 10 is configured.
The method of illustrating circuit elements adopted in the circuits shown in FIG. 5 and subsequent circuits will be explained with reference to FIG. 4. Figure 4 a and b are entered: "7.?.: Temple: Rinini = Draw a line and cross this input line with multiple signal lines, and the signal line and input line of the signal to be input to the same circuit. The intersection point with is surrounded by a circle.

Therefore, in the case of the example shown in Figure a, the logical formula is Q-A-B-D, and in the case of the example shown in Figure b, the logical formula is Q-A+B+C. Figure 4c shows a shift register (delay flip-flop) for delaying a 1-bit signal, and shows the number in the block ("1").
” or “2”, etc.) represents the number of delay stages. If a shift clock is not specifically shown, a 1 μs main clock pulse φ1 (FIG. 2a) is used. Figure 4d shows a multi-stage shift register, [S/R(
12/1)] in fractional form, the number in the denominator (R) (for example, 1) represents the number of bits of the signal, and the number in the numerator (S) (for example, 12) represents the number of stages of shift. If no shift lock is specifically shown, main clock pulse φ1 is used. The key press detection sound generation assignment circuit 15 in the chord pyramid keyboard repeatedly outputs the key code KC associated with the key that is currently being pressed or is producing attenuated sound after the key is released, in synchronization with the assigned channel time. , among which note codes N1 to N4 and octave court B1
.about.B3 are supplied to the coincidence detection circuit 31 via the delay flip-flop group 30 in FIG.

The other input of the coincidence detection circuit 31 is given the count output of a code pyramid counter 32 consisting of a 7-bit up/down counter (modulo 27=128). As will be described later, the counter 32 is advanced by one step every 12 .mu.s, and the count does not change during the 12 .mu.s period in which the total channel time goes through one cycle. Key code N1~
When the count contents of B3 and the counter 32 match, a match detection signal COIN is output from the match detection circuit 31 for a time width of 1 μs of the key code. This coincidence detection signal COI
Since N is issued regardless of the type of keyboard, AND circuit 3
3, the coincidence detection signal COIN corresponding to the desired keyboard
Select. In this embodiment, the lower keyboard is used to perform a chord pyramid performance, so the other input line 34 of the AND circuit 33 is supplied with a signal representing a key depression on the lower keyboard. That is, the AND circuit 35 detects that the contents of the keyboard codes Kl and K2 of the key code KC represent the lower keyboard (K2゛1゛, K1-゛O゛), and the lower keyboard detection signal LE is sent to the shift register. 36. In addition, the take-key start signal DS is inverted by the inverter 37, and when the inverted output is "1", it indicates that the key is being pressed, so it is applied to the AND circuit 39 via the delay flip-flop 38, and delayed by one stage by the shift register 36. Look at the AND condition with the lower keyboard detection signal LE.
Thus, at the channel time to which the key code of the key pressed on the lower keyboard is assigned, the output of the AND circuit 39 is 1', and the AND circuit 33 becomes operational via the line 34. At this time, the key code of the lower keyboard key is N1 to B3.
matches the contents of the counter 32, the coincidence detection signal CO
IN is applied to an AND circuit 40 via an AND circuit 33. The AND circuit 40 is activated by a gate signal from a line 41 only at a predetermined sound generation timing.

Therefore, the coincidence signal CON selected by the AND circuit 40 corresponds to the sound generation timing. The gating signal applied to line 41 is generated from code pyramid system control 42. The code pyramid system control section 42 mainly controls the counting and scanning operation of the code pyramid counter 32, and as will be described later, during the counting and scanning of the counter 32, the AND circuit 40 can be operated by the gate signal on the line 41. becomes. Lower keyboard key press signal LE from AND circuit 39. DS is the shift register 43 and OR circuit 4 in FIG.
4 and is input to the AND circuit 45.

This lower keyboard key press signal LE-DS indicates that a key is pressed on the lower keyboard used for playing the chord pyramid. In FIG. 6, the key operation detection section 11
, a 12-stage shift register 43 with the same number as the number of sound generation channels, a 12-input OR circuit 46 into which the outputs of all 12 stages of the register 43 are input, and the OR circuit 44.
, and detects the first key depression operation on the lower keyboard.

If no key is pressed on the lower keyboard, the lower keyboard key press signal LE-DS does not appear at any channel time, and the input to the shift register 43 is always 00''. The output is 0° in terms of direct current. When a key is pressed on the lower keyboard for the first time, the lower keyboard key press signal L is generated at the channel time to which that key is assigned.
E-DS is generated and the output of the OR circuit 44 rises to "1". This lower keyboard key depression signal LE-DS is transmitted to the shift register 4.
3, the lower keyboard key press signal LE-DS is sequentially shifted for 12 channel times (12 μs), and when the time of the same channel comes 12 channel times later, the lower keyboard key press signal LE-DS is inputted to the shift register 43 again. Therefore, the lower keyboard key press signal LE-DS generated in a time-sharing manner is converted into a direct current in the shift register 43 and the OR circuit 46, and when even one key on the lower keyboard is pressed, the output of the OR circuit 46 is always a signal. It becomes ゛1゛. Since the output ``1'' of this OR circuit 46 is applied to the OR circuit 44, the output of the OR circuit 44 rises from 0'' to ``1'' in response to the first key press operation, and always increases while the lower keyboard key is pressed. The signal becomes "1". This DC-converted key depression signal will be referred to as a lower keyboard key depression display signal LKD. Therefore, OR circuit 4
When the lower keyboard key press display signal LKD, which is the output of step 4, rises from ``O゛゜ to ``1'', it is detected that a key is pressed for the first time on the lower keyboard.For example, the first key press operation on the lower keyboard is detected. D
If you press the three keys 3, G3, and B3 at the same time and perform a chord pyramid using the sounds corresponding to these three keys, press the B3 key, D3 key, and G3 key every 10I1S in the order. Suppose there is some variation in key timing.

Key press detection circuit 1 that does not particularly perform waiting time setting control
4 and the sound generation assignment circuit 15 (FIG. 1) directly respond to this variation in key press timing and assign B3, D3, and G3.
Pronunciation assignment processing is performed in the order of the sounds. Here, assuming that the B3 tone is assigned to the second channel, the D3 tone to the fourth channel, and the G3 tone to the sixth channel, Figure 8b
As shown in the figure, the lower keyboard key press signal LE-DS/) is generated in a divisive manner. That is, at first, a repeated lower keyboard key press signal LE-DS is generated in the second channel to which the B3 note that was pressed first is assigned, and then the D3 note that was pressed several tens of microseconds later is assigned. The lower keyboard key press signal LE-DS is also generated during the fourth channel.

Furthermore, the lower keyboard key press signal signal LE-h is also transmitted at the time of the 6th channel to which the G3 tone, which was pressed several tens of microseconds later, is assigned.
Liao will begin to occur.

In order to clearly understand the repetition of the time-division channel time, FIG. 8a shows a control system clock pulse SYl generated in synchronization with the first channel time. still,
The lower keyboard key press signal LE-b is actually delayed by 1 μs in the delay flip-flop 38 (FIG. 5), but it is
For the sake of convenience, the relationship between and b is shown ignoring this point. FIG. 8c shows the lower keyboard key press display signal LKD, which rises to signal "1" in response to the first key press operation.

The key press display signal LKD output from the key operation detection section 11 is supplied to the waiting time setting circuit 12, and the waiting time is set as described below.

Further, the output of the OR circuit 46 is inverted by an inverter 47 and applied to an AND circuit 45. When no key is pressed on the lower keyboard, the output of the OR circuit 46 is 0, the output of the inverter 47 is 1, and the AND circuit 45 is enabled. There, the first lower keyboard key press signal LE-
When DS is given, the output of the AND circuit 45 becomes 1'. After 1 .mu.s, each stage of the shift register 43 starts outputting the signal 2, so the AND circuit 45 becomes inactive. Therefore, the AND circuit 45
The output of this AND circuit 45 is ``1''.
sets a flip-flop consisting of NOR circuits 48 and 49. When the signal ``1'' associated with the first key press signal LE-1 is shifted to the position of the final stage of the shift register 43 after 12 μs, the flip-flop 48 is activated by the signal ``1'' appearing on the output line 50 of the final stage. , 49 are set.

Therefore, the key press initial pulse LKDP, which is the output of this flip-flop (the output of the NOR circuit 48), remains 1 for only 12 μs at the beginning of the key press. Setting of Waiting Time To put it simply, the function of the waiting time setting circuit 12 (FIG. 6) is to set the time period (for example, several to 10+ M
A waiting time is provided only during the period s), and the operation of each component circuit of the code pyramid device 10 is prohibited during this waiting time.

Since key presses are detected for all keys pressed at the same time during the waiting time, once the waiting time is over, it will be as if the
Signals related to all pressed keys (key codes N1 to N4, Bl to B3) as if they were pressed at the same time in units of s
, Kl, K2, attack start signal AS, decay start signal DS, etc.). In Figure 6, when no keys are pressed on the lower keyboard for chord pyramid performance,
The output of the shift register 43 that stores the lower keyboard key press signals LE-DS for 12 channels is 0, and the OR circuit 44
The output of is also ゛O゛. Therefore, the output of the inverter 51 which inverts the key depression display signal LKD is "1", and this signal "1"
is supplied to a waiting time counter 52 and delay flip-flops 53 and 54 in the waiting time setting circuit 12 to reset them. When the first key press is detected,
Since the key depression display signal LKD becomes "1" in direct current and the output of the inverter 51 becomes "0", the above-mentioned setting is canceled. 61 and can be obtained by inversion.

Therefore, when the delay flip-flop 53 is in the reset state, the wait time setting signal WR is 1''.Also, even if the reset is released, the delay flip-flop 53 remains in the reset state unless the signal is read. Since it holds 0 if it is stored, the waiting time setting signal WR
Maintain 1. The waiting time starts when the waiting time counter 52 is reset.

That is, a predetermined length of waiting time is measured by counting the waiting time setting clock pulses TC in the counter 52 from the time when the reset of the counter 52 is released. The waiting time setting clock pulse TC is 12
12 depending on the system clock pulse SYl with a period of μs.
Delay flip-flops 54 and 55 providing a μs delay
(55 is an output inversion type), an inverter 56, and an AND circuit 57 form the waveform into a 12 μs wide pulse, and the AND circuit 57 selects a 1 μs wide pulse at the timing of the system clock pulse SY1. 1μ
The clock pulse TC, which is waveform-shaped to have a width of s and is output from the AND circuit 57, is added to the counting input of the counter 52.

A counter 52 counts clock pulses TC, and an AND circuit 58 detects when the data of the lower five binary bits Q1 to Q5 all become 1'. That is, the clock pulse TC is 25 counting from the time when the reset is released.
- When 131 elements are added, the output of the AND circuit 58 becomes electric F
? becomes. The output “1” of the AND circuit 58 is the OR circuit 59
The memory of the flip-flop 53 is stored in the output line 60 and the OR circuit 59.
It is self-maintained through .

When the memory in the flip-flop 53 becomes ``1'', the waiting time setting signal WR falls to 0''. This ends the waiting time. In this way, a waiting time of approximately 31 times the period of the clock pulse TC is set. During the waiting time, the reset signal WR is 1', and as will be described later, various counters, flip-flops, memory circuits, etc. are reset by the reset signal WR, and the code pyramid device is reset during the waiting time. It inhibits 10 major actions. For example, if the length of the waiting time is desired to be about 5 ms, the period of the clock pulse TC is set to about 160 μs. At the start of the performance in FIG. 6, the key press initial pulse LKDP is inverted by an inverter 62 and is used as the key press initial set signal KONR, which becomes a signal "0" for a width of 12 μs.

This key press initial set signal KONR is used to reset the contents of all 12 channels of a predetermined counter at the initial key press. Here, the predetermined counter is
It is equipped with a 12-stage shift register and an adder and can time-divisionally perform counting operations for each channel.The tempo clock frequency dividing circuit 66 is composed of a 12-stage 3-bit shift register 63, an adder 64, and an AND circuit 65.
, the octave storage circuit 67 and the up-down control memory 68 in FIG. A basic tempo clock pulse CPL for the code pyramid is supplied from a timing signal generation circuit (not shown), and includes delay flip-flops 69 and 70, an inverter 72, and an AND circuit 71.
The rising portion of the pulse CPL is shaped into a pulse with a width of 12 μs in a differentiating circuit consisting of the following. In other words, when the waveform of the rising portion of the pulse CPL is delayed and outputted by the first delay flip-flop 69 in accordance with the timing of the system clock pulse SY1 and applied to the AND circuit 71, the inverted output of the delay flip-flop 70 at the next stage is still 1'', the condition of the AND circuit 71 is satisfied.

The waveform of the rising portion delayed by 12 μs by the delay flip-flop 70 is inverted and outputted by the inverter 72, and when the input of the AND circuit 71 becomes ``0'', the output of the AND circuit 71 falls to 0'', and therefore the pulse CPL At the rising edge, a 12 μs wide pulse synchronized with the entire channel time is obtained. It goes without saying that the frequency of this 12 μs wide pulse is the same as the basic tempo clock pulse CPL. Key press display signal LK
D, and when the chord pyramid performance selection signal CPF given in response to the closing of the chord pyramid performance selection switch (not shown) is ``1'', the basic signal whose waveform has been shaped to a width of 12 μs from the AND circuit 71 is Tempo clock pulse CPL is selected and applied to the count input of adder 64 of frequency divider circuit 66.

Frequency dividing circuit 6 by 12 stage shift register 63
6 is designed so that counting can be performed for each channel in a time-division manner, but since counting pulses are given with a width of 12 μS, all channels have the same counting content.

In the embodiment, the frequency dividing circuit 66 performs 1/8 frequency division, and when the most significant bit of the 3-bit half adder 64 overflows, a 12 μs wide carry signal sent to the line 74 is set as the sound generation timing. It becomes pulse TEP.
Therefore, the sound generation timing pulse TEP is a 12 μs wide pulse whose frequency is divided to 1/8 of the basic tempo clock pulse CPL. The generation period T of this sound generation timing pulse TEP corresponds to the sound generation interval between each generated sound in chord pyramid performance.

Therefore, the tone generation timing pulse TEP is output approximately T hours after the key on the lower keyboard is pressed for the first time and the basic tempo clock pulse CPL of 12 μs width can be selected from the AND circuit 73. By the way, the sound generation timing of the first sound to be sounded at the start of the chord pyramid performance does not depend on the sound generation timing pulse TEP, but depends on the fall of the wait time setting signal WR.

This is because if you wait for the first sound generation timing pulse TEP to appear, there will be a time delay that is clearly noticeable to the human ear between the key press operation and the first sound. By sounding the first chord pyramid sound immediately upon completion of the waiting time, responsiveness between key depression and the start of the chord pyramid sound generation is improved, and performance performance is improved. Waiting time setting circuit 12 (sixth
When the "waiting time" set in FIG. 2 ends, the waiting time setting signal WR falls from "1" to "O".

When the reset signal WR is 1', the chord pyramid counter 32, the coincidence code storage circuit 75, and the delay flip-flops 76, 77, and 78 shown in FIG. 5 are reset, and the control operation for playing the chord pyramid is performed. Or prohibit the processing operation. In FIG. 5, when the wait time setting signal WR falls from 0 to 0 (see FIG. 9a), the delay flip-flop 79, AND circuit 80, and inverter 81 of the code pyramid system control section 42
A negative differentiator circuit consisting of
A differential pulse of μs width is generated. That is, the AND circuit 80
A start pulse STAT (1゛1゛) with a width of lμs is output from the start pulse. (See Figure 9b). Note that the code pyramid system control section 42 has a delay flip-flop.
JMoV is for controlling the scanning counting operation of the code pyramid counter 32, and the delay flip-flop 76 is for securing the processing operation time when the carry signal of the counter 32 is output. Further, the waiting time setting signal WR disables the AND circuit 83 via the NOR circuit 82 (FIG. 7) and resets the up/down control memory 68. When the memory 68 becomes ``0'', the counter 32 and the octave counter 84 are set to the up counting state. Further, the reset signal WR is applied to the octave counter 84 via an OR circuit 85 and an AND circuit 86, and resets the counter 84. When the set signal WR becomes 'O' due to the end of the waiting time,
The code pyramid counter 32 is released,
The counter 32 is now capable of performing counting operations.

Therefore, in the coincidence detection circuit 31, it becomes possible to compare the key codes N1 to B3 given based on the pressed keys with the count contents of the code pyramid counter 32, and perform signal processing for generating the code pyramid sound. You will be able to do it. At the end of this waiting time, all the key codes KC related to the plurality of keys pressed almost simultaneously by the fingers of the person Z1 are all present.

For example, in the example shown in FIG. 8, the electronic musical instrument (key press detection circuit 14) shows that the keys B3, D3, and G3, which the human intended to press at the same time, were actually pressed with a variation of several tens of microseconds.
However, during the waiting time, the code pyramid device 10 is in a state in which it does not respond to key press operations (that is, the key codes N1 to B3 are not substantially used in the coincidence detection circuit 31). Therefore, this slight variation in key press operation has no effect on the chord pyramid performance. For example, when the waiting time of about 5 ms has ended, the keys B3 and D3 are pressed with slight variations.
, G3 are all reliably pressed, and the key codes N1 to B3 of each key are repeatedly supplied in synchronization with the channel time by being assigned to appropriate channels. Therefore, after the waiting time ends, the code pyramid device 10 performs key code coincidence detection processing for all the keys pressed on the lower keyboard, so that no malfunctions occur due to variations in the timing of key pressing. The operation of the code pyramid device 10 after the end of the waiting time will be described below for reference.

The first sound pronunciation will be explained with reference to the 1T time domain column in FIG.

When the waiting time ends and the start pulse STAT becomes ``1'', the output of the delay flip-flop JMoV becomes H.
Since H2ba0'', the inverted signal H2ba1' is
The output of the AND circuit 87 becomes ゛1゛, and the OR circuit 88
The signal "1" is read into the delay flip-flop JMOV through the AND circuit 89, which is a circuit for circulating the memory of the flipflop JMOV. (output ``1'' of inverter 91), and (
2) Under the condition that the coincidence signal CON is not outputted through the AND circuit 40 (the output of the inverter 92 is BI), the logic value ``1'' of the output H2 of the flip-flop JMOV is stored in a circular manner (see FIG. 9). c).

When the output H2 of the flip-flop JMoV becomes "1", the scan counting operation of the code pyramid counter 32 becomes possible.In other words, the AND circuit 93 of the code pyramid system control section 42 (1) When the system clock pulse SYl is given under the condition that the output signal H2 is "1" and (2) the coincidence signal CON is not output (the output of the inverter 92 is "1"), the count is synchronized with the pulse SYl. Output pulse J1 (
Figure 9e).

This count pulse J, is supplied to the count input terminal of the code pyramid counter 32 via the OR circuit 94. The system clock pulse SYl is 1 as shown in Figure 9d.
It is generated in synchronization with a certain channel time (for example, the first channel time) at a period of 2 μs. Therefore, during the period when the output H2 of the delay flip-flop JMOV for counting operation control is "1", the counter 32 is stepped by 1 step every 12 μs by the count pulse J1 until the coincidence signal CON is generated. Counting continues. Note that since the contents of the up/down control memory 68 (see FIG. 7) are 0'' at the beginning, the up count signal U is 1-1.
The down count signal D is ``0'', and the counting mode of the coat pyramid counter 32 starts from up counting. Therefore, the contents of the code pyramid counter 32 are incremented sequentially from O. The count contents of the counter 32 are compared with the key codes N1 to B3 in the coincidence detection circuit 31, and the key codes N1 to B3 for all 12 channels are 12μ.
The contents of the counter 32 do not change for 12 μs, whereas the contents of the counter 32 do not change for 12 μs. Therefore, each time the contents of the counter 32 advance by one step, comparison with the contents of all key codes N1 to B3 assigned to all channels is repeated. By the way, the key codes consisting of note codes N1 to N4 and octave codes B1 to B3 increase in value in the order of the pitch of the key, as shown in Table 1 above (note that bits N, (The least significant bit is the most significant bit, and bit B3 is the most significant bit.)

In other words, the value of a key code associated with a lower pitch key is smaller, and the value of a key code associated with a higher pitch key is larger.
Therefore, when the contents of the incrementing counter 32 match the value of the key code related to the lowest note among the key codes N1 to B3 assigned to the 12 channels, the first match detection signal COIN is sent to the match detection circuit. 31 (Figure 9h). As described above, if this is for the lower keyboard, the coincidence detection signal COIN is applied to the AND circuit 40 via the AND circuit 33.

A counter 32 is connected to the gate line 41 of the AND circuit 40.
An output H2 of the flip-flop JMOV is provided which indicates that the flip-flop is in a scan counting operation. Therefore, when the code pyramid counter 32 outputs the coincidence detection signal COIN (regarding the lower keyboard) while the code pyramid counter 32 is scanning and counting, the AND circuit 40 outputs the coincidence signal CON (゛1゛). 9 Figure 1) The output of the inverter 92 becomes "0" due to "1" of the coincidence signal CON, and the circulation AND circuit 89 becomes inoperable, so that after 1 μs, the output H2 of the flip-flop J/V becomes "0". As a result, the scanning count of the counter 32 is stopped, and the AND circuit 40 is also deactivated.Therefore, the coincidence signal CON is generated at the channel time to which the key codes N1 to B3 that match the contents of the counter 32 are assigned. Correspondingly, only one shot is issued with a width of 1 μs.
For example, if three keys, D3, G3, and B3, are pressed (almost simultaneously) on the lower keyboard, the first matching signal C will be generated corresponding to the key code of D3, which is the lowest of the keys.
ON occurs.

The following description will be made assuming that the keys of the three notes mentioned above are being pressed. Further, when the coincidence signal CON becomes "1", the signal "O" outputted from the inverter 92 is applied to the inverter 95. Therefore, the inverter 95 outputs "1" in synchronization with the coincidence signal CON. This output "1" becomes the read command signal LOAD2 of the coincidence code storage circuit 75 (FIG. 9j). When the read command signal LOAD2 is applied to the coincidence code storage circuit 75, the current count contents of the coat pyramid counter 32 are read into the coincidence code storage circuit 75 and stored. Therefore, count data having the same content as the key codes N1 to B3 that generated the coincidence signal CON is stored in the coincidence code storage circuit 75. In the case of the D3 sound, the same data 010000F as the key codes B3, B2, Bl, N4, N3, N2, Nl is stored. Coincidence signal CON
is applied from the AND circuit 40 to the delay flip-flop 96 for timing adjustment shown in FIG.

The 1 μs delayed match signal CON enables AND circuits 97 and 98 of octave storage circuit 67.

It is also provided to the circuit of FIG. 6 via line 99. Octave counter 84 (seventh
The bit outputs Ql and Q2 shown in FIG. It is 00゛. The fact that the content of the octave counter 84 is O indicates that the sound should be produced in the octave range corresponding to the pressed key. The octave storage circuit 67 is a 2-bit circular shift register with a total of 12 stages, including 2-stage shift registers 100, 101 and 10-stage shift registers 102, 103, and is used to store the counted contents of the octave counter 84 for each channel. Used as a memory circuit (however, the memory contents of all channels are the same).

The contents of the octave counter 84 read into the octave storage circuit 67 by the coincidence signal CON are taken out from the seventh output stage of the shift registers 102 and 103, and the octave command signals 0CTV1, 0CT are obtained.
V2 is supplied to the octave encoder 104 in FIG. Note that AND circuits 105 and 106 in FIG. 7 are circuits for circulating the memories in shift registers 100, 102 and 101, 103.

That is, when the coincidence signal CON occurs, the count contents of the octave counter 84 are read into the octave storage circuit 67 via the AND circuits 97 and 98, and the memory is rewritten; however, when the coincidence signal CON is not generated, the inverter 107
AND circuit 105,1 by the output ゛1゛(CON)
The memory of the octave memory circuit 67 is held through the octave memory circuit 67. When the first match signal CON is generated from the circuit shown in FIG. 5 as described above, this match signal C
The ON signal goes through the circuit shown in Fig. 7 to the circuit shown in Fig. 6, which generates the clear signal CCF necessary for generating the chord pyramid sound, and further outputs the octave change designation signal FF (FFl to F
F3), is rewritten according to the contents of the octave counter 84.

In the octave encoder 104 of FIG. 6, the octave command signal 0 supplied from the octave storage circuit 67
CTV1 and 0CTV2 are encoded as shown in Table 2 below.

In Table 2, an octave slide amount of 0 indicates an octave range according to the pressed key, and an octave slide amount of 1, 2, or 3 indicates a range 1, 2, or 3 octaves above the octave range according to the pressed key. The octave change designation signals FFl to FF3 are sent to line 108 when the chord pyramid performance selection switch (not shown) is closed.
On the condition that the selection signal CPF of is set to ``1'',
Octave command signals 0CTV1, 0CTV1,
It is generated according to the contents of 0CTV2. In addition, in order to output the octave switching designation signal FF only when the lower keyboard tone is used for chord pyramid performance, the shift register 3 shown in FIG.
Detection of the lower keyboard with a delay of 11μs in 6! Signal LEl
l is added to the condition of the encoder 104 via line 111. There is a delay of exactly 12 .mu.s from the time when the key code that caused a match in the match detection circuit 31 is input to the code pyramid device 10 until the octave switching designation signals FF1 to FF3 related to that key code are output.

That is, the delay flip-flops 30 and 96 have a delay of 2 μs.
, 9μS1 at the 7th stage of shift registers 100, 102 and 101, 103 and octave encoder 1
The delay flip-flop group 112 on the output side of 04 is 1 μs.
, a total of 12 μS. The reason why the +'keyboard detection signal LE is delayed by 11 μs by the shift register 36 to become LEll is for the same reason. As mentioned above, in the case of the first note, the octave command signals 0CT1, 0CTV2 are 00゛, so only bit FFl of the octave change designation signal FF becomes the signal ゛1゜゛, and the sound should be produced in the octave range according to the key pressed. to instruct.

1 μs wide coincidence signal CO provided via line 99
N is added to AND circuit 113 in FIG.

When performing a chord pyramid performance, the selection signal CP
The AND circuit 113 is enabled to operate by "1" of F. Therefore, the coincidence signal CON passes through the AND circuit 113, is applied to the 10-stage shift register 114, and is output from the shift register 114. Coincidence signal CO
N becomes the envelope clear signal CCF. As in the case of the octave switching designation signal FF, the clear signal CC is issued 12 μs after the key codes N1 to B3 that generated the coincidence signal CON are input to the code pyramid device 10.
F is output.

That is, delay flip-flops 30 and 96 provide 2 μS.
, and is delayed by 10 μs in the shift register 114. Therefore, the channel times of the key code KC input to the tone forming series 16, the octave change designation signal FF, and the clear signal CCF are completely synchronized. In the envelope generating circuit 22 (FIG. 1) of the tone forming series 16 to which the clear signal CCF is applied, when the clear signal CCF is applied to the envelope counter 24, the count contents of the corresponding channel are cleared to O.

Therefore, when the clear signal CCF falls (more precisely, the signal CCF
1 from the channel time when CF became 1 μS wide.
The signal CCF becomes ``0'' at the channel time 2 μs later.
3), the envelope counter 24 starts counting, and a percussion envelope signal EV as shown in FIG. 3 is generated from the envelope generation circuit 22 in a time-divisional manner during the channel time. Therefore, at the rise of this percussion envelope signal E, the sound assigned to the channel (in the above example, the first
A musical tone (D3 tone) is generated from the musical tone formation series 16.The tone D3 is generated as the plate envelope signal EV attenuates.
is attenuated. As mentioned above, in the case of the first note, the octave slide amount is 0, so the octave change designation signal FF
Even if QF is applied to the foot change circuit 19 of the tone forming series 16 at the same channel time as the clear signal CCF, the value of the output QF of the accumulator 18 is not changed. Therefore, the first tone D3 is generated in the octave specified by the key press specified by the key code KC. Since the chord pyramid basic tempo clock CPL for the second and subsequent notes forms the basic tempo of notes that can be clearly perceived by the human ear, the chord pyramid counter 32 clocks for 12 μs until the coincidence signal CON is output. This is sufficiently longer than the time required for unit counting scanning.

Therefore, as described above, the first part of the chord pyramid performance is
The clock pulse CP in the frequency dividing circuit 66 starts from the time when the sound generation starts (the time when the first coincidence signal CON is output).
It is safe to assume that counting of L will begin. Therefore,
Approximately T time after the start of sound generation of the first note, a carry signal is sent from the frequency dividing circuit 66 to the line 74 (Fig. 6), and this is sent to the code pyramid system control unit 42 (Fig. 5) as a sound generation timing pulse TEP of 12 μs width. ) is added to the AND circuit 115 (Fig. 9k). This sound generation timing pulse TEP is repeatedly generated every T time. T is eight times the period of clock pulse CPL. From the second tone onward, counting scanning of the code pyramid counter 32 is started in response to the generation of the sound generation timing pulse TEP, and when the coincidence signal CON is output, the code pyramid tone is generated.

Incidentally, a timing chart of the coincidence signal CON generation control regarding the second and third sounds is shown in the 2T and 3T time domain columns of FIG. In FIG. 5, a sound generation timing pulse TEP having a width of 12 .mu.s is selected by an AND circuit 115 in synchronization with a system clock pulse SY1 having a width of 1 .mu.s and a period of 12 .mu.s.

The sound generation timing pulse TEPl (9th
1) is added to the OR circuit 94 and the AND circuit 116.

As mentioned above, when the coincidence signal CON related to the first tone is output, the memory of the delay flip-flop JMoV becomes "0", so the signal N2 (which is the other input of the AND circuit 116)
The signal obtained by inverting the output H2 of the flip-flop JMOV by an inverter is 1". Since the sound generation timing pulse TEPl of 1 μs width is applied thereto, the AND circuit 116
, the OR circuit 88 sends the signal 1 to the flip-flop JMoV.
is added. Therefore, after 1 .mu.s, the output signal H2 of the flip-flop JMOV becomes "l", which is circulated through the AND circuit 89 and stored. When the signal H2 becomes "1", the counting and scanning operation of the code pyramid counter 32 is restarted as described above. By the way, the code pyramid counter 32 stops counting when the coincidence signal CON related to the first note is issued, and the code pyramid counter 32 stops counting when the coincidence signal CON regarding the first note (D3 note) is output.
The count value was kept the same as 3. When the counting and scanning operation is restarted with this previous match code and the gate of the AND circuit 40 is opened by the signal H2, there is a disadvantage that the same match signal CON as the previous match code is immediately output. In order to prevent such inconveniences, the sound generation timing pulse TEPl with a width of 1 μs is set as a count pulse J2 (FIG. 9f), and this count pulse J2
(-TEPl) is applied to the count input of the coat pyramid counter 32 via the OR circuit 94. The timing at which the signal H2 becomes "1" is delayed by 1 μs from the sound generation timing pulse TEP1 (count pulse J2) due to the existence of the flip-flop JMOV. Therefore, the signal H
Immediately before the counter 32 enters the counting scanning mode when 2 becomes ``1'', one count pulse J2 is applied, and the contents of the code pyramid counter 32 are advanced by one step from the previous matching code. , the match detection operation for producing the next sound (second sound) is restarted from a state in which the contents of the code pyramid counter 32 are advanced by one step from the previous match code.

By increasing the number of the chord pyramid counter 32, when the counted value of the counter 32 becomes a value that matches the key code of the high-pitched key (G3 note) above the previous note (D3 note), that G3 note is 1 μs corresponding to the allocated channel time
A width match signal CON is output.

Similarly to the above, the signal H2 becomes ゛0''゜ and the counter 3
2 is stopped, and the matching code reading command signal LOAD2 is sent to the matching code storage circuit 7 via the inverter 95.
given to 5. Therefore, the memory circuit 75 stores the key code of G3 note B32B2) B1 la N42 N3 k N2 la N
It is rewritten to the same data as 1, 0101000゛. In this way, the coincidence code storage circuit 75 stores the coincidence signal CO.
Every time N is generated, it is rewritten with new data (matching key code). When the coincidence signal CON is generated, as described above, a 1 μs wide clear signal CCF is output in synchronization with the channel time to which the key code that generated the coincidence signal CON is assigned, and the corresponding tone forming sequence 16 is Sound generation begins in the channel.

Note that the octave switching designation signal FF does not change unless the count of the octave counter 84 (FIG. 7) changes. As described above, each time the sound generation timing pulse TEP is generated from the frequency dividing circuit 66 (FIG. 6), that is, at a period of time T, the counting scan of the counter 32 is restarted and the coincidence signal CON is generated.

When the counter 32 is incrementing in the counting scanning operation (up count signal U is "1"), the contents of the counter 32 match in order from the key code related to the bass key, so in the above example, the second note The coincidence signal CON related to the third tone is generated based on the key code of the G3 tone, and the coincidence signal CON related to the third tone is generated based on the key code of the B3 tone.
Therefore, when the counting mode of the chord pyramid counter 32 is up counting, sounds are produced in order from the lowest tones.

When counting down, sounds are produced in order from the highest tones. Here, the sound generation interval is macroscopically the same as the period T of the sound generation timing pulse TEP. 2nd note, 3rd note,
G3 sound, B3 sound, etc. are...
Channel time assigned to...
1 μs wide clear signal C generated in synchronization with...
In response to CF (in response to the falling edge), envelope signals EV are generated in sequence (every time T), and G3 tone, B3 tone, . . . are generated in order.

Octave slide control (Part 1) The octave slide amount specified by the octave switching designation signal FF is:
This corresponds to the contents of the octave counter 84 (FIG. 7).

Octave counter 84 is court pyramid counter 3
When the carry signal CARY is issued from 2, the count is advanced by 1. Therefore, the octave of the generated sound does not change and remains constant until the code pyramid counter 32 completes one counting scan (counts by the modulo number and generates the carry signal CARY). and carry signal CA
When RY is issued, the octave of the generated sound changes. The carry signal CARY is sent to the carry detection circuit 90 (Fig. 5).
generated from.

The carry detection circuit 90 includes an AND circuit 117 and a NOR circuit 118 to which the up counting command signal U and all bit outputs of the counter 32 are input, respectively. AND circuit 11
7 is enabled by the signal U representing the up counting operation of the counter 32, and when the output of the counter 32 reaches the maximum value (that is, all output bits are 1), a carry detection output 2 is generated. The output "1" from the AND circuit 117 passes through the OR circuit 119 and becomes the carry signal CARY when the counter 32 counts up. (Down counting command signal D1'') enables operation, and the output of the counter 32 is set to the minimum value (
That is, when all output bits become ``0'', a carry detection output ``1'' is generated. The output "1" from this NOR circuit 118 passes through an OR circuit 119 and becomes a carry signal CARY when the counter 32 counts down. Therefore,
When the chord pyramid counter 32 is in the up counting state, the counting scan of the counter 32 is restarted after T time from when the matching signal CON related to the key code of the highest key among the keys specified by the key code KC is output. In the process, a carry signal CARY is issued (by the AND circuit 117).

Further, when the counter 32 is in the down counting state, the counting scan of the counter 32 is restarted after T time from when the matching signal CON related to the key code of the lowest key among the keys specified by the key code KC is output. A carry signal CARY is output from the NOR circuit 118.

When the carry signal CARY is output, the counting scan of the counter 32 is temporarily stopped, and when the processing of the carry signal is completed, the counting scan is started again. B is the highest note among the three notes (D3, G3, B3) currently being pressed simultaneously on the lower keyboard.
Assume that three sounds are pronounced as the third sound.

At this time, the key code of B3 tone is stored in the matching code storage circuit 75 (FIG. 5). When the sound generation timing pulse TEP is generated T hours after the start of sound generation of the third note and applied to the code pyramid system control section 42, the signal H
2 becomes 1, and the counting scan of the code pyramid counter 32 is restarted. In other words, the key code N for the B3 note
The count clock J2 is applied to the counter 32, which has stopped at the same value as 1 to B3, and the contents of the counter 32 become the value obtained by adding 1 to the key code of the B3 sound, and then the system clock pulse SYl The count pulse J1 comes to be given at the timing of . The counter 32 is incremented by this count pulse J1, but B3
Key codes N1 to B3 with values greater than the sound key code
is not supplied in this case (at least for the lower keyboard), the count value of the counter 32 reaches the maximum value "111111F" without generating the coincidence signal CON.Then, the carry signal CARY is transmitted via the AND circuit 117.
is issued (Fig. 9 m). Carry signal CARY is 1
When it becomes ゛, the output of the inverter 91 becomes ゛0゛,
AND circuit 89 becomes inoperable, and the delay flip-flop
The memory of JMoV is erased, and the signal H2 falls to 0'' after 1 μs (see the 4T time domain column in Figure 9).

Furthermore, if the system clock pulse SY occurs while the carry signal CARY is output, the AND Output "1" is produced from circuit 120 and stored in flip-flop 76 via OR circuit 121.

When the output H1 of the flip-flop 76 becomes ``0'' after 1 μs, the signal ``1'' is circulated through the AND circuit 122 and stored since the system clock pulse SY1 has become ``0''.

When the system clock pulse SY1 occurs 12 μs later, the AND circuit 122 becomes inactive and the memory of the 7 lip-flop 76 is cleared.

Therefore, as shown in FIG. ), the conditions of the AND circuit 123 are satisfied and the octave switching pulse TRI with a width of 12 μs is generated.
G is issued (see Figure 9 0).

This octave switching pulse TRIG is passed through the line 124 to the delay flip-flop 1 for timing adjustment shown in FIG.
In addition to 25, an octave rise/fall control circuit 126
are added to each AND circuit 127-133. If the octave slide amount (content of the octave counter 84) currently being played does not reach the value set by the octave slide amount setting switch (not shown), an output "1" is generated in the AND circuit 127, and the OR circuit 134 is output. through and circuit 1
The signal "1" is applied to the AND circuit 135. Since the system clock pulse SYl is applied to the AND circuit 135, the signal "1" of 1 μs width is applied at the timing of the pulse SYl.
is outputted from the AND circuit 135 and added to the counting power of the octave counter 84. Therefore, the octave counter 84 is incremented by one. If the system clock pulse SYl is generated when the signal H1 generated based on the carry signal CARY is "1" and the signal H2 is "O", the AND circuit 136 (FIG. 5) generates the signal shown in FIG. 9g. Count pulse J3 is generated as follows.

This count pulse J3 is applied to the code pyramid counter 32 via the OR circuit 94. Also, under exactly the same conditions as the AND circuit 136, the AND circuit 137 (FIG. 5) outputs a signal "1" and is stored in the flip-flop JMOV. Therefore, 1 μs when count pulse J3 occurred
Later, the signal H2 becomes "1", and the counting scan of the counter 32 is restarted.If the up counting command signal U is still applied, the counter 32 is incremented from the minimum value 0.

When the contents of the counter 32 match the key code of the lowest note (D3 note), a match signal CON is output. This starts the production of the fourth sound. Note that when the AND circuits 97 and 98 of the octave storage circuit 67 (FIG. 7) become operational due to the coincidence signal CON regarding the fourth note,
Since the count of the octave counter 34 has been incremented by 1, data "0F" representing an octave slide amount of 1 is stored in the circuit 67. Therefore, the switching designation signals FFl, FF2, FF3 become 01',
The D3 note associated with the key code that generated the coincidence signal CON is slid up one octave to become the D4 note.
Therefore, the D4 sound is produced as the fourth sound. The octave counter is 84 until the next carry signal CARY is issued.
Since the content of does not change, the coincidence signal CON regarding the key code of G3 note and B3 note will be used as the 5th note and 6th note from now on.
However, even if the content of the key code KC output from the sound generation assignment circuit 15 (FIG. 1) is for G3 note and B3 note, the foot change circuit 19 outputs 1 by the octave change designation signal FF. Upper octave G4, B4
The sound will be changed respectively.

Therefore, the G4 sound and the B4 sound are sequentially pronounced as the fifth and sixth sounds. Octave Slide Control (Part 2) The maximum octave slide amount is set according to the performer's wishes using an octave slide amount setting switch (not shown).

Depending on the setting of this switch, octave slide amount setting signals 0SE1 and 0SE2 (FIG. 7) are provided. The relationship between the signals 0SE1 and 0SE2 and the octave 2 degree amount is as shown in Table 3. In Table 3, the meanings of octave slide amounts 0, 1, 2, and 3 are the same as in Table 2 above.

The octave slide amount setting signals 0SE1 and 0SE2 are applied to one input of an adder 139 of an octave comparison circuit 138 (FIG. 7). Signal 0SE1 is the lower bit, 0SE2
has the weight of the upper bit. Octave comparison circuit 1
38 is configured as a subtracter, and converts the counting output of the octave counter 84 into an octave slide amount setting signal 0S.
Subtract from E1,0SE2. By performing complement calculation in the adder 139 (the lower bit is always given "1" from the line 140), subtraction is performed, so the count output of the octave counter 84 is transmitted to the inverters 141 and 142. and adder 1.
39 other inputs. That is,
The octave comparison circuit 138 subtracts the current performance octave slide amount "0CTV2, 0CTV1" from the octave slide amount setting binary number "0SE2, 0SE1". When the current octave slide amount reaches the set value, the result of the subtraction is 00. Therefore, the output of the adder 139 becomes ``00''.The NOR circuit 143 inputting the output of the adder 139 detects that the current octave slide amount has reached the set octave slide amount, and outputs ``1''. arise. The output ``1'' of this NOR circuit 143 is applied to the octave rise/fall control circuit 126 as an octave slide amount match signal 0SEQ via an OR circuit 144 and a delay flip-flop 145 for timing adjustment. Further, when the current octave slide amount (0CTV1, 0CTV2) is 0, the AND circuit 146 operates and the octave slide amount 0 detection signal ZR becomes "1".

This detection signal ZR is sent to the octave rise/fall control circuit 12.
Used in 6. Up mode and turn mode "Up mode" is a system in which the notes corresponding to multiple keys pressed on the lower keyboard are sounded one by one in order from the low end, and this sequential sound is repeated over one or more octaves. , which produces the effect of repeated rises in pitch.

"Turn mode" is a format in which the above-mentioned tones are sounded in order from the low end, and then in order from the treble end, producing the effect of repeating the rise and fall of the pitch over one or more octaves. . In this embodiment, it is possible to select either the above-mentioned "up mode" or "turn mode". When selecting the up mode, close the up mode selection switch (not shown) and set the selection signal UM/TM to 'O'.

As a result, the up mode selection signal UM becomes "1" via the inverter 147 (FIG. 7), and the turn mode selection signal TM on the line 148 becomes "0".When the turn mode is selected, the above is different. Conversely, the up mode selection signal UM is ``0'' and the turn mode selection signal TM is ``1''.Special signal processing for the turn mode or up mode will not be particularly explained.

Therefore, the AND circuits 149, 150, 151, 152 and the OR circuit 153 in FIGS. 5 and 7 are related to this process.
, 154, 155, NAND circuit 156, adder 157,
Descriptions of delay flip-flops 78, 158, 159, 160 and signals H, 100, TP, LOAD, OCRE, etc. will be omitted. Regarding these matters, the patent application 1973
It is explained in detail in the specification of No. 78574 titled "Electronic Musical Instrument". For example, 3 of D3, G3, B3
Press the keys at the same time D3 → G3 → B3 → D4 → G4 → B
When trying to play a chord pyramid in the order of low notes such as 4→・・・・・・, the B3 key on the high note side is actually pressed several 100 μs earlier than the other keys D3 and G3. Suppose that

In this case, assuming that the waiting time setting circuit 12 is not provided, the code pyramid device 1 is activated at the same time as the first B3 key is pressed.
0 is activated, for example, B3 → D4 → G4 → B4 →
The B note is sounded first, D5→..., and the octave is also changed at the same time, making it impossible to perform as desired. However, when the waiting time setting circuit 12 is provided as in the above embodiment, the above-mentioned malfunction does not occur at all. In the above example,
Although the present invention has been applied to the processing of key press information for playing chord pyramids, it is not limited to this, and can also be applied, for example, to detecting chords (chords) formed by pressing multiple keys on a keyboard. The waiting time setting circuit related to this invention can be applied.

In short, the present invention can be applied to all cases where it is necessary to handle information regarding multiple keys operated simultaneously on a keyboard as if they were operated simultaneously in a circuit within an electronic musical instrument. As explained above, according to the present invention, a key operation dead time commensurate with human senses is provided at the beginning of key operation, so that the electronic musical instrument can be prevented from performing operations that the performer did not intend. (ie, malfunctions are prevented), and performance performance is improved.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the electronic musical instrument according to the present invention, FIG. 2 is a timing chart explaining the operation of the sound generation assignment circuit in FIG. 1, and FIG. 3 is a diagram of the envelope waveform stored in the envelope memory. A graph showing an example, FIG. 4 is a diagram explaining a method of illustrating logic circuit elements, delay flip-flops, and shift registers, and FIGS. 5, 6, and 7 are detailed examples of the code pyramid device shown in FIG. FIG. 8 is a detailed circuit diagram shown in three parts, FIG. FIG. 9 is a timing chart showing an example of the operation of the code pyramid system control section in FIG. 10... Code pyramid device, 11...
...Key operation detection unit, 12...Waiting time setting circuit, 32...Code pyramid counter, 42...
...Code pyramid system control section, 52...
...Waiting time counter.

Claims (1)

[Scope of Claims] 1. A key information generating device that detects a key press (or key release) on a keyboard and generates key information representing the detected key;
An electronic musical instrument comprising: a processing device that receives a plurality of pieces of key information generated from the key information generation device and executes a predetermined musical tone forming process based on the plurality of key information; a detection device that detects when any key is pressed (or released) on the keyboard based on key information; and a time measurement device that measures a predetermined time from the time when the detection device detects the key. An electronic musical instrument comprising: a control device that holds key information input from the key information generating device while the time measuring device measures a predetermined time and prohibits operation of the processing device. 2. The processing device includes a circuit for forming musical tone information that specifies musical tones to be produced based on the key information generated by the key information generating device, and a circuit for forming musical tones corresponding to the musical tone information formed by this circuit. An electronic musical instrument according to claim 1, comprising a circuit. 13 In an electronic musical instrument comprising a detection means for detecting a key press (or key release) of each key, and a means for executing a predetermined musical tone forming process based on information representing the detected key, The electronic musical instrument is provided with a control means for controlling processing operations in the processing means, assuming that all keys detected by the means are pressed (or released) at the same timing.