JPS6057571A - Video conversion system - Google Patents

Abstract

The binary coded data signal is divided into data blocks in the video translation system in accordance with the invention. n copies are made of each data block. Televison synchronization signals are added to the original data block and to the n copies thereof, the assembly thus forming a video data block. This video data block is transferred to a video processing device, for example, a video recorder in which it is recorded. When the video data block is recovered, the corresponding data block is recovered from the n+1 data blocks present.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a first apparatus for converting a binary coded data signal into a video signal;
a first connection terminal for exchanging binary encoded data with an external data source; and a second device for C conversion; and a second connection terminal for connecting the first device to the first connection terminal.
The device further comprises a register system for temporarily storing one data block at the same time, and receives the data signal in the form of continuous data blocks. 1st person cuff for 1"14
The child and the mixer are both on TV, JtJ.
a second input terminal for receiving the j signal, and an eighth input terminal connected to the output of the register system -(-VC),
1:1; the video data block is configured to form a video data block, which video data block includes a data block and a synchronization signal, and the register thread is further connected to the supplied television. and first means for cooperating with a synchronization signal to create an integral number of two copies of the data block, the copies being synchronized with the television synchronization signal and containing said original data block. In order to output the video data block, the output terminal of the mixer is connected to the second connection terminal VC, and the second
In addition to the synchronization signal separating device for separating the TV 1 synchronization signal from the video signal supplied to the second connection terminal, the second device further comprises The present invention relates to a video conversion system which also includes a recovery circuit for recovering corresponding data blocks from n+1 data blocks forming part of the blocks.

The 10-111 video conversion method is based on European Patent Application No. 4877.
It is known from No. 9. In the video conversion system described in this European patent application, a data block is extracted from a data signal by a first device each time a data signal is provided by a data source. This extracted data block is temporarily stored in a register system. In the register system n copies of such a data block are formed. These copies are made in order to significantly reduce the risk that data blocks related to video signal processing procedures will be transferred or stored incorrectly. The original data block and n copies are then transferred to a mixer, which adds a television synchronization signal to the data block and its copies to form a video data block. The video data block thus formed is output to a second connection terminal to which a video recorder is connected. Video data blocks are recorded in a known manner by a video recorder.

The second device extracts the data blocks again from the video data blocks recorded by the video recorder. For this reason, the second device is especially provided with a synchronization signal separation device,
This separates the television synchronization signal from the video signal supplied from the video recorder VC. The second device also includes a recovery circuit for recovering corresponding data blocks from the n+1 data blocks based on majority voting.

The decoded data block is then output to the terminal station. Thus, video recorders are used, for example, to store binary data from a computer.

However, the conventional video conversion method 1 as described above has the drawback that the data blocks are not recovered in synchronization with the television synchronization signal. Therefore.

Recovering data blocks takes a lot of processing time.

This has an adverse effect on the amount of data that can be stored per unit area of the storage means.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a video conversion method that reduces the associated drawbacks.

To achieve this objective, a video conversion method according to the present invention is as follows:
Synchronize with the television synchronization signal extracted to the recovery circuit 1! The present invention is characterized in that a second means for performing the 1-return processing is provided.

According to the present invention, since the corresponding data block can be recovered in the same manner as the extracted television synchronization number 8, the time required for recovery is shortened, and the configuration of the recovery channel 1 is also the same as the conventional one. It's much simpler than that. The television synchronization signal is provided by the same signal separator, and this synchronization signal is also a reliable signal, which allows the recovery circuit to operate properly. A faster number of times is advantageous for the amount of data that needs to be stored, and if the processing time required for recovery is short, the amount of data that needs to be stored can be reduced.

In a first preferred embodiment of the video conversion system according to the invention, the recovery circuit is provided with a majority circuit. In this first preferred embodiment, the output terminal of the synchronization signal separation device is connected to the input terminal of a shift pulse generator that generates shift pulses in synchronization with the synchronization signal, and the second device also comprises a shift register. , a data input terminal of the shift register is connected to the second connection terminal, the shift register has at least n sub-output terminals, and each output terminal of the shift register is connected to another input terminal of the majority circuit. and said shift register also has at least one control input terminal by which at least n data blocks from the supplied video data blocks are transferred to the shift register under the control of a first shift node. At the same time, the n suboutput terminals are operated under the control of the second shift pulse, so that the first and second shift pulses appear successively over time. Therefore, n+1 data For each block provided, one correct data block is recovered based on the highest voting total n.Since the shift pulses are generated synchronously with the synchronization signal, the sampling pulses are removed from the video signal. can be easily extracted.

Therefore, the configuration of the majority circuit can be simplified. It is preferable that the majority circuit determines the corresponding bit value bitwise from the n+1 bits supplied to it based on majority vote. Since the majority circuit operates at the bit level, this circuit 111M can be made in n++ only.

In another preferred embodiment of the video conversion system according to the present invention, the first input terminal is connected to a synchronization signal generator, and the control signal is generated by using the output terminal 14 of the synchronization (G) generator based on the synchronization signal V. Connect to the input terminal of the frequency divider.

In this preferred embodiment, said register system comprises an input register, the first f-ter input terminal of said input register being connected to the first data input terminal of a cyclic register of a combination register; a control input having an output terminal connected to an eighth input terminal of the mixer and a second data input terminal of the cyclic J%1 carry coupling register, the cyclic carry coupling register being connected to an output terminal of the frequency divider; and a cyclic carry coupling register for retrieving data blocks from said input register under control of a first control signal and for repeatedly loading data blocks via a second data input terminal. The n copies are made under the control of two control signals. In this case, since the control signal is generated based on the synchronization signal, a separate clock is not required to generate the control signal. Furthermore, the full use of the circular carry combine register ensures that the bits of the video data block occupy approximately the same amount of space relative to the television line when looking at the video signal as a whole. This is the backbone 4 for data recovery.

According to a second preferred embodiment of the "dirty" video conversion scheme, the recovery circuit comprises a majority circuit for recovering said corresponding data block. If you do this, (n
+1) Each time data blocks are supplied, the maximum number of votes? A correct data block is bitwise recovered from these (n+1) data blocks based on IVc. Furthermore, this type of majority circuit is advantageous in terms of the speed at which bits can be supplied to the second connection terminal.

In such a second preferred embodiment, the output terminal of the synchronization signal separating device is connected to the input terminal of a shift pulse generator that generates shift pulses in synchronization with the synchronization signal, and the second device also comprises a shift pulser, the data input terminal of the shift register is connected to the second connection terminal, the shift register comprises at least n sub-output terminals, and the valley output terminals are connected to another input terminal of the majority circuit. The shift register also has at least one control input terminal for shifting at least n data blocks from the supplied video data blocks under the control of a first shifter. n in the register and under the control of the second shift pulse.
Preferably, the first and second shift pulses ζ appear successively over time by activating the sub-output terminals. In this way, since the shift pulse is generated in synchronization with the synchronization signal, the sampling pulse can be easily extracted from the video signal. Therefore, the configuration of the majority circuit can be simplified.

According to a further preferred embodiment of the video conversion method according to the invention, the majority circuit shares an error signal output terminal for supplying an error signal indicating an error in the data block. By supplying the error signal in this manner, the bit error can be corrected by using this error signal and cooperating with the error l/dimeta.

Preferably, the majority circuit determines bitwise the corresponding bit value from the n+1 bits supplied to it based on majority vote. Since the majority circuit operates at the bit level, this circuit is easy to fabricate.

Preferably, a data block contains data for l television lines and a video data block G contains video data for un+1 consecutive television lines. Therefore, the capacitance of the register system and shift register can be of a limited capacitance value it, and further the register system is protected against drop-out in the longitudinal direction of the videotape)1. Ru.

(7) Preferably, the register comprises n series interconnected delay elements, each of which is provided with a control input terminal and an output terminal, and the output terminal is connected to a majority circuit. By choosing the number of delay elements equal to the number of copies of the data block, each delay element is provided with a control input terminal, resulting in a shift register that is easy to control.

The invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing a series of devices N1 for converting 231L coded data signals into video signals, which converters form part of the video conversion system according to the present invention. be. This first device l is, for example, f-1t-:
It comprises a first connection 14 to a data source 11, such as a l-yy heater or a data processing system.

The first JF8i terminal 14 is connected to an input terminal of a register system comprising an input register 2 and a circular block carry combination register 8. The data output terminal of the input register 2 is connected to the parallel data input terminal of the cyclic digit-piled combination register 8. Input register 2 and circular carry combination register 8 each have a bar control input i':! j (S and s'). The serial data output terminal of the cyclic carry combination register 8 is connected to the first input terminal of the mixer 7 and is also connected to the serial data input terminal 16 of the cyclic carry combination register 8 .

The first device l also comprises a recognition pattern generator 9, the output of which is connected to the parallel data input of the cyclic carry combination register 8. The output terminal of the mixer 7 is connected to a second connection terminal 15, to which a video signal processing device 8, such as a video recorder, is connected.

The first device l cooperates with the number circuit 17 synchronously. The synchronization signal circuit 17 in this example includes a clock 4, and the output terminal of this clock is connected to the synchronization signal generator 5 ((((also connected to the first input terminal of the frequency divider 6). 5 is of a known type, and clock 41C
The generator 5 generates television synchronization +Fk based on the supplied clock pulse J:υ, and sends these synchronization signals to the second input terminal of the mixer 7 and the second input terminal of the divider 6.
Supplied to the input terminal. The frequency divider 6 is especially configured to the first output terminal 1
2 & the first control signal outputted from the second output terminal '18
and generate a second control signal to be outputted to each of the first and second control signals. The first output terminal 12U of the frequency divider 6 is connected to the control input terminal S of the input register 2. The second output terminal 13 of the frequency divider 6 is connected to the control input terminal S' of the cyclic carry combination register 80 and to the control input terminal of the recognition pattern generator 0. The synchronization signal circuit 17 may be configured in whole or in part (for example, only by division 6).
It can also be integrated into the device 1. The television synchronization signal can also be supplied from an external signal source, in which case the synchronization signal circuit 17 does not include the clock 4 or the synchronization signal generator 5.

In this example, 16 bytes (1,28 pits) of data supplied by f-Yuso 11 are handled per television line. This data is coded, for example, according to the NRZ-code. Furthermore, in order to reduce the risk of inaccurate data, the same array is made to repeatedly view data from the same television line n times. In this example, the number of n is 4. It is preferable to set the value of n to an even number for reasons explained later, and in this case, the total number of times the same data is written (
n-1-1) is an odd number. The repetition of data for exactly the same television line within the same frame is related to the fact that the video signal is recorded with a spatial extent during recording to videotape. Therefore, the negative effects of high percentage drop-outs in magnetic tape are substantially reduced. Such a method is only one preferred example, and there are other methods of repeating data, such as repeating one frame n times. However, in this case, it is necessary to make the capacity of the input register and the circular carry combination register extremely high.

The data supplied by the data source 11 is shifted into the input register 2 under the control of a first control signal appearing at the first output terminal 12 of the splitter 6. Input register 2 in this example has a capacity to store a data block containing 16 bytes. The first control signal is data source 1 at -10,000.
1, and on the other hand, it has a frequency determined taking into account the need to ensure that the input register is filled during n+1 consecutive television lines.

Cheetah Block (1 Television Line) Ha.

It is transferred from the input register 2 to the circular carry-combined video register 8 under the control of a control pulse appearing at the second output terminal 18 of the division period 6. Such a control pulse is generated each time after n+1 consecutive horizontal synchronization pulses (determined by a counter, for example) have been repeated J7. A second control signal consisting of 128 shift pulses is applied to the second output terminal 18Vclii of the splitter 6 between each two consecutive horizontal VCs. Under the control of these 128 shift pulses, the data block in the cyclic carry combination register 8 is shifted to the mixer IKy and the data block is transferred to the feedback line 1.
0 and is also fed back to this register 8 via the serial data input terminal 16. The shifting to the cyclic carry combine register is repeated n+1 times for each television line supplied 11-.Therefore, the f-tuff' 0 to n numbers from the data source 11 are It happens that a copy of the data block is created tL.However, n
In response to the +1st horizontal sync pulse, the next data block is retrieved from input register 2 under control of the next control pulse.

The next data block is the circular carry combination register 8.
Erase previous data blocks that still exist.

Mixer 7 adds a television synchronization signal to each data block supplied from register 8 to form a video signal. The original data block, the n copies of the data block, and the summed synchronization signal form a video data block. This video data block is supplied to a video signal processing device 8 in the manner normally used for video signals. For example, a bit whose bit value is logical 1To11 is recorded as black, and a bit whose bit value is logical 1n is recorded as white.

To determine the correct Sands ring phase, a well-defined recognition pattern is applied to the data block. This means that the synchronization signal is slightly shifted relative to the data block.
This is necessary since it is possible to shift the data block slightly relative to the synchronization signal, or vice versa.

By adding such a recognition pattern, for example ]0100101, a phase correction can be made when reading the data again. FIG. 2 shows an example of a datab "hook" having a recognition pattern associated with the device of FIG. The recognition pattern 2o is placed at the beginning of the 01Um-ta block 22 in the undirected state.However, the recognition pattern can also be provided spread out between the ?:4F'tF5 VC of the data block or the data blocks.Recognition pattern causes the recognition pattern generator 9 to generate J:,p, and this pattern causes the cheater block to shift to the register 8 at the same time.Therefore, the recognition pattern generator divides the frequency to 7j upon receiving the control pulse. The second output terminal 18Vc of the device 6 is connected to the second output terminal 18Vc.

It is also possible to add a recognition pattern to the data for one television frame, in which case the recognition pattern generator 9 is controlled by a vertical synchronization signal. It is also possible to apply the recognition pattern to only a limited number of television lines of a frame, in which case the recognition pattern generator is also provided with appropriate control signals.

FIG. 8 is a block diagram showing an example of a conversion device 80 for converting a video signal into a binary coded data signal, and this second device 80 also forms part of the video conversion method according to the present invention. be. A video signal including video data blocks is output to the output terminal of the video signal processing device 8.
, each video data block contains a synchronization signal and several copies of one and the same data block. The video signal output terminal of the video signal processing device 8 is connected to the second connection terminal 50 of the conversion device 80 . This second connection terminal 50 is connected to the input terminal of the synchronization signal separation device 390 and to the limiter 25 . An output terminal of the synchronization signal separation device 89 is connected to a clock (pulse) regenerator 81 .

The output terminal of the limiter 25 is connected to the input terminal HVC of the clock regenerator 81, and also to the first input terminal of the first delay element 26 in the array of delay elements (26, 27, 28, 29) forming the shift register. Also connect. The array of delay elements consists of the same number of delay pieces as the number of copies to be made from the l-J light data block. Therefore, in this example, the array is composed of four delay elements. Each of these delay confections has a control input terminal (S″) connected to the output terminal of the clock regenerator 81. Each third delay confection (1≦
The output terminal of j<n-1, n=total number of delay elements) is (j+
i) th input terminal [connection and turn 4 (recovery)
It is also connected to the l-th input terminal of the circuit 82. Each third delay confectionery is provided with one input terminal of the associated first. The last (nth) delayed confectionery of said array (29)
An output terminal of the recovery circuit 82 is connected to a first input terminal of the recovery circuit 82 . The recovery circuit 82 has n+1 input terminals, and the (n+1)th input terminal is directly connected to the output terminal of the limiter 25. The output terminal of the recovery circuit 8z is connected to the register 88. This register 83 is connected to a first connection terminal 51 to which a terminal station 34, for example a computer, is connected.

The first device 1 shown in FIG. 1 and the second device 80 shown in FIG.
5 are the same as connection terminals 51 and 50, respectively.

The synchronization signal separator 89 extracts the television synchronization signal from the video signal supplied by the video signal processing device 8 and supplies this television synchronization signal to the clock regenerator 31 which regenerates the clock signal from it.

FIG. 4 is a j-block diagram showing an example of the clock pulse regenerator 81. In FIG. The synchronization signal (FIG. 5a) coming from the synchronization signal separator 39 (FIG. 3) is received by the phase control circuit 41 and the clock 45 via line 48. The synchronization signal controls clock 45. An input of register 40 is connected to input terminal H of the clock pulse regenerator and receives, in particular, a bit signal containing a recognition pattern. Phase control circuit 41 provides a control signal to register 40 via line 44 after receiving the horizontal synchronization pulse. Under the control of this control signal, the recognition 2 turns are extracted from the bit signal and stored in register 40vc. The phase control circuit 4.1 has an input terminal connected to the output terminal of the register 40, and this phase control circuit tests when a single pattern is received with respect to reception of a horizontal synchronization pulse. do. This test is performed, for example, by counting the number of clock pulses provided by clocks 4 and 5 during the period from when the horizontal synchronization pulse is received until the last bit of the recognition pattern is received.

Corrections for possible phase shifts are therefore made based on such tests. The phase control circuit 41 supplies a clock signal of the correct phase to the frequency divider circuits 4 and 2, which act as shift pulse generators. This shift pulse generator generates first shift pulses for delay elements 26, 27, 28 and z9, and these first shift pulses are output from output terminal 85. Furthermore, the %(n+1)th first
After the generation of the knot sequence, the divider circuit 42 also generates a second shift pulse, and these second pulses are output to the output terminal 86.
The signal is then supplied to the register 83.

Each delay element of the array in this example is formed by a shift register having sufficient capacity to store data for one television line (16 bytes or 128 bits). Under the control of a first pulse train of first shift pulses, data bits from a video signal generated by a video signal processing device are provided to a continuous V delay element 26. Once the 128 first shift pulses (128 bits/television line) have been supplied by the clock pulse regenerator 81, the data focus of the first television line is supplied to the delay element z6. As shown in Figure 5b, these 128 first shift Hals occur between two consecutive horizontal sync pulses (Figure 5a). Under the control of the next 128 first shift pulse trains,
The data bits are serially shifted from delay element 26 to delay element 27, and the data for the next television line is provided to delay element 26VC. Thus, under the control of a first series of pulses, the data bits are shifted through each delay element of the array, and the data bits of the respective television line are input. Therefore, in this example, the data bits of the first television line are caused to reach the delay element 29 using a pulse train of 4.times.(n=4) of the first shift pulse. After this first transmission line is shifted to the delay element 29, the effective data is lost during the period of the first shift pulse train.
It is output by Vc. In response to each shift pulse VC in the n11th pulse train of such first shift pulses, the data bits appearing at the output terminal of each data delay element as well as the data bits appearing at the output terminal of the limiter 25 are affected by the associated data bits of the recovery circuit 8z. Supplied to the input terminal.

The recovery circuit 32 includes a known majority voting circuit.

Recovery circuit 32 recovers only one correct bit value from the n+1 data bits 7) supplied thereto and shifts this bit value into register 88.

As mentioned above, it is preferable that the value of n be an even number. The reason for this is that in this case, n+1 is an odd number, so the majority decision circuit can always take a majority decision. Therefore, the recovery circuit 32 has only 1 power from the n+1 data blocks forming part of the video cheater block.
Only the corresponding data blocks are recovered, which approximately correspond to the original data blocks. In addition to recovering data blocks, the recovery circuit 82
An error signal may also be provided to the recovery circuit to indicate that an error has occurred in one of the n+1 data bits provided to the recovery circuit. Such error signals may also be provided to terminal station 84 for correction purposes.

The data line present in register 88 is provided to terminal station 84 under control of a second shift pulse (Figure 5C).

If a of the pulse train of g1 shift pulses does not correspond to a multiple of (n+1), data bits coming from two different video data blocks are provided to the recovery circuit 82. In this case, no valid data is output to the output terminal of the recovery circuit 82. However, if this becomes a problem, it will be a long time.

This is because the second shift pulse controlling register 8B prevents such invalid data from being provided to the end station. This setup has the advantage that no extra force control data is required in the recovery circuit.

It goes without saying that the present invention is not limited to the above-mentioned examples, and can be modified in many ways. For example, correction bits can be added to each data block. In this case, the array of delay elements can be constructed with only one register, and the recovery circuit can test whether the data block from the video data block is correct based on the added correction bits, and One correct data block Z displacement can be selected from the fixed data blocks.

[Brief explanation of the drawing]

Figure 2151 is a block diagram illustrating an example of an apparatus for converting a binary encoded data signal into a video signal; Figure 2 illustrates an example of a data block having recognition patterns associated with the apparatus of Figure 1; Signal waveform diagram; Fig. 8 is a block diagram showing an example of a device for converting a video signal into a binary coded digital mail; Fig. 4 is a block diagram showing an example of a clock pulse regenerator; Fig. 5 The figure is a waveform diagram showing a pulse pattern for controlling the device as shown in FIG. l... Binary code data signal/video signal converter 2... Input register 8... Circulating digit-Nige combination register... Clock 5... Synchronization signal generator 6...・・・
Frequency divider 7...Mixer 8...Video signal processing device 9...Recognition pattern generator 11...Data source 17
...Synchronization signal circuit 20...Recognition pattern 21...
・Synchronized Hals 22. ...Data block 25...Limiter 26-29...Delay element 82...Recovery circuit 88...Register 84,...Terminal station 89...Synchronization signal separation device 40...Register 4・l
...Phase control circuit 4.2...Frequency divider circuit 45...
clock. Patent applicant: N.B.Philips Fluirampenfabriken

Claims (1)

[Scope of Claims] A device for converting a binary coded data signal into a video signal; and a second device for converting the video signal into a binary coded data signal. a video conversion system, the video conversion system comprising a first connection connector for exchanging binary encoded data with an external data source; and a second connection terminal for connection to an external video signal processing device;
The first device further comprises a register system connected to the first connection terminal for receiving the data signal in the form of continuous data blocks and temporarily storing one data block at a time. , a first input terminal for receiving a television synchronization signal, and a mixer, the mixer having a second input terminal for receiving a television synchronization ID signal,
a third input terminal connected to the output terminal of the register system, the fifth R mixer forming a video data block, the video data block combining the data block and at least eleven synchronization signals; and said register system further comprises first means for producing an integral number of copies of the original data block in conjunction with the provided television synchronization signal, and synchronizing the copies with the television synchronization signal. adding the optical data block to the containing video data block;
an output terminal of the mixer is connected to the second connection terminal in order to output the entire video data block; In the video conversion method, the second device further comprises a recovery circuit for reversing a corresponding data block from n+1 data blocks forming part of the supplied video data block; The recovery circuit is
A video conversion system comprising second means for recovering the data blot in synchronization with an extracted television synchronization signal. In the video conversion method set as claimed in claim 1, wherein the recovery circuit comprises a majority circuit for recovering the corresponding data block, the output terminal of the synchronization signal separating device is connected to the synchronization signal and the synchronization signal. and connected to an input terminal of a shift pulse generator for generating shift pulses, the second device also comprising a shift register, and a data input terminal l of the shift register connected to the second connection terminal, a register comprises at least n sub-output terminals, each of these output terminals being connected to another input terminal of said majority circuit; said shift register also comprising at least one control input terminal; shifting at least n data blocks from the supplied video data blocks into the shift register under control of the first shift pulse and actuating the n sub-output terminals under control of the second shift pulse; A video conversion system characterized in that the first and 277th pulses appear continuously over time. 8. In the video conversion method according to claim 2, the majority decision circuit determines corresponding bit values from each bit set of n+1 bits supplied to the circuit based on the majority decision VC. Featured video conversion method. 4 Connect the first input terminal to the synchronization signal generator. A video conversion method according to any one of claims 1 to 8, wherein the output terminal of the synchronization signal generator is connected to the input terminal of a period-divider that generates the control signal based on the synchronization signal, The register system includes an input register, a first data input terminal of the input register is connected to a first data input terminal of a cyclic carry combination register, and an output terminal of the cyclic carry combination register is connected to an eighth input terminal of the mixer. A terminal array VC is connected to a second data input terminal of the cyclic carry coupling register, and the cyclic carry coupling register also has a control input terminal connected to an output terminal of the divider; and retrieving a block of data from the input register under control of a first control signal. A video conversion method characterized in that the n copies are made under control of a second control signal by repeatedly loading a data block through a second data input terminal. 5. In the video conversion method according to any one of claims 1 to 4, the data block includes data for one television line, and the video data block includes n
1. A video conversion system comprising video data for +1 continuous television line. & Scope of claims? and 5. The video conversion method according to 5, wherein the shift register comprises n delay elements interconnected in series, and each of these delay elements comprises a control input terminal and an output terminal connected to the majority circuit. A video conversion method with all the features. ? A video conversion method according to claim 6, characterized in that each delay element has a delay time corresponding to one television line.