JPS6057452A - Simulated input and output device - Google Patents

Abstract

PURPOSE:To transfer continuously plural data and to access to an optional address of a register by providing a memory part which holds plural transferred data, a mode register and a multiplexer. CONSTITUTION:A memory part 10 consists of plural memory parts holding data. A mode register 4 decides the 1st method which access to the memory parts successively or the 2nd method which access at random to the memory parts with the address information supplied from outside to access to the memory part. In other words, it is possible to transmit continuously data of different contents with addition of the part 10. Then using the register 4 makes it possible to use a memory part with both methods. Furthermore a memory part is formed in the depth direction to an input/output addressive an address counter 6 and an address bus (b) by means of a multiplexer 9. Thus it is possible to transfer plural data continuously and also to access to an optional address of a register.

Description

[Detailed description of the invention]

INDUSTRIAL APPLICATION FIELD This invention relates to a developed microcomputer and peripheral chip (1) MAL direct memo IJ access control output device. In recent years, with the development of microcomputers (hereinafter referred to as CPUs) and peripheral chips, it has become necessary to check access operations to input/output spaces, DMA operations, etc. for simulating human/output devices. The conventional simulated input/output device, which has become indispensable in the following, will be explained below. Figure 1 shows the Wlt configuration of a conventional simulated input/output device61
is an input/output address decoder that detects that its own address has been selected, and outputs a selection signal f if it matches the own address. 2 is an input/output register, and when the selection signal f is output, if the write status #A is output, the data bus a
If the read status [F] is held, the data bus a
Sends the contents of K input/output register 2. The operation of the conventional simulant/output device having an IC structure as described above will be explained below. Figure 2 shows a signal waveform diagram.
/7”l J-* 〃)7t118?1171.li
! i'l -F 11 S n YuL a* tlj
The signal WRT-c indicating whether the signal is for use in the first mode is at the high level. The CPU or peripheral chips have the following address:
The address information is output to the data bus a[tj, and the content to be read to that address is output. Furthermore, the strobe signal d
(DTSD-d This signal becomes a data request signal in the read state.) is output. The address decoder 1 sends out a response signal e (DTAK-e) and confirms that the data has been received by t1''. When the selection signal q is output, the input/output register 2 outputs the data bus a.
Retains the contents of. A signal waveform diagram in the read state is shown in FIG. 2 [Bl]. WRT-c is at L low level. As in the write state, address information is output from the CPU or peripheral chip to the address bus b, and a data request signal d L DT
SD-d) is output. Mock person on address bus b
When the address for selecting the output device is output, the input/output address decoder l outputs the selection signal f.
When the input/output register 2 is output, the input/output register 2 sends the contents held in the input/output register 2 to the data bus aK. The input/output address decoder 1 sends out a response signal e indicating that data is being sent. In this way, data was written to the person/output register 2 and read out to confirm the access operation of the person/output space. However, with the above configuration, it is possible to check whether the input/output space can be accessed for reading and writing single data, but since there are 11 input/output registers, it is difficult to perform operations that continuously transfer multiple different data. I can't confirm. In addition, for bottle stands and simulated input/output devices that use normal input/output devices such as floating disks and printers as simulated people and output devices, one input/output address is assigned to the device, and the input/output address is assigned to the device. - Instead of the Wi configuration, which holds data one by one in the address direction of the output space, it uses the W4 configuration, which holds multiple pieces of data at the same input/output address. In other words, the registers at one address have depth. However, there are problems such as not being able to access any position (address) in the depth direction, and in order to read or write data, it is necessary to access from the first data in the depth direction, which takes time to confirm. Purpose of the Invention The purpose of this invention is to solve the problems of the conventional Kamimi method, and its purpose is to provide a simulator/output device that can transmit multiple data continuously and can access any address in a register. Structure of the Invention The simulated input/output device of the present invention includes a plurality of storage sections that hold data, a first method of sequentially accessing the storage sections, and a method of randomly accessing the storage sections using address information supplied from the outside. a mode register that holds contents that determine which of the second access methods is used to access the storage unit;
An address counter that determines address information when accessing the storage unit sequentially using the first method, and address information of a dress counter whose own address is

[That is, the first method]
address information of the address path (i.e. the second method)
It is equipped with a multiplexer that selects one of the two, and enables transfer operations of multiple data and access to arbitrary addresses. DESCRIPTION OF EMBODIMENTS FIG. 3 is a 441 diagram of a simulated input/output device of the present invention. Reference numeral 1 denotes an address decoder that detects whether a simulated person/output device is selected. 2 is a simulated input/output device when accessing the storage section using address information supplied from the outside, that is, when operating as the input/output device of the second method, which has the storage section in the address direction of the input/output space. A memory address decoder detects that its own address is selected, and outputs a memory selection signal k when a simulated input/output device is selected. 3 is an address bus b, yDh supplied from the outside.
Looking at the diagram, when operating as the input/output device of the 10th method that has a memory section in the depth direction on the single person/output address space and sequentially accesses the memory, the self address of the simulated person/output bag is An input/output address decoder detects selection, and outputs an input/output selection signal l when a simulated person/output device hole is selected. Reference numeral 4 denotes a mode register that holds contents for determining the operation mode of the simulant/output device (whether to operate by the first method or the second method) and outputs a mode signal j. 5 is a selector for selecting either memory '9 selection signal k or input/output selection signal 4;
The 0 selection condition for outputting is determined by the mode signal Jvc. 6 is an address in the depth direction for sequentially accessing the storage unit 10 when operating the simulated person/output device as the input/output device of the first method. The address counter determines the input/output address signal 0 and outputs the input/output address signal 0. 7 is an AND circuit that outputs the counter signal n of the address counter 6. A controller 8 controls the mode register 4 and the address counter 6. Numeral 9 is a multiplexer which selects input/output address signal 0 or address bus b, and outputs a storage section address signal p to storage i10. 10 is a plurality of storage units that hold data. The concept of the operation mode of whether the m personification/output device is operated as an input/output device of the first method or an input/output device of the second method will be explained using FIG. The storage section is composed of n data storage sections. When operating as an input/output device using the second method (→
(Y direction), one data storage unit is allocated to one person/output address. The self-address of the simulated person/output device is up to address mNn. Viewed from address bus b, any data storage section can be accessed. When operating as an input/output device for the first method (-
For one person/output address (address m in FIG. 9), there are addresses in the depth direction (→X direction) at the bottom of the groove in a plurality of data storage sections. When viewed from the address bus b, one data storage section accessed by the input/output address signal 0 is visible only as an address field (C).The address information at this time is determined by the contents of the address counter 6.・The self-address of the output bag is address m. The data storage section accessed by address m+1 when operating as a person/output device of the second method is effective as input/output ii of the first method. 1m+2 corresponding to the data storage section to be accessed by address m+1 when
...The same applies to n-1 and nlc. The following is about the simulated person/output bag @ of this example, which has been completed as described above! ! Explain 0. Before operating the simulated transfer input/output device, set mode register 4.
The operation of setting the address counter 6 and resetting the address counter 6 will be briefly explained. R1 is a response signal that receives the strobe signal (data request signal) DTSD-d output from the CPU, peripheral chip 17'', etc. and generates the response signal e. generation circuit, 82
A controller address decoder 83 detects that the controller 8 is selected.
This is a recess 71 circuit that generates the rese VF signal i. The controller 8 is allocated on an address that does not overlap with the address of the simulated input/output device. CPU and peripheral chips
Before moving the simulated person/output device, the knob accesses the controller 8 and sets the operating conditions. Of the n bits of the data bus a, bit 0 is the bit that controls the mode register 4. 1 is the bit node that controls the address counter 6. FIG. 5 shows a signal waveform diagram when controlling the mode register 4. Since the WRT signal C is in the writing state, it is at H high level. When an address for selecting the address bus blc controller 8 is output, the controller address decoder 82 outputs a controller selection signal. At this time, period O of data/<s a becomes mode data g and is sent to mode register 4. The mode register 4 holds the contents of the mode data g at the rising edge of the controller general selection signal and outputs a mode signal j. The simulated person/output device operates as a person/output when the mode signal j is 1, and operates as a memory when it is 0. Figure 6 shows the input when the address counter 6 is controlled! Mode register 4' (il-11113111
Then, in the same way as above, the controller 8 is selected and the control selection signal is output. At this time, the contents of bit 1 of the data bus a (Fig. When the address counter 6 receives the reset signal i't:receive 1'j, the count value (input/output address signal % o ) is changed to the initial M value (9th
Set address m) in the figure. Simultaneous IC response signal generation times v
! r81 outputs a response signal e (FIGS. 5 and 6). FIG. 7 is a signal waveform diagram when the simulated person/output device operates as the input/output device of the first method. Address information for selecting the simulated person/output device on address bus b (Fig. 7, ■-I10 to 13) Strobe signal (data request signal) DTSD -d 75E If sent, input/output address decoder 3 outputs an input/output selection signal llo. Since the mode signal j is at the H/1 level, the selector 5 outputs the input/output selection signal 4 as the first week selection signal m. Further, the multiplexer 9 similarly outputs the input/output address signal O as the storage unit address signal p. The address set by the storage address signal p is accessed again by the CPU and peripheral chips. When the access is completed, the address counter 6 is counted up by the count-up signal n, and the input/output address signal O is increased by 1. ■l) Even if you transfer different data consecutively to access the next data storage section,
Previous data is guaranteed. Next, a case will be described in which the simulated person/output device is operated as the input/output device of the second method. FIG. 8 is a diagram of the signal waveform. The controller 8 is accessed and the mode register 4t is set to operate as an input/output device for the second method.
(Low level), address bus bK address information for selecting the simulator/output device (Figure 8. Since the mode signal i is at L low level, the selector 5 outputs the memory selection signal k.
is output as a storage section selection signal m. multiplexer 9
Similarly, the contents of address bus b are transferred to register address signal t.
Output as p (gg8 figure ■m, rn', rr
f, rn"), 7 address bus b sets the e storage section address signal p, making it possible to access any address in the storage section 10. As described above, according to this embodiment, For example, by providing a storage unit 1O that holds a plurality of data to be transferred, multiple pieces of data with different contents can be transferred continuously.Also, by providing a mode register 4, one storage unit can be It can be used in two ways, method 2. Also, as an input/output device for the first method, !Df11: Address counter 6 that determines the address of the storage unit IO when By providing a multiplexer 9 that determines which address information from the input/output address signal O and the address bus b is to be supplied to the storage unit i o vc, 1
A storage section can be configured in the depth direction for a person/output address. Effects of the Invention According to the simulator/output device of the present invention, there is an effect that a plurality of data can be transferred continuously and a neglected address of a register can be accessed. That is, (1) it is possible to confirm the IIOI operation in which a plurality of different data are continuously transmitted; (1) Data setting and access are possible when performing a D~F (direct memory access) operation for one person/output address in the storage section. ■ Also, if you switch the static mode and operate it as a memory, you can access any address in the storage section, so data modification is easy, and you can perform DMA transfer operations by rewriting data in one place. If confirmed, the time can be shortened.

[Brief explanation of drawings]

FIG. 1 is a groove bottom diagram of a conventional simulated input/output device ffl, and +A1 in FIG. IB1 is a signal waveform diagram thereof, FIG. 3 is a cause of i of a simulated input/output device in an embodiment of the present invention, FIG. 4 is a groove bottom diagram of a control section, and FIG. 5 is a signal waveform diagram of mode register control. , FIG. 6 is a signal waveform diagram of address counter control, FIGS. 7 and 8 are signal waveform diagrams of the simulated input/output device of FIG. 3, and FIG. 9 is a conceptual diagram of operation modes.

Claims (1)

[Claims] The first method uses a plurality of storage sections that hold data and sequentially accesses the self-storage sections, and the second method randomly accesses the storage sections based on externally supplied address information. Decide whether to access the storage section 1
- a mode register for holding the contents of the first register;
Using the method of The address counter determines the address 1 when accessing the 1 note 5 next time, and the first method or the second method is selected depending on the contents of the mode register, and the address is stored in the previous g storage section. A simulated person/output device equipped with a multi-chip Vxa that supplies information.