JPS60540A - Predicative logic type language processor - Google Patents

Abstract

PURPOSE:To compare a predicate with another predicate at a high speed, by providing plural buffer memories which can read out simultaneously as the processor of a predicative logic type language. CONSTITUTION:The internal expression of a paragraph composed of a series of predicates consisting of their names and referring numbers in stored in a storage device 100. The stored internal expression of a paragraph is read out to buffer memories 102, 104, 106, and 108 by appointing an address of the device 100 through an address register 101 under the control of a control section 113. Also under the control of the control section 113, out of the outputs of each buffer memory one is selected by means of a selection circuit 110 and another one is selected by means of another selection circuit 111, simultaneously, and the selected data are sent to the control section 113. At the control section 113, readout from the buffer memories selected by means of the selection circuits 110 and 111 is simultaneously performed and predicates are compared with each other at a comparator 112, and thus, coincidence between predicates can be detected.

Description

[Detailed description of the invention] [Technical field to which the invention pertains] The present invention relates to a predicate logical language processing device.

[Technological environment]

A predicate logical type language processing device is a device that processes a predicate logical type language written as a set of clauses consisting of a predicate name and its argument (a series of predicates). This will be explained using an example.

In prolog, the event to be expressed is expressed by a ``predicate'' consisting of a combination of a predicate name and its argument, and the relationship between the predicates is also described. For example, the phenomenon ``Fatbe likes fruit'' can be described as follows.

Prefer (fat 9 tatami) ← Fruit (bone) In this example, ``prefer'' and ``fruit'' are predicate names, and ``fat'' and ``norimono.''
is called an argument, and the blue mark indicates that the argument is a variable. In other words, in the upper part, ``fat''``likes'' the thing written as an argument of the predicate written with the predicate name ``fruit.''
It expresses that.

Therefore, if the sentence ``1 fruit (strawberry stone'') is written elsewhere, the conclusion ``Fatbe prefers strawberries'' can be reached by reasoning using syllogism.

The application area of the prolog mentioned above is expanding as a predicate logical type language. However, in order to further expand the usage area, it is necessary to improve the processing efficiency of the program.

[Prior art]

Conventionally, this prolog processing has been realized on a general-purpose computer. However, it was not possible to process the prolog program at high speed due to constraints due to the hardware configuration of general-purpose computers.

The execution of a prolog program is basically a process of comparing matches between predicates. For example, the above “...←fruit (
Bone movement. The basic process is to compare ``and fruit (strawberry)'' to check for a match between the two predicates.To achieve this process at high speed, both predicates are read out at the same time and the predicate name and the argument that follows it are read out simultaneously. It is necessary to check the matches sequentially.

However, in conventional computers, reading from a storage device is only possible from one word or one unified area at a time, and it is not possible to read from separate areas at the same time. This situation is similar to the cache memory that realizes a high-speed buffer function in conventional computers, and the cache memory can only be referenced from a single word or area from the processing unit side.◎This hardware configuration This is a limitation when processing prolog programs at high speed on conventional computers.

[Purpose of the invention]

The present invention provides a device that is capable of quickly comparing a predicate and a predicate by being equipped with a plurality of buffer memories that can be read simultaneously, as a processing device for a predicate logical language such as a prolog. It is something.

[Structure of the invention]

According to the present invention, in a device that processes a predicate logical language written as a set of clauses consisting of a series of predicates constituted by a predicate name and its argument, a memory for storing an internal representation of the clause in the device is provided. a device, a plurality of buffer memories for temporarily storing internal representations of clauses read from the storage device, and a first selection of selecting one of the outputs of the plurality of buffer memories as an output. a selection circuit for selecting one of the outputs of the plurality of buffer memories as an output; a stack mechanism and an internal register for holding a path that successively traces the relationship between the predetermined words; and a buffer memory management function and a selection designation function in the two selection circuits, and one of the outputs of the plurality of buffer memories is selected by the first selection circuit and sent to the plurality of back 7 memory control devices. A predicate logic type language processing device is obtained, characterized in that a coincidence between predicates can be detected by simultaneously reading data from the buffer memories selected by the two selection circuits. .

[Explanation of Examples]

An embodiment of the present invention will be described in detail below with reference to the drawings.

In this embodiment, the prolog predicate is expressed in the following format.

Predicate name (Argument 1, Argument 2, etc.) Arguments can be constants or variables, and variable arguments are distinguished by putting an ax at the beginning. A sentence in the prolog is called a clause, and its form is as follows.

Predicate 1 ← Predicate 2. Predicate 3. ..., predicate n← is a logical symbol, and there are at most three predicates that can exist on the left side of it. This is called the head part, and the part to the right of the ← mark is called the body part, and the 1 and ' marks that separate the predicates on the body side represent the logical product between the predicates. The general form above is predicate 2. Predicate 3. ...,
It expresses that when the logical product of predicates n holds true, predicate l holds true, and this form is called a rule clause.

-As a special form of the membrane type, a clause consisting only of a head part is called a declaration clause, and a clause consisting only of a body part is called an interim clause.

Program execution of the prolog is performed in the following steps.

(1) Find a clause whose head part has the same predicate as the predicate that appears in the body part of the clause. Here, the arguments of both predicates are compared in the order in which they are arranged to check for a match. If all the arguments match here, the process moves to step (2). If all the arguments do not match, the process of step (1) is repeated.

When comparing arguments, if -10,000 is a variable and the other is a constant, the value of the constant is bound to the variable. Furthermore, if both are variables, -10,000 is rewritten as a pointer to the other so that they take the same value.

This double process also satisfies the matching condition.

(2) Control transfers to the processing of the body of the clause whose predicates are found to match as a result of the comparison in step (1), and returns to step (1). If the clause is a declaration clause, step The process moves on to the subsequent predicate in the body of the first referenced clause in (1). If there is no subsequent predicate, all processing ends.

FIG. 1 shows an example of a prolog program. "Pi" in the diagram
, @P2'' is the predicate name, ta), , n , uBn.

6C"/"D"p1E" is a constant argument/*X".

“Y”+”*z” is a variable argument. Section 1 is the theory of company regulations], Section 2. Clause 3 is a declarative clause, and clause 2 and 4 are makeshift clauses.

The processing flow of this program will be explained below.

Program execution begins with a makeshift clause. In the example shown in Figure 1, the first predicate 1p1(*x, *y) of clause 4 is processed. Clause 1 is found in step (1), and all arguments match, so step (2) ).

Here, the constant value @A” of clause 1 is bound to the variable view * It is shown that they are equal.

In step (2), the body part of node 1''P2 (B, C
, *z)", and returns to step (1) to check for a match with clause 2 which has the predicate name "'P2" as the head part. Since there is a mismatch, the predicate name "P2" is next set as the head part. The body part of clause 1 and the head part of clause 3 match, and the process proceeds to step (2). The constant value 6A" is bound. As a result of the above processing, the values of the variable 6*y" and the variable 1*z" are equal, so the variable "*y" is bound.
The value of is also a constant value "A".

Since clause 3 is a declaration clause in step (2), control returns to the processing of clause 1. Since there is no predicate following the predicate ``''P2(B,C,*z)''K in the body of clause 1, the processing of clause 1 ends and control is passed to the processing of clause 4, which passed control to the processing of clause 1. returns.As a result of the processing so far, the constant value V is bound to the variable "*x" IIC in clause 4, and the variable I
Similarly, the constant value "'A" is bound to I*Y19.

Next, since the second predicate "Pi (*x, *x)" of clause 402 is not to be processed, clause 1 is found in step (1), and as a result of comparing the arguments, a match of the predicates is recognized. In this argument match check, the value of the variable "*x" is the constant value uA obtained by the above processing. Furthermore, since the value of variable "*2" in clause 1 is also the same value as variable 1*x", it becomes a constant value "A'. The variable "*z' has a constant value of 6A in the processing of the first predicate "'PI(*x+*)')" in clause 4."
However, the predicate ``P1(*x
, *x)", the node l is a new processing target.

At this time, the value of the variable "*z'h% constant" is an unbound variable, and is bound to the value 6A" of the variable 6*x" for the first time in the process of step (1).

Hereinafter, in step (2), the body part of clause 1 is processed, and the body part of clause 1, which is processed in step (1), does not match the body part of clause 2, but matches clause 3. Next step (2)
Okay, as a result of processing the second predicate of clause 4, a match is returned to clause 4, and all processing ends.

In the apparatus of this embodiment, the format shown in the example of FIG. 2 is used as the internal representation of the prolog section.

FIG. 2 is an example showing an internal representation corresponding to section 1 of the prolog program shown in FIG. In the device of this embodiment, each node has an internal representation described in a group of areas as shown in FIG. This internal representation for each clause is called a "code." Each line in FIG. 2 is called a word, and one word consists of a tag field and a value field. The tag field holds the attribute information of the word, and the value field holds the value corresponding to the attribute indicated by the tag.

The word "header" at the beginning of the code holds information regarding the entire code. That is, it holds information on the number of unique variables in the information section 9 indicating whether the code corresponds to a rule clause, a declaration clause, 2 makeshift clauses, etc.

A "pointer", which is the second word of a code, holds link information to a clause having the same predicate name as the code as a head part.

The third word corresponds to the predicate name "'P1" in clause 1, and has a tag field indicating that it has the predicate name as a value, and a value field indicating that the predicate name is specifically "PI". have In the fourth word, the tag field indicates that the attribute of the first argument "A" of the predicate "'P1 (A9 year old t)" is an atom, and the value field indicates that its value is @A #. In the fifth word, the tag field indicates that the attribute of variable 1*z, which is the second argument of predicate wp1(At*z), is a variable, and the variable is the first variable that appears in clause 1. The value field has a number (0) indicating that it exists.

Below, the predicate name "P2" of the body part of clause 1, the argument "B",
uC" and '11*z" are the 6th to 9th words in Figure 2, respectively.
words correspond. Here, the fact that the variable 6*z" of the 9th word and the variable "*2" of the 5th word are the same variable is indicated by the same variable number (0) in the value fields of these words. .

FIG. 3 is a diagram expressing the program example of FIG. 1 using the internal representation described above. na in the value field in the diagram
ll indicates the end of the memory link 0 clauses 1, 2
, 3.4, four codes are expressed.

In order to specify the clause to be compared when checking for a match with a predicate that has the same predicate name as the head of the predicate name of the body part, the predicate name of the body part has the same predicate name in the head part. Contains the address of the internal representation corresponding to the clause. These relationships are shown by dashed lines in the figure.

Clauses whose head parts have the same predicate name are linked by a pointer, which is the second word in the code. For example, clause 2 and clause 3
are clauses that have the same predicate name in the head, so clause 2 is linked to clause 3.

FIG. 4 is a block diagram showing one embodiment of the apparatus of the present invention. In the figure, 100 is a storage device that stores the internal representation described in the explanation of FIG. 3 in the form 11, and 101 is a storage device 100.
The address register 102.104.106.108 is used to read the code stored in the storage device 100.
Buffer memory A1 which temporarily stores the code read from buffer memory B, buffer memory C, buffer memory D, 103゜105, 107, 109 indicates the words of buffer memory 102゜104, 106, 108, respectively. The useless buffer pointer A, buffer pointer B, buffer pointer C, buffer pointer D, 110 are the four backup memories 102, 104, 106, 10.
A first selection circuit A that selects one output from eight outputs.
, 111 is the above four buffer completion notes 1J102゜10
4. Second selection circuit B for selecting one output from the outputs of 106 and 108, 112tj: Comparison for detecting a match by comparing the words selected by the selection circuit A110 and the selection circuit B111. The comparator 112 not only detects whether the bit patterns of two input words match, but also detects a match when comparing a word indicating a variable with a word indicating a constant. 113 is a stack mechanism, an internal register, and each buffer memory 102, 10;
4.106.108 and the storage device 100, and controls the movement of other components based on the coincidence detection signal from the comparator 112. Since the control unit 113 can be realized with a configuration similar to that of a conventional processor, its internal mechanism will not be particularly described.

In FIG. 4, when the address specified by the address register 101 is sent to the storage device 100 via the address line 201, the output is sent to each buffer memory 100 via the bus 202.
, 104, 106, 108. The data on the bus 202 is stored in the four buffer memories 102, 104, 10.
6,108. This storage destination selection is performed by the control unit 113. Buffer memory Al
Outputs from O2, B104° C106, D108 are sent to selection circuit A110 and selection circuit B111 via data lines 203, 204, 205, 206, respectively.

The selection circuit A110 and the selection circuit B111 select one of the signals on the data lines 203, 204, 205, 206 as an output, and output the signals on the data lines 207, 208, respectively.
Output to. Signals on data lines 207 and 208 are both input to comparator 112 and control section 113. Comparator 1
A match signal, which is the result of the comparison in step 12, is sent to the control unit 113 via a signal line 209.

The control unit 113 inputs the match signal on the signal line 209 and the signals on the data lines 207 and 208 to operate the stack mechanism and registers provided in the control unit 113. Furthermore, the control unit 113 sends a signal to update the contents of the address register 101 in order to control reference to the storage device 100 via the signal line 212, and a signal 4 as a destination for storing data read from the storage device 100. Buffer memory AlO2
, B104° C106, D108, a signal for selecting one of C106, D108, a reference pointer A103, a back-off pointer B105, and a signal to control these buffer memory references.
It checks whether data that needs to be transferred from the storage device 100 is already stored in the memory device 106 and 108, and determines whether data transfer is necessary or not.
0 and the selection circuit B111 selects O. Below, the execution operation of the example program shown in FIG. 1 in this embodiment will be explained using FIGS. 3, 4, 5, and 6.

The storage device 100 stores the prolog program shown in FIG. 1 in the format shown in FIG. 3. Data in the storage device 100 is stored in each buffer memory 1 as the program is executed.
02, 104, 106, and 108. Figure 5 (
a)(b)(c)(d) show the respective buffer memories 102 and 1 when the processing of the prolog program shown in FIG.
04, 106, 108 storage state step numbers, the buffer memory selected by the selection circuit A110 and the address of the word referenced in the selected buffer memory, the buffer memory selected by the selection circuit B111 and the selected buffer. The address of the word referenced in the memory, the output of the output 1 selection circuit B111 of the selection circuit All0, the internal register information and stack information of the control unit 113, and the operation in the execution step are shown in this order.

In FIG. 1, clause 4 represents an inquiry instruction in the prolog. That is, execution begins with a makeshift clause such as clause 4, which consists only of the body part.

The internal representation of node 4 is stored sequentially from address CL4 in storage device 100 in the format shown in FIG. Control part 1
13 stores the CL4 address in the address register 101,
Execution begins by reading its contents. In the initial state, each buffer memory 102, 104, 106, 1
08 is empty, and the code of clause 4 is not stored. Therefore, the code corresponding to clause 4 is stored in the buffer memory AlO2.As a result, as shown in Figure 5, the internal expression 8 words corresponding to clause 4 are stored from address 20 to address 27 of buffer memo 1JA102. be done.

The control unit 113 stores the start address 20 of the code of clause 4 in the buffer pointer AIO3, reads out the "header" and "pointer" of clause 4 in sequence, and then reads out the word corresponding to the first predicate. This word has as a value the address of clause 1 which has the same predicate name in its header, and reads the code corresponding to clause 1 from the storage device 100. The code of node 1 starts the process of step 1 shown in FIG. 6 below O stored in the buffer memo 1JB 104 according to the instruction from the control unit 113.

In step 1, the buffer pointer AlO3 has node 40.
The address 22 indicating the storage destination of the code corresponding to the first predicate 1(*x+*y)" is stored, and the buffer pointer B105 stores the address 120 indicating the storage destination address of the clause 10 "Header 1 word. has been done.

Corresponding to each address (rough memory AIO
2 outputs the predicate name "=P1" of clause 4 to the data line 203, and from the outer memory B104 outputs the "header" of clause 1 to data@204. The selection circuit A110 selects the buffer memory Al in response to the selection instruction signal 210 of the control unit 113.
You will be prompted to select the O2 output. As a result, the predicate name 1'' of node 4 is output to the data line 207.The selection circuit B111 is instructed to select the output of the rough memory B104 by the selection instruction signal 211 of the control unit 113. As a result, the "header" of clause 1 is output to the data line 208.The information contained in this header is related to the attributes of the code, and does not itself affect execution control. ) Steps forward the draft pointer B105 and enters the execution step state.

In step 2 of FIG. 6, the company buffer completion pointer B105 points to the "pointer" following the "header" of clause 1, and the resultant buffer memory B104 outputs the value of the "pointer" to data 11J204. This "pointer" is link information to a clause having the same predicate name in the head part, but when it is the last link, its value is "1 null". In a makeshift clause such as clause 4, the "pointer" is always "null". Buffer pointer old 05 continues to increment.

In step 3, the buffer completion pointer B105 points to address 122 of the rough memory B104, and outputs the predicate name "Pi" of clause 1 to the data line 204 as the output of the rough memory B104. Here, a buff note! JA10
The output of No. 2 is the first predicate name of Clause 4, which is "Pi" like the output of buffer memory B104. Selection circuit Al
Since l0 selects data on data line 203, node 4
The predicate name ``'P1'' of node 1 is output to the data line 207. Since the selection circuit B111 selects the data of the data line 204, the predicate name -p 1m of node 1 is output to the data line 208. The outputs of the selection circuits 110 and 111 are input to the comparator 112, and since both of the input data have the predicate name @PI, a match signal is sent to the control unit 113 via the signal line 209. L in the control unit 113
Based on this comparison result, in order to make the word following the word currently being compared in clause 1 and clause 1 the comparison target in the next step, buffer pointer AlO3 and buffer pointer B are set.
105 respectively.

In step 4, make a buff note! The output of jA102 is “*”, which is the first argument following the first predicate name “P1” in clause 4.
X", this "*X" becomes the output of the selection circuit A110. The output of the buffer memory B104 is the value of the first argument following the predicate name parameter P1" of clause 1, this - A'' becomes the output of the selection circuit B111.

Each output is sent to comparator 112 via data lines 207 and 208. The variables 'ton*x'' and 'A'' satisfy the matching condition, and the comparator 112 sends a matching signal to the control unit 113 via the signal line 209. The control unit 113 secures the word variable "*X" at the top 0 of the stack and sets its value to 'A'. Through this process, the word variable '*X' is set to 'A'.
A” is marked Indian.

Buff end pointer AlO3 and Nogurafuto pointer B
105 respectively step.

In step 5, the variable * * y n, which is the second argument following the variable "* The variable 1*L", which is the second argument following , becomes the output of the buffer memory B104 and the output of the selection circuit B111. In the comparator 112, the variable 1*y" and the variable 1*t
” satisfies the matching condition, and the signal line 2 is connected to the control unit 113.
A match signal is output via 09. In the control unit 113,
The first word on the stack is stored as the word for variable "*y", and the second word is stored as the word for variable 6*z".
In order to show that the variable "I*z" and the variable "'*z" should have the same value, store the pointer value to the variable "*y" in the word variable "I*z" and refer to the variable "6*z". Sometimes the variable “
The value of *y'' is referred to. Then, the buffer pointer AlO3 and buffer pointer B105 are incremented.

Through the process of detecting a match between the predicate name and all the arguments in the predicate, it is found that the first predicate in clause 4 and the predicate in the header part of clause 1 match. This controls the node 1
The process proceeds to match detection between the body part of and a clause whose head part has the same predicate name as the predicate name of the body part.

In step 6, the predicate name in the body of clause l is buffer memo! The output of jB104 is "P2", and the control unit 113 is
Obtain the address to node 2 whose head is "P2".

Before shifting the control to match detection for the predicate name ``'P2'', the address indicating the second predicate name 1P1'' of clause 4 is sent to the control unit 1.
13 NEXT register. This means that when a predicate match is detected in the comparison process of the predicate "'Pz (B, C, *z)" in the following, the control is transferred to the second predicate "PI (*x, *z)" in clause 4.
x)". At the same time, the address indicating the predicate name "=P2" in the body part of clause 1 is stored in the MTf'tY register of the control unit 113. Predicate "'P2(B, C,
*z)” and the predicate to be checked for matching P2 (B, D, E)”
When the match test result with the clause with the head part is inconsistent, the clause 3 with the predicate °'Pz(H,C,A)'' in the head part
This is to start the comparison from the predicate "'P2(B, C, *B)#" again.

Processing for this mismatch will be shown after step 7.

Here, the addresses stored in the NEXT register and the RETRY register are addresses 25 and 125 corresponding to the preceding word name "Pl" and the preceding word name "P2" stored in the storage device 100, respectively. The correspondence between the addresses of each buffer memory 102, 104, 106, and 108 and the address of the storage device 100 is realized using the buffer memory management function of the control unit 113.

In step 7, the header at the beginning of the code in clause 2 is referenced. Since clause 2 is not stored in the buffer memory, it is read from the storage device 100 into the buffer memory C106.

After storing in the buffer memory C106, the value of the buffer pointer 0107 becomes address 150 indicating the header of section 2.

In step 8, the pointer in clause 2 is referenced. The value of this pointer is stored in the LINK register, which is an internal register of the control unit 113. This causes the predicate 2 (
The purpose is to save the address information for this node 3 in the control unit 113 in order to start a match check with node 3 having B, C, A)', and the LINK register is set in step 8. Indicates the operations involved.

In step 9, a match of the predicate name 6P2'' is detected.
Step 05.

In step 10, a match is detected because the first arguments of the predicate name "P2" are both "B".

In the following step 11, there is a mismatch because the argument of clause 2 is "D" and the argument of clause 1 is 'C'.This result is sent from comparator 112 to control unit 113 via signal a209.

In the control unit 113, in order to start comparison with another clause whose predicate name in the head part is aP2'', that is, clause 3, step 1 is performed.
2, in order to re-examine the coincidence regarding the statement rtup2+Btc+*z)" in Section 1, we compare the REs that were previously compared.
0 to store the value 125 of the address in the buffer memory B104 corresponding to the address to the predicate name "P2" of clause 1 of the TRY register in the buffer pointer B105;
The contents of the previously saved LINK register are the address to clause 3, and clause 3 is the predicate of clause 1 @p2(B, C,
*z)” is not stored in any buffer memory, so the code of clause 3 is stored in storage device 1.
Buffer memo via bus 202 from 00! JD108
is stored in

From step 12 to step 17, the predicate ``'P2(B, C, *Z)'' of clause 1 and the predicate u p 2(
B, C, A)" is detected. In step 17, "A" is bound to the variable 1*z.

As a result, "A" is stored in the area of variable 1*y, which is pointed from the area of variable "*z" in the stack.

Through the above processing, the first predicate of clause 4 “Pi(*XJ*y
)” is completed, and then the processing proceeds to the second predicate of clause 4, tlPl (*x + *x)”. Second
Since the predicate name of the predicate is "-p1" like the predicate name of the first predicate, a match with clause l is checked. Since clause 1 has already been stored in buffer memo 1JB 104, there is no need to read it from storage device 100. From step 18 to step 23, the predicate "PI (A, *z)" of clause 1
A match is detected.

In the subsequent processing, we check whether the predicate "P2 (B, C, *z)" of clause 1 matches clause 2, and since there is a mismatch, we check whether it matches clause 3, and if the results match, we check clause 4. Processing of the second predicate ends. Since the following predicate is strong in clause 4, the entire processing of clause 4 ends.

Comparator 112 outputs a control signal to control section 113.

This comparator 1120 function can also be considered as part of the control section 113. In the description of the embodiment shown in FIG.
is shown separately from the control section 113 in order to explain that the outputs from the selection circuit A110 and the selection circuit B111 can be referenced and compared at the same time.

〔Effect of the invention〕

As is clear from the above description, according to the present invention, processing of a predicate logical language typified by prolog can be executed at high speed.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an example of a prolog program, FIG. 2 is a diagram showing an internal format in this example, and FIG. 3 is a diagram showing a storage device image when the program example in FIG. 1 is converted into an internal format. FIG. 4 is a block diagram showing an embodiment of the apparatus of the present invention, and FIGS. FIG. 6 is a diagram showing an image of the stored internal representation, and is a diagram showing execution steps when the program example of FIG. 1 is executed by the embodiment shown in FIG. 4. 100...Storage device, 1o1...Address register, 102...Buffer memory A11
03...Baku7 pointer A, 104...
・Buffer memory B, 105... Buffer pointer B, 106... River ・Buffer completion memo IJc, 107.
...Buffer pointer C, 108...Buffer memory D, 109 ...Buffer pointer D1110...Selection circuit A, 111...
・Selection circuit B, 112... Comparator, 113...
...control section. Agent Patent Attorney Uchihara Oto 1! It PI (A Sai Z > PI (B, e, water: 1) 7P2 (β, D, E 8e 3 PZ (B, e, A to 14 - PI (<; l) t Vji, PI and <z
, t, z).姶 / 2 Figure 7

Claims (1)

[Claims] In a device that processes a predicate logical language written as a set of clauses consisting of a series of predicates consisting of a predicate name and its argument, there is provided a storage device that stores an internal representation of the clause, and a storage device that stores an internal representation of the clause, and a a plurality of buffer memories that temporarily store internal representations of the nodes; a first selection circuit that selects one of the outputs of the plurality of buffer memories as an output; and a first selection circuit that selects one output from each of the plurality of buffer memories; a second selection circuit that selects one of the outputs as an output; a stack mechanism that maintains a path to successively follow the relationships between the preceding words; and a management function for internal registers and buffer memory; a control device including a selection specifying function in a selection circuit and a comparison function for checking the coincidence of the predetermined words; one selection circuit selects the other one of the outputs of the plurality of buffer memories, the second selection circuit selects the data selected by the two selection circuits, and transmits the data selected by the two selection circuits to the control device. A predicate logic language processing device characterized in that a match between predicates can be detected by simultaneously reading from two buffer memories selected by the two selection circuits.