JPH0566941A - Data processing system and language processing system - Google Patents

Abstract

PURPOSE:To suppress the useless consumption of a memory which stores the interim computing result in a logical language that treats a double precision floating point by storing the output data in a memory part designated by a register which designates the input data through a processing means. CONSTITUTION:An exclusive addition (addt) instruction is provided for execution of an operation of the interim result. The addt instruction obtains the interim computing result consisting of two words in a step 64 and then checks whether the registers r0 and r1 that are designated with input are identical with a register r2 designated with output or not. If an input register can be broken after the coincident is checked between the input registers r0 and r1 and the output register r2, the computing result is written in a memory area used for the input data. Thus the interim result is stored in the same area as that of the input data even though the interim result is outputted as the output data. Thus the useless consumption of the memory area can be prevented.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing system and a language processing system, and more particularly to a prolog processing system which handles a floating point number composed of two or more words.

[0002]

2. Description of the Related Art As a processing method of prolog, a document "An AbstractProlog Instru
action Set, TR309, SRI (198
3) ”. K. There is a method based on register-based argument processing, which uses the DWarren abstract instruction set. In this method, the instruction string of the predicate is executed with the arguments used in the predicate calling on the register before the predicate calling.

For example, according to this method, the source program shown in FIG. 5 is expanded by a compiler into an instruction sequence as shown in FIG. In FIG. 6, 1 is an addition instruction.
Operate three registers, register number R0, R
Designated by 1, ... R5, the contents of the first register and the contents of the second register are added, and the result is returned to the third register. Two
Is a unification instruction that unifies two designated registers. Reference numeral 3 is an instruction for completing the execution of the predicate and returning to the calling source.

The question shown in FIG. 7 is given to this program. First, the caller sets the arguments in order. For example, the first argument is set in the register R0, the second argument is set in the register R1, and so on, and then the called program sum is executed. The state at this time is shown in FIG.
Six registers R0 to R5 are used. Each register has a tag section 4a and a value section 4b. The tag portion stores the attribute of data, where int is an integer and ref is a pointer that points to a specific address in the memory. Reference numeral 5 indicates a value cell storage memory, 5a is its tag portion, and 5b is its value portion. undf indicates an undefined variable. In this program, each addition instruction 1 uses the register R0 as an output register, and the unification instruction 2 destructively uses the register R0 to obtain the final result. Therefore, the state shown in FIG. 9 is obtained after the program is executed. That is, the result remains in the register R0, and the value is written in the memory pointed to by the register R5 unified with the result.

The above is an example of the case where the argument is an integer that can be expressed by one word, but if this argument extends over two words or more, a problem occurs. For example, in the case of a floating point number represented by two words, no value is stored in one register, so a pointer indicating the address of the memory storing the value is written in the register, and the floating point number is written in the tag section 4a of the register. Write the tag flt indicating For example, in the case of the question shown in FIG. 10, the states of registers and memories before the program is executed are as shown in FIG. 6 is a stack memory for storing the value part of a floating point number, and 7 is a pointer pointing to the top of the stack. In this state, the add instruction 1 is executed. The processing flow of this addition instruction 1 is shown in FIG. First, in step 61, the input data type is checked, and if it is an integer, it is directly calculated between the registers as in the above example. In the case of the floating point number in this example, the value of the memory pointed to by the flt type data is read out in step 63, and the internal register Rt0 is read.
~ Load to Rt3. Next, at step 64, the floating point numbers represented by the two registers are added together, and the results are stored in registers Rt0 and Rt1. Next, at step 65, the address of the memory for pushing the result is written in the register designated by the operand r2 as data with the flt tag. In step 66, the result is pushed onto the stack 6. That is, the states of the register 4, the memory 5, and the memory 6 after the execution of the first add instruction are as shown in FIG. In this way, since the stack is used as a storage location for the result for each add instruction, after executing the add instruction four times,
And after unification instruction 2, register 4,
The states of the memories 5 and 6 are as shown in FIG.

[0006]

Since the conventional processing method performs the processing as described above, the memory 6 is consumed for an intermediate calculation result. In this case, the intermediate result is not referred to by others, so it becomes garbage in the memory and cannot be released unless execution of the predicate fails or garbage collection is not started. During that time, the memory was continuously occupied unnecessarily, which was a big problem from the viewpoint of efficient use of the memory.

The present invention has been made to solve the above problems, and an object thereof is to obtain a data processing system and a language processing system capable of suppressing the use of an unnecessary memory area.

[0008]

The data processing system according to the present invention is provided with another processing means for obtaining an intermediate result, and the processing means reuses the memory area used for input to obtain the result. It is configured to be stored, and has the following elements. (A) A register that specifies input / output data for data processing, (b) a memory unit that is specified by the register and stores the input / output data, (c) a register that specifies input data and output data. Processing means for storing output data in a memory section designated by the register designating the input data in predetermined data processing in which the registers are the same register.

Further, the language processing system according to the present invention is
The present invention relates to a compiler that outputs the processing means as a predetermined instruction, and has the following elements.
(A) The input step of inputting a predetermined command of the first language for data processing, and (b) that the input variable used in the predetermined command of the first language input in the input step is not referred to by others. A check step of checking, (c) an output step of outputting a second language instruction that enables the output variable used in the instruction to use the memory area allocated to the input variable based on the check in the check step.

[0010]

In the data processing method according to the present invention, the processing means stores the output data in the memory section designated by the register for designating the input data.
Even if the intermediate result is output as output data, it is stored in the same area as the input data, and unnecessary consumption of the memory area can be prevented.

The language processing method according to the present invention is
In the check step, it is checked that the input variable used in the instruction of the first language is not referred to later, and when it is found that the input variable is used only once, the output variable of the instruction is used in the output step. Since an instruction for making the memory area the same as that of the input variable is generated as the second language, it is possible to prevent unnecessary consumption of the memory area when executing the data processing in the second language.

[0012]

【Example】

Example 1. An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram showing an example of a second language of the invention described in claim 2, and is a result of compiling the source program of FIG. 5 (an example of the first language) according to the present invention. In FIG. 1, 1 is a conventional add instruction, 2 is a conventional get-
value-t instruction, 3 is a conventional processed instruction,
Reference numeral 8 is an addt instruction which is an example of the processing means according to the present invention.

FIG. 2 is an example of a processing flowchart of the processing means (addt instruction). Steps 61 to 66 are the same as the conventional add instruction. In the addt instruction, after the operation result consisting of two words is obtained in step 64, steps 67 and 69 for checking whether the registers r1 and r2 designated by the input and the register r3 designated by the output are the same are added. .. 67 is the register r0 of the first input,
It is checked whether they match the output register r2, and if they match, the area of the first input can be used for writing the result. That is, in step 68, the calculation results Rt0 and Rt1 are written into the memory address indicated by the contents of the register designated by r0 and the address next thereto. Also,
If the second input register r1 matches the output register r2 in step 69, the operation results Rt0 and Rt1 are similarly set in step 70 to the memory address indicated by the contents of the register designated by r1 and the next address. Write to.

FIG. 3 shows the states of the register 4, memories 5 and 6 after the execution of the query of FIG. 10 with the instruction sequence of FIG. 1 using the addt instruction 8. In the stack memory 6 (an example of a memory unit), the portion holding the intermediate result pointed to by R0 is repeatedly used, so the stack pointer S does not extend by more than 2 words, and wasteful memory consumption is suppressed.

Next, FIG. 4 shows an algorithm of the instruction selection of the compiler for outputting the instruction code string of the second language shown in FIG. 1 from the instruction of the first language shown in FIG. First, in step 139, an instruction in the first language shown in FIG. 5 is input, and it is determined whether the instruction is one that selects the add instruction (input step). Next, the conditions of the input variables designated as r0 and r1 of the add instruction are checked. That is, in step 140, it is checked that it is a variable generated as the output of the operation instruction, and in step 141, it is checked that it is not referenced by other than the self instruction (check step). When this condition is satisfied, one addt instruction is output. If not satisfied, one add instruction as usual is output (output step).

As described above, in this embodiment, the logical language processing system including the registers handles a floating point number having a length of two words or more and has a memory area used for storing the floating point number. Regarding the processing method of the logic language, if the same register is specified for the input register and the output register in the operation instruction, the function to directly write the output value to the memory area specified by the contents of the register is provided. The logical language processing method characterized by having the operation instruction has been explained. Further, the logical language processing method having the compiler characterized in that the arithmetic instruction is inserted by judging from the appearance position of the input register of the source program of the logical language has been described.

Embodiment 2. In the above embodiment, the case of the addition instruction is shown, but the present invention is not limited to the addition instruction and may be a subtraction instruction or another operation instruction.
Also, other data processing instructions may be used.

Example 3. In the above embodiments, the case of the prolog processing system is shown, but the present invention is not limited to the prolog processing system and may be a lissp processing system or other logical language processing system. Also, other programming language processing systems may be used.

[0019]

As described above, according to the first aspect of the present invention, since the memory area for holding the result can be reused by the processing means, unnecessary expansion of the memory area can be suppressed.

Further, according to the second invention, it is possible to select the application portion of the processing means of the first invention from the first language such as the source program without omission, and the second memory does not use an unnecessary memory area. It becomes possible to execute data processing by language.

[Brief description of drawings]

FIG. 1 is a diagram showing an application program of a language processing method according to the present invention.

FIG. 2 is a processing flowchart of processing means according to the present invention.

FIG. 3 is an explanatory diagram of states of registers and memories after execution of a program according to the present invention.

FIG. 4 is a processing flowchart of the compiler according to the present invention.

FIG. 5 is a diagram showing logical language source programs of the present invention and a conventional embodiment.

FIG. 6 is a diagram showing an example of a program according to a conventional processing method.

FIG. 7 is a diagram showing a question program for integer arithmetic according to a conventional processing method.

FIG. 8 is a diagram showing a state of registers and a memory before executing a program shown in FIG. 7 according to a conventional processing method.

FIG. 9 is a diagram showing states of registers and memories after the program of FIG. 7 is executed by the conventional processing method.

FIG. 10 is a diagram showing a question program for floating-point arithmetic for explaining the conventional processing method of the present invention.

FIG. 11 is a diagram showing states of registers and memories before executing the program shown in FIG. 10 according to a conventional processing method.

FIG. 12 is a processing flowchart of an arithmetic instruction according to a conventional processing method.

FIG. 13 is a diagram showing states of registers and memories during execution of the program shown in FIG. 10 according to the conventional processing method.

FIG. 14 is a diagram showing states of registers and memories after the program of FIG. 10 is executed by the conventional processing method.

[Explanation of symbols]

1 add instruction by a conventional processing method 2 unification instruction 3 instruction that appears at the end of predicate execution 4 register 4a register tag section 4b register value section 5 value cell storage memory 5a value cell storage memory tag section 5b value cell storage Value part of memory for use 6 Floating point data storage stack memory (an example of memory part) 6a Tag part of floating point data storage stack memory 6b Value part of floating point data storage stick memory 7 Stack pointer 8 addt instruction according to the present invention

Claims (2)

[Claims] 1. A data processing system having the following elements: (a) a register for designating input / output data for data processing, (b) a memory unit designated by the register for storing the input / output data, (c) ) A processing means for storing the output data in a memory section designated by the register designating the input data in a predetermined data processing in which the register designating the input data and the register designating the output data are the same register. 2. A language processing method (a) having the following elements:
An input step of inputting a predetermined command of a first language for data processing, and (b) a check for checking that the input variable used in the predetermined command of the first language input in the input step is not referred to by others. Step (c) An output step for outputting an instruction in a second language that enables the output variable used in the instruction to use the memory area allocated to the input variable based on the check in the check step.