JPS6053084A - Manufacture of rom - Google Patents

Abstract

PURPOSE:To manufacture a finished product in a short time by writing informations by writing informations by using the change of the threshold voltage of a plural floating gate type field-effect transistors by the projection of ultraviolet rays or X-rays. CONSTITUTION:MOS FETs 43, 44, 45 are each constituted by n<+> layers 28, 30, 32 (source regions), n<+> layers 29, 31, 33 (drain regions) and floating gates 34, 35, 36, and these FETs are mutually isolated electrically by p<+> layers 26, 27 as channel-stoppers. Predetermined informations are written to an ROM by projecting ultraviolet rays 47 for a fixed time through a passivation film 42 consisting of films 39, 40, 41 applied and formed on an Al electrode 38 by using a photo- mask 46 prepared in response to informations to be written to the ROM, thus completing the ROM. Accordingly, threshold voltage VT viewed from the Al electrode 38 of the MOS FETs is controlled by the projection of ultraviolet rays 47, and the predetermined informations are written to the ROM by the value of VT.

Description

[Detailed description of the invention] Industrial applications The present invention relates to a method for manufacturing a ROM.

Problems with Backpack Technology Hitherto, masks R and OM (read-only memory) have been manufactured by the following method. That is, as shown in FIG. 1A, a p-type silicon substrate (11 surface IC5i0
2 membrane f21 and (J p soil layer t31 f41 !51
(Cha\ne)L/-7°Totsupa), and the above 5i
After applying photoresist on the n2 film (2), RO
The photoresist (6) (71
form.

Next, the 8i02 film (2a
) A p+ layer (8) is formed immediately below. Next, after removing the photoresist (f6H7), gates (9) (101) made of polycrystalline silicon are formed as shown in the fflIB diagram, and then using these gates +91 (101 as a mask), for example, arsenic ( The source region (111f1
2+ and drain area 03)04) are formed. Thereafter, a 1M fabrication process is performed according to a known n-channel silicon gate process to complete the mask R10M. Note that in FIG. 1B described above, the gate (9), the source region circle, and the drain region 03) are connected to
5+, MO8F E T il[il
Although only two MOS FETs are shown, in reality, a large number of MOS FETs are formed on the p-type silicon substrate (1).

In the above manufacturing method, by selecting the channel doping ion implantation conditions described above, the MOS FB
The threshold voltage (T) of T (151) can be set to, for example, 5 or more. On the other hand, the threshold voltage (T) of MOS FET (flit) which is not subjected to channel doping (V, P of flit can be set to, for example, 0.6 to 1.Ov) Therefore, for example, vT is 5
■If data “1” corresponds to the above state, and data “0” corresponds to the state where A is 1V or less, the MOS
FET [5) IC has data “1”, but also MOS FE
This means that T(16) lcLL data rOJ has been written by fL. In this manner, in the above manufacturing method, VT is controlled by ion implantation, and predetermined information is written into the ROM by 4F depending on the level of VT.

The above-mentioned manufacturing method has the advantage that ROMs can be mass-produced because information can be written on a board-by-board basis, but it has the disadvantage that it takes a long time to manufacture ROMs. There is. This I9 is due to the following reason. That is, normally, the mask R, O'l (for example, as shown in FIG. Party B proceeds with the manufacturing process described above using a photomask made according to the information to be written.
This is because many steps must be performed from exposure using the photomask to completion of the ROM.

OBJECTS OF THE INVENTION In view of the above-mentioned problems, the present invention provides a method for manufacturing a ROM that has the advantages of the method for manufacturing a mask ROM and can write information into a finished product in an extremely short time. The purpose is to

Summary of the Invention A method for manufacturing a ROM according to the present invention is a method for manufacturing a ROM in which each of a number of memory cells is formed of a floating gate field effect transistor formed on a semiconductor substrate. A source region, a drain region, a floating gate, and a gate insulating film constituting the effect transistor, and a passivation film covering the surface of the floating gate field effect transistor are formed, respectively, and then prefabricated according to the information to be written. Using a predetermined photomask, the plurality of floating gate field effect transistors are selectively irradiated with ultraviolet rays or X drops through the passivation film. Information is written using the change in the threshold voltage of the transistor caused by the irradiation.

By doing so, it is possible to write information into the ROM to produce a finished product extremely easily and in a short time, and it is also possible to mass-produce ROMs.

EXAMPLE An example of the ROM manufacturing method according to the present invention will be described below with reference to the drawings.

FIGS. 2A to 2G are cross-sectional views showing an embodiment of the ROM manufacturing method according to the present invention in order of steps. The steps will be explained below in order.

As shown in FIG. 2A, a p-type silicon substrate (1) having a specific resistance of, for example, 100 m is coated with a thickness of 500 m by thermal oxidation.
5in2 film + 21) of X, then this 5in2 film
Si3 with a thickness of 100 OA is deposited on the film (21) by OVD method.
A N4 film (22) is deposited. Next this SH3N41
:6 After applying photoresist on (22), predetermined patterning is performed to form photoresist (2311).
,7!4+ (25) is formed.

Next, as shown in the second FS diagram, a photoresist 1231
(Using 241 (25) as a mask, 5i5N4 film (2) is etched and 5r5N4 film (22a) (22b) (2
2c), and then the photoresist (231(2)) is formed.
Using 41 (25+ again as a mask), for example, boron (Bl) is ion-implanted under the conditions of 100 KeV and lx10 cm to form a p+ layer 6) (27).

Next, after removing the photomask C13) (241f251), 5i5N4 film (22a) (22b) (22
c) The part of the SiO2 film (21a) not covered with (
21b) to a thickness of 1μ as shown in Figure 2C.
A 5in2 film (21c) (21d) (field oxide film) of m is formed. Note that during the above thermal oxidation, the p+ layer (2
G+ (27) is S r 02 film (21c) (21d
) as it grows, it is pushed into the depth direction, and
It extends both in depth and in the lateral direction.

Next, as shown in FIG. 2D, a Si 5N 4 film (22
a) After patterning (22b) (22c) to form Si 5N4 films (22d) (22e) (22f), for example, arsenic (As) is applied to the entire surface at 150 Ke.
N+ layers (28) to C33) are formed by ion implantation under the condition VllxIQ''C1n-2 (7).

Next, the 5i02 film (21e)'' (
21D is thermally oxidized to have a baseness of 1 and 3 as shown in Figure 21.
000A StO2 films (21k) to (2ip) are formed. In addition, during the above thermal oxidation, the n layer C? 81- (33
) is pushed in the depth direction to an appropriate size as the SiO2 films (21k) to (2ip) grow, as well as in the depth direction and in the lateral direction, similar to the p + 10 layer 76)C27) shown in Figure 2C. It's expanding.

Next, the Si and NA films (22dX22e) (22f) are etched away, and the SiO2 film (2D) is partially etched to remove the top surface (1a,) (1b) of the p-type silicon substrate.
) (Ic) is once exposed and then thermally oxidized again to inject 500A of Sin into this exposed area. flu
(21qX21r)(21s) (gate insulating film) is formed. Next, as shown in FIG. 2F, a polycrystalline silicon film with a thickness of 200 OA is deposited on the entire surface by the CVD method, and then a floating gate is formed by performing predetermined patterning.
(34) C3:'i! (forms 361. Then C
After forming a SiO2 film (c37) as an interlayer insulator by a VD method, an Al electrode (038) is further formed on this 5i02 film (3η) by a vapor deposition method. After this, the above hp'a electrode (5 inches each was deposited on top of the pipe by CVD method) 2 membranes, PS
A passivation film (42) with a 6-layer structure consisting of a G film (40) and an 8i02 film (42) is formed.In FIG.
layer (291 (drain region) and floating gate 04) MO8F E T (431 is the i layer (a+)
(source region), n layer 0υ (drain region) and floating gate (35) make MO81i”
4), the broken breakdown layer t32+ (source 'jA region), n-soil layer (t) (drain region), and floating gate (MOS Ii" E T 14:i) are respectively configured by 36+, and these MOS FET (431 (1) (4
51 constitutes the memory cell of ■(, 0λ4. And the above MOSFET (49 (44) (4e is
p-layer (',!6) as a channel stopper!
27) and are electrically isolated from each other by 11. Note that in FIG. 2F and FIG. 2G (described later), the T electrodes leading out of the source region and the drain region are omitted.

next,! ”, 2 G I￥l, a photomask (46+
(A mask pattern (46b) made of chromium (Or) is formed on the glass plate (46a)) is used to irradiate ultraviolet + W (47) for a predetermined period of time. According to this 1,
Write predetermined information into the ROM based on Principle 1, which will be described later (1), and complete the ROM.0 The information stripping method described above is based on the principle described below. That is, in Fig. 2G, the ultraviolet rays (■ seen from the Al electrode side of 1νi 08 F E T (44) where the phrase is not irradiated) are about 0.1 D (see Fig. 6), but the ultraviolet rays, ?&( 47) was irradiated with MOS FET (
431 (■ and r in 451 indicate that due to this ultraviolet irradiation, electrons near the top surface (Ia) (Ic) of the p-type silicon substrate cross the barrier of the gate insulating film (5in2 film (21q x 21s) and form a floating gate 434) (gG) As a result of being stored in 0.8V
Data “1” is set in the above state, and ■T is 0.8 V.
When data “0” corresponds to each of the following states, M
OS FET (431 (45) Is the data “1”?
Also, MOS FET (441 has data rOJ
Each of them was carved into the rock. In this way, ■T of the MOS FET is controlled by irradiation with ultraviolet rays (47), and predetermined information is stored in the ROM according to the height of
can be written to.

In the embodiment described above, as shown in FIG. 2G, the memory cell MOS FET (431
) (451 and passivation film (42), photomask 06) is used to form MOS FET (451) and passivation film (42).
31 (45), the above passivation film (42)
selectively irradiates ultraviolet rays (4 rays) through the
The above MO8F ET (49d(
4F; rO) VT O) Change wo use i"'CI'j O
Mlc+W report is being written. Therefore, as with the mask ROM described above, information can be written on a board-by-board basis, which makes it possible to mass-produce If and OM.
<43 (441 (45) and passivation film (
42), the second FIR
Information can be written to the final ROM using the process shown in I. Moreover, the time required to write this information is extremely short, at most 20 minutes as shown in FIG. Therefore,
It is possible to write information to ft0M and create a finished product in an extremely short time. It is extremely simple because information can be written using only ultraviolet irradiation.

In the embodiments described above, information is written using ultraviolet rays, but information may be written using X-rays instead of ultraviolet rays. Also, floating gate type fvl O
If S F E T is Jl, MOS FE'I' (43
'1 (4 (J (15) L Hansu 61m construction (7) MOS
M
OS FET (43i (44) (4) has a different shape of the source region and drain region.
T u51 (FIG. 1B) may constitute a memory cell.

Effects of the Invention According to the ROM manufacturing method according to the present invention, it is possible to write information to a ROM and make it into a finished product easily and in a short time, and it is also possible to mass-produce ROMs. .

[Brief explanation of drawings]

1A and 1B are cross-sectional views showing a conventional method for manufacturing a mask ROM in order of steps, and FIGS. 2A to 2G are cross-sectional views showing an example of a method for manufacturing an OM according to the present invention in order of steps. , Fig. 6 is a graph showing the change in ■1 due to ultraviolet irradiation.In the symbols used in the drawing, m...................................p-type silicon substrate (
2)・・・・・・・・・・・・・・・5in2 membrane (6X
7)・・・・・・・・・Photoresist+91+
101......Gate electrode (II) [
2+・・・・・・・・・ Source area (13) α4
)・・・・・・・・・ Drain region (21)・
・・・・・・・・・・・・・・・5i02 film (Sakaki・・・・
・・・・・・・・・・・・Si3N4 film (23) (24X
2 ■・・・・・・・・・ Photo cyst (3 distribution ω (3G
)・・・・・・Floating gate (37)・・・・・・
......S io 2 membrane 08)...
・・・・・・・・・Al electrode (gate electrode) (4th electrode)
・・・・・・・・・・・・Passivation film (4G
)・・・・・・・・・・・・・・・ Photomask (47
)・・・・・・・・・・・・・・・Ultraviolet light. Agent Masaru Saturn 2F Figure 2G Figure 149 Par Figure 3

Claims (1)

[Claims] A ROM in which each of a plurality of memory cells is a floating gate field effect transistor formed on a semiconductor substrate.
A manufacturing method comprising forming a source region, a drain region, a floating gate, and a gate insulating film constituting the floating gate field effect transistor, and a passivation layer 11σ covering the surface of the floating gate field effect transistor, respectively. Then, using a predetermined photomask prepared in advance according to the information to be written, the plurality of floating gate field effect transistors are selectively irradiated with ultraviolet rays or X-rays through the passivation film. , whereby the above-mentioned ultraviolet rays or X-rays! ) A method for manufacturing a ROM, characterized in that information is written using a change in the threshold voltage of the transistor due to six shots.