JPS6053059A - Resin molded semiconductor device and manufacture thereof - Google Patents
Resin molded semiconductor device and manufacture thereofInfo
- Publication number
- JPS6053059A JPS6053059A JP58160387A JP16038783A JPS6053059A JP S6053059 A JPS6053059 A JP S6053059A JP 58160387 A JP58160387 A JP 58160387A JP 16038783 A JP16038783 A JP 16038783A JP S6053059 A JPS6053059 A JP S6053059A
- Authority
- JP
- Japan
- Prior art keywords
- resin
- mold
- semiconductor device
- resin molded
- molded semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 229920005989 resin Polymers 0.000 title claims abstract description 50
- 239000011347 resin Substances 0.000 title claims abstract description 50
- 239000004065 semiconductor Substances 0.000 title claims abstract description 36
- 238000004519 manufacturing process Methods 0.000 title claims description 10
- 239000008188 pellet Substances 0.000 claims abstract description 16
- 238000007789 sealing Methods 0.000 claims abstract description 10
- 239000002344 surface layer Substances 0.000 claims abstract description 4
- 238000000034 method Methods 0.000 claims description 7
- 238000000465 moulding Methods 0.000 abstract description 3
- 239000002184 metal Substances 0.000 abstract 4
- 239000002131 composite material Substances 0.000 abstract 1
- 239000000047 product Substances 0.000 description 6
- 229910000831 Steel Inorganic materials 0.000 description 5
- 239000010959 steel Substances 0.000 description 5
- 230000007547 defect Effects 0.000 description 4
- 239000006082 mold release agent Substances 0.000 description 4
- 239000000853 adhesive Substances 0.000 description 3
- 230000001070 adhesive effect Effects 0.000 description 3
- 238000005452 bending Methods 0.000 description 2
- 238000005336 cracking Methods 0.000 description 2
- 239000012467 final product Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229910001030 Iron–nickel alloy Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 230000000052 comparative effect Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000007598 dipping method Methods 0.000 description 1
- 238000006073 displacement reaction Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000002156 mixing Methods 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 230000008646 thermal stress Effects 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B29—WORKING OF PLASTICS; WORKING OF SUBSTANCES IN A PLASTIC STATE IN GENERAL
- B29C—SHAPING OR JOINING OF PLASTICS; SHAPING OF MATERIAL IN A PLASTIC STATE, NOT OTHERWISE PROVIDED FOR; AFTER-TREATMENT OF THE SHAPED PRODUCTS, e.g. REPAIRING
- B29C33/00—Moulds or cores; Details thereof or accessories therefor
- B29C33/12—Moulds or cores; Details thereof or accessories therefor with incorporated means for positioning inserts, e.g. labels
- B29C33/123—Moulds or cores; Details thereof or accessories therefor with incorporated means for positioning inserts, e.g. labels for centering the inserts
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B29—WORKING OF PLASTICS; WORKING OF SUBSTANCES IN A PLASTIC STATE IN GENERAL
- B29C—SHAPING OR JOINING OF PLASTICS; SHAPING OF MATERIAL IN A PLASTIC STATE, NOT OTHERWISE PROVIDED FOR; AFTER-TREATMENT OF THE SHAPED PRODUCTS, e.g. REPAIRING
- B29C33/00—Moulds or cores; Details thereof or accessories therefor
- B29C33/12—Moulds or cores; Details thereof or accessories therefor with incorporated means for positioning inserts, e.g. labels
- B29C33/14—Moulds or cores; Details thereof or accessories therefor with incorporated means for positioning inserts, e.g. labels against the mould wall
- B29C33/16—Moulds or cores; Details thereof or accessories therefor with incorporated means for positioning inserts, e.g. labels against the mould wall using magnetic means
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B29—WORKING OF PLASTICS; WORKING OF SUBSTANCES IN A PLASTIC STATE IN GENERAL
- B29C—SHAPING OR JOINING OF PLASTICS; SHAPING OF MATERIAL IN A PLASTIC STATE, NOT OTHERWISE PROVIDED FOR; AFTER-TREATMENT OF THE SHAPED PRODUCTS, e.g. REPAIRING
- B29C70/00—Shaping composites, i.e. plastics material comprising reinforcements, fillers or preformed parts, e.g. inserts
- B29C70/68—Shaping composites, i.e. plastics material comprising reinforcements, fillers or preformed parts, e.g. inserts by incorporating or moulding on preformed parts, e.g. inserts or layers, e.g. foam blocks
- B29C70/72—Encapsulating inserts having non-encapsulated projections, e.g. extremities or terminal portions of electrical components
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B29—WORKING OF PLASTICS; WORKING OF SUBSTANCES IN A PLASTIC STATE IN GENERAL
- B29C—SHAPING OR JOINING OF PLASTICS; SHAPING OF MATERIAL IN A PLASTIC STATE, NOT OTHERWISE PROVIDED FOR; AFTER-TREATMENT OF THE SHAPED PRODUCTS, e.g. REPAIRING
- B29C70/00—Shaping composites, i.e. plastics material comprising reinforcements, fillers or preformed parts, e.g. inserts
- B29C70/68—Shaping composites, i.e. plastics material comprising reinforcements, fillers or preformed parts, e.g. inserts by incorporating or moulding on preformed parts, e.g. inserts or layers, e.g. foam blocks
- B29C70/84—Shaping composites, i.e. plastics material comprising reinforcements, fillers or preformed parts, e.g. inserts by incorporating or moulding on preformed parts, e.g. inserts or layers, e.g. foam blocks by moulding material on preformed parts to be joined
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B29—WORKING OF PLASTICS; WORKING OF SUBSTANCES IN A PLASTIC STATE IN GENERAL
- B29L—INDEXING SCHEME ASSOCIATED WITH SUBCLASS B29C, RELATING TO PARTICULAR ARTICLES
- B29L2031/00—Other particular articles
- B29L2031/34—Electrical apparatus, e.g. sparking plugs or parts thereof
- B29L2031/3406—Components, e.g. resistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
- H01L2924/3511—Warping
Landscapes
- Engineering & Computer Science (AREA)
- Mechanical Engineering (AREA)
- General Physics & Mathematics (AREA)
- Composite Materials (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Chemical & Material Sciences (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の利用分野〕
本発明はレジンモールド半導体装置およびその製造方法
に係り、特にレジン封止部の亀裂や剥離を生じる虞れの
無いように改良したレジンモールド半導体およびその製
造方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a resin molded semiconductor device and a method for manufacturing the same, and particularly to a resin molded semiconductor device and a resin molded semiconductor device improved so that there is no risk of cracking or peeling of the resin sealing part. The present invention relates to a manufacturing method thereof.
従来のレジンモールド半導体パッケージの製作方法およ
び該方法で製作したパッケージは、金型から取υ出す際
の外力（離型力）によってペレットが割れたシ、ペレッ
トおよびリードフレームとレジンとの界面が剥離したシ
するとｂう不具合が有って、製品の信頼性、耐久性、特
に耐湿信頼性を損ねている。こうした欠点を解消するた
めに■ペレット等を封止するレジン内に離型剤を配合し
たり、■金型キャビティに離型剤を塗布する等の処置を
とっていたが、欠配のような技術的問題を残している。Conventional methods for manufacturing resin-molded semiconductor packages and packages manufactured using this method have problems such as the pellet cracking due to external force (mold release force) when removed from the mold, and the interface between the pellet and lead frame peeling off. When this happens, there are defects that impair the reliability and durability of the product, especially its moisture resistance. In order to eliminate these drawbacks, measures such as ■ blending a mold release agent into the resin that seals the pellets, etc., and ■ applying a mold release agent to the mold cavity, etc., have been taken. Technical issues remain.
（イ） 離型剤の配合量を多くすると、大きい接着力を
必要とする個所（例えばペレットやリードフレームとレ
ジンとの間）の接着力が低下して製品の信頼性、耐久性
を損ねる。(b) If the amount of mold release agent added is increased, the adhesive strength in areas that require high adhesive strength (for example, between pellets or lead frames and resin) will decrease, impairing the reliability and durability of the product.
←）金型キャビティ内に離型剤を均一に塗布することか
困難であるため、金型が汚れたシ、成形したパッケージ
の外見が不良となって商品価値を低下させたシする。←) Because it is difficult to uniformly apply the mold release agent inside the mold cavity, the mold gets dirty and the package looks bad, reducing the product value.
従来技術における不具合の情況を第１図〜第４図につい
て次に詳述する。The situation of defects in the prior art will now be described in detail with reference to FIGS. 1 to 4.
第１図はレジンモールド半導体パッケージを成形した状
態を示す。す々わち、半導体ペレット１０を搭載したリ
ードフレーム４は下型２に設置され、レジン９が注入さ
れた後加熱硬化する。FIG. 1 shows a resin molded semiconductor package in a molded state. In other words, the lead frame 4 carrying the semiconductor pellet 10 is placed on the lower mold 2, and after the resin 9 is injected, it is heated and hardened.
第２図は上記のようにして成形した製品を金型から取シ
出す操作を模式的に描いた説明図である。下型２が下方
に移動するとともに上型エジェクタプレート５が押し下
げられ、上型エジェクタビン６によってパッケージ９′
が突き出される。この瞬間にレジン９は上型１あるいは
下型２に接方しているため、接着力のアンバランスによ
りパッケージ９′は曲げモーメントを受け半導体ペレッ
ト１０は破壊することになる。そして、第３図のように
、リードフレーム４はパッケージ９′から引きぬかれる
方向の力を受ける。FIG. 2 is an explanatory diagram schematically depicting the operation of removing the product molded as described above from the mold. As the lower die 2 moves downward, the upper die ejector plate 5 is pushed down, and the package 9' is pushed down by the upper die ejector bin 6.
is thrust out. At this moment, the resin 9 is in contact with the upper mold 1 or the lower mold 2, so the package 9' receives a bending moment due to the unbalanced adhesive force, and the semiconductor pellet 10 is destroyed. Then, as shown in FIG. 3, the lead frame 4 is subjected to a force in the direction of being pulled out from the package 9'.
そして、パッケージ９′が上記のような曲げモーメント
を受ける結果として、第４図に示すように、半導体ペレ
ット１０とレジン９との間に剥離１１を生じたシ、リー
ドフレーム４のコーナ部のレジン内でクラック１２が発
生したシするという欠点があった。As a result of the package 9' being subjected to the above-mentioned bending moment, as shown in FIG. There was a drawback in that cracks 12 were generated inside.
このような状態で得られた成形品は、リードフレームの
切断、温度サイクル試駿およびはんだディップの各工程
を経て最終製品となる。しかし、上記の従来工程では、
最終製品としてのパッケージに機械的・熱的ストレスが
さらに負荷され、従来のパッケージ構造のｉｔでは界面
剥離やクラックの発生・進展が起こり易いという欠点が
あった。The molded product obtained in this state becomes a final product through the steps of cutting the lead frame, temperature cycle testing, and solder dipping. However, in the above conventional process,
Further mechanical and thermal stress is applied to the package as a final product, and IT with a conventional package structure has the drawback that interfacial peeling and cracks are likely to occur and develop.
本発明は上述の事情に鑑み、従来技術の欠点を解消すべ
く為されたもので、その目的とする所はレジンと金型キ
ャピテイとの離型力を格段に軽減させ、耐湿信頼性の高
いレジンモールド半導体装置、及び、その製造方法を提
供しまうとするものである。In view of the above-mentioned circumstances, the present invention has been made to eliminate the drawbacks of the conventional technology.The purpose of the present invention is to significantly reduce the mold release force between the resin and the mold cavity, and to achieve high moisture resistance and reliability. The present invention provides a resin molded semiconductor device and a method for manufacturing the same.
上記の目的を達成するため、本発明の半導体装置は、半
導体ペレットと、リードフレームと、封止用レジンとを
備えたレジンモールド半導体において、封止用レジンの
表層部に高剛性薄板を装着したことを特徴とする。In order to achieve the above object, the semiconductor device of the present invention is a resin molded semiconductor including a semiconductor pellet, a lead frame, and a sealing resin, in which a highly rigid thin plate is attached to the surface layer of the sealing resin. It is characterized by
寸た、本発明のレジンヤールド半導体製造方法に、半導
体をレジンで封止する工程において、上、下金型のキャ
ピテイの壁面に高剛性薄板をセットした後、ペレットを
搭載したリードフレームを上記上、下の金型の間に介装
し、そのキャビティ内にレジンを注入・充填することを
特徴とする。Specifically, in the resin yard semiconductor manufacturing method of the present invention, in the step of sealing the semiconductor with resin, after setting highly rigid thin plates on the walls of the cavities of the upper and lower molds, the lead frame carrying the pellet is placed on the upper and lower molds. It is characterized by being inserted between the lower mold and injecting and filling the cavity with resin.
次に、本発明の１実施例を第５図及び第６図について説
明する。Next, one embodiment of the present invention will be described with reference to FIGS. 5 and 6.
第す図は、本発明方法によってパンケージ９′を成形し
た状態を示す。すなわち、上型１および下型２に縦弾性
係Ｄ ’Ｅ ＝ １９０−２００ ＧＰ ａ、厚さ０１
〜０１５Ｎの高剛性薄鋼板１３１１４をセットする。こ
の作業は専用の治具（図示せず）を用いて行なう。FIG. 3 shows a pancage 9' formed by the method of the present invention. That is, upper mold 1 and lower mold 2 have longitudinal elastic modulus D'E = 190-200 GP a, thickness 01
A high-rigidity thin steel plate 13114 of ~015N is set. This work is performed using a special jig (not shown).
一方、上型１および下型２の表面近くに電磁石１５を埋
設し、当該成形装置のシーケンスに連動せしめて通電を
ＯＮ 、 ＯＦＦする。この電磁石１５は前記の高剛性
薄鋼板１３．１４をセットするときに通電を開始しであ
る。これによシ高剛性薄鋼板１５．１４はキャピテイの
底面に安定して保持される。その後、リードフレーム４
の上、に搭載した半導体ペレット１０をリードフレーム
固定ビン３で位置決めする。とのような状態で、レジン
９を型内に注入し加熱硬化させるものである。On the other hand, electromagnets 15 are embedded near the surfaces of the upper mold 1 and the lower mold 2, and are turned on and off in conjunction with the sequence of the molding apparatus. The electromagnet 15 starts to be energized when the high-rigidity thin steel plates 13 and 14 are set. As a result, the highly rigid thin steel plates 15 and 14 are stably held on the bottom surface of the cavity. After that, lead frame 4
The semiconductor pellet 10 mounted on the top of the lead frame fixing bin 3 is positioned. In this state, resin 9 is injected into the mold and cured by heating.
本実施例で用いた高剛性薄板ｉ３．１４はＦ ｅ−Ｎｉ
系材質（４２アロイ）で、その厚さは０．１＋ａ＋であ
る。The high-rigidity thin plate i3.14 used in this example is Fe-Ni
The material is 42 alloy and its thickness is 0.1+a+.
また、成形条件は、型温を１８０±５℃に保持した後レ
ジン９（エポキシ樹脂に石英ガラスを５０〜６０ｗｔ％
充填したもの）を上、下型のキャビティ内に圧力フ０鞭
包で注入する。このとき、高剛性薄鋼板１３．１４は電
磁石１５に吸着されているので、レジン９の流動によっ
て位置ずれを生じる虞れカ無い。その後、型のキャピテ
イ内のレジン９を１８Ｏｆ５℃で１５〜３分間保持させ
硬化させる。In addition, the molding conditions were as follows: The mold temperature was maintained at 180 ± 5°C, and then resin 9 (50 to 60 wt% of quartz glass was added to the epoxy resin) was used.
Filled material) is injected into the cavities of the upper and lower molds under pressure. At this time, since the high-rigidity thin steel plates 13 and 14 are attracted to the electromagnet 15, there is no risk of displacement due to the flow of the resin 9. Thereafter, the resin 9 in the mold cavity is held at 18Of5°C for 15 to 3 minutes to harden.
つぎに、第５図の状態で硬化したパッケージ９′を、先
の第２図および第３図で説明したと同じ動作工程で該パ
ッケージ９′を型キ、Ｙビティから取り出す。この作動
に際して、型開きのシーケンス開始と同時に電磁石１５
の通電を。ＦＦ Ｌ、高剛性薄鋼板１３．１４の拘束を
解くとパッケージ９′は容易に離型せしめ得る。このよ
うにして、レジン９と上型１卦よび下型１２とは接着せ
ず、非常に小さな前型カで該パッケージ９′は容易に取
り出せる。Next, the package 9' cured in the state shown in FIG. 5 is taken out from the mold die and Y bit by the same operation steps as explained in FIGS. 2 and 3 above. During this operation, at the same time as the mold opening sequence starts, the electromagnet 15
energize. When the restraints of the high rigidity thin steel plates 13 and 14 are released, the package 9' can be easily released from the mold. In this way, the resin 9 and the upper mold 1 and lower mold 12 are not adhered, and the package 9' can be easily removed using a very small front mold force.
第６図は、本発明によって得たパッケージ９′の形状を
示す。すなわち、半導体ペレッ）１０を搭載したリード
フレーム４で、該半導体ペレット１０をレジン９で封止
し、さらにレジン９の」二下両面に篩剛性薄板１３．１
４が装置され／こ複合形状のレジンモールド半導体装置
を仕ることができる。FIG. 6 shows the shape of a package 9' obtained according to the invention. That is, a lead frame 4 on which a semiconductor pellet (10) is mounted is used, the semiconductor pellet (10) is sealed with a resin (9), and a rigid thin plate (13.1) is placed on both lower surfaces of the resin (9).
4 can be used to produce composite-shaped resin molded semiconductor devices.
第７図及び第８図はそれぞれ本発明の実施例を示すパッ
ケージの形状の例である。第７図は高剛性薄板１３．１
４の一部上面にレジンで被覆した例である。第８図は該
薄板１３．１４をパッケージの傾斜部まで装置した実施
例である。FIGS. 7 and 8 each show an example of the shape of a package showing an embodiment of the present invention. Figure 7 shows high rigidity thin plate 13.1
This is an example in which a part of the upper surface of 4 is coated with resin. FIG. 8 shows an embodiment in which the thin plates 13 and 14 are installed up to the slope of the package.
第１図に示した従来の製造方法を比較例とし、第５図に
示した実施例の製造方法によってレジンモールド半導体
を製造した場合の製品品質を第１表に示す。Using the conventional manufacturing method shown in FIG. 1 as a comparative example, Table 1 shows the product quality when a resin molded semiconductor was manufactured by the manufacturing method of the embodiment shown in FIG.
以上詳述したように、本発明のレジンモールド半導体装
置は、封止用レジンの表層部に高剛性薄板を装着しであ
るので、該レジンが直接的に１１．１に接触せず、この
ため離型が容易であるため離型に起因する欠陥を生じる
虞れが無く、耐湿信頼性が大きい。As detailed above, in the resin molded semiconductor device of the present invention, since the highly rigid thin plate is attached to the surface layer of the sealing resin, the resin does not come into direct contact with 11.1. Since mold release is easy, there is no risk of defects caused by mold release, and moisture resistance is highly reliable.
また、本発明のレジンモールド半導体製造方法は、半導
体をレジンで封止する工程において、上、下金型のキャ
ピテイの壁面に高剛性薄板をセントした後、ベレットを
搭載したリードフレームを上記上、下の金型の間に介装
し、そのキャビティ内にレジンを注入・充填することに
より、前記の本発明装置を容易に高能率で製造すること
ができる。Further, in the resin mold semiconductor manufacturing method of the present invention, in the step of sealing the semiconductor with resin, after placing high-rigidity thin plates on the walls of the cavities of the upper and lower molds, a lead frame equipped with a pellet is attached to the upper and lower molds. By interposing it between the lower molds and injecting and filling the cavity with resin, the device of the present invention described above can be easily manufactured with high efficiency.
第１図はレジンモールドした半導体装置の縦断面図、第
２図および第６図は該装置を取り出す状態を示す縦断面
図、第４図は欠陥を生じた一例を示すレジンモールド半
導体装置の縦断面図である。第５図は本発明によるレジ
ンモールド半導体装置の縦断面図、第６図、第７図、第
８図は本発明で作製した一例を示すレジンモールド半導
体装置の縦断面図である。
１・・・上型 ２・・・下型
３・・・リードフレーム固定ビン
４・・・リードフレーム
５・・・上型エジェクタプレート
６・・・上型エジェクタビン
７・・・下型エジェクタプレート
８・・・下型エジェクタビン
９・・・レジン ９′・・・パッケージ１０・・・半導
体ベレット１１・・・界面剥離（ボイド）１２・・・ク
ラック １６・・・上部高剛性薄板１４・・・下部高剛
性薄板 １５・・・電磁石第 ４ 凹
Ｉｔ
第５ 図
５
第６ 図
第 ７ 図
＄ Ｂ 目
ｑ １４−FIG. 1 is a longitudinal sectional view of a resin-molded semiconductor device, FIGS. 2 and 6 are longitudinal sectional views showing the state in which the device is taken out, and FIG. 4 is a longitudinal sectional view of a resin-molded semiconductor device showing an example of a defect. It is a front view. FIG. 5 is a longitudinal cross-sectional view of a resin molded semiconductor device according to the present invention, and FIGS. 6, 7, and 8 are longitudinal cross-sectional views of resin molded semiconductor devices showing an example of the resin molded semiconductor device manufactured according to the present invention. 1... Upper die 2... Lower die 3... Lead frame fixing bin 4... Lead frame 5... Upper die ejector plate 6... Upper die ejector bin 7... Lower die ejector plate 8...Lower ejector bin 9...Resin 9'...Package 10...Semiconductor pellet 11...Interfacial peeling (void) 12...Crack 16...Upper high rigidity thin plate 14...・Lower high-rigidity thin plate 15... Electromagnet No. 4 Concave It No. 5 Fig. 5 Fig. 6 Fig. 7 Fig. $ B q 14-
Claims (1)
ジンとを備えたレジンモールド半導体において、封止用
レジンの表層部に高剛性薄板を装着したことを特徴とす
るレジンモールド半導体装置。 ２、 半導体をレジンで封止する工程にかいて、上、下
金型のキャビティの壁面に高剛性薄板をセットした後、
ペレットを搭載したリードフレームを上記上、下の金型
の間に介装し、そのキャビティ内にレジンを注入・充填
することを特徴とするレジンモールド半導体の製造方法
。[Claims] 1. A resin molded semiconductor comprising a semiconductor pellet, a lead frame, and a sealing resin, characterized in that a highly rigid thin plate is attached to the surface layer of the sealing resin. Semiconductor equipment. 2. In the process of sealing the semiconductor with resin, after setting high-rigidity thin plates on the walls of the upper and lower mold cavities,
A method for manufacturing a resin molded semiconductor, which comprises interposing a lead frame loaded with pellets between the upper and lower molds, and injecting and filling the cavity with resin.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58160387A JPS6053059A (en) | 1983-09-02 | 1983-09-02 | Resin molded semiconductor device and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58160387A JPS6053059A (en) | 1983-09-02 | 1983-09-02 | Resin molded semiconductor device and manufacture thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6053059A true JPS6053059A (en) | 1985-03-26 |
| JPH0117260B2 JPH0117260B2 (en) | 1989-03-29 |
Family
ID=15713858
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58160387A Granted JPS6053059A (en) | 1983-09-02 | 1983-09-02 | Resin molded semiconductor device and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6053059A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5179039A (en) * | 1988-02-05 | 1993-01-12 | Citizen Watch Co., Ltd. | Method of making a resin encapsulated pin grid array with integral heatsink |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2011216253A (en) | 2010-03-31 | 2011-10-27 | Yazaki Corp | Crimp terminal and wire connection structure of crimp terminal |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS559420A (en) * | 1978-07-07 | 1980-01-23 | Hitachi Ltd | Resin shielding type semiconductor device |
| JPS57196547A (en) * | 1981-05-28 | 1982-12-02 | Nec Corp | Semiconductor device |
-
1983
- 1983-09-02 JP JP58160387A patent/JPS6053059A/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS559420A (en) * | 1978-07-07 | 1980-01-23 | Hitachi Ltd | Resin shielding type semiconductor device |
| JPS57196547A (en) * | 1981-05-28 | 1982-12-02 | Nec Corp | Semiconductor device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5179039A (en) * | 1988-02-05 | 1993-01-12 | Citizen Watch Co., Ltd. | Method of making a resin encapsulated pin grid array with integral heatsink |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0117260B2 (en) | 1989-03-29 |
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