JPS6052474B2 - Digital signal correction method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a digital signal correction method for correcting missing information when converting an image signal obtained by a scanning device such as a facsimile or an optical character reading device into a digital signal.

In scanning devices such as facsimiles and optical character readers, depending on the information distribution of the document, even if the information has the same linear density, the photoelectric conversion output may be different from the OTE (OPTIC) of the optical system.
It usually differs depending on the sensitivity of the photoelectric conversion device, etc. For example, in the image signal A obtained by scanning the original 0 along the scanning line 1, as shown in Figure 2, there is a phenomenon in which the white level of areas with dense information is lower than the black level of areas with sparse information. occurs. Conventionally, a method is known in which an image signal obtained by a scanning device is compared with a reference voltage using a comparator and converted into a binary value, and the reference voltage is divided while maintaining the white level of the image signal.

In such a method of binarizing image signals, even if the reference voltage follows the white information of the original, depending on the value of the partial voltage value, either the white information or the black information may be lost due to the above-mentioned phenomenon. As a result, phenomena such as so-called black spots and white spots occur. Therefore, a method of correcting the white spot phenomenon in information-dense areas by maintaining the peak values of the white level and black level, as in the Japanese Patent Publication No. 48-14129,
Although methods have been proposed that detect spaces and marks and generate optimal binarization patterns using three levels of reference voltages, as in the case of 9-3320 Sae, these methods require the use of complex circuits. In view of these points, it is an object of the present invention to provide a digital signal correction method capable of compensating for missing status information when an image signal is binarized using a simple circuit.

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows the circuit used in this example, and FIGS. 2 and 3 show its timing chart.

Image signals obtained by scanning a document 0 in the scanning device and photoelectrically converting the image are amplified by a non-inverting amplifier 1 and an inverting amplifier 2, respectively. Here, the highest information density Uc of the image signal is the desired readable upper limit linear density (11ne1
For example, in a scanning device using a self-scanning solid-state image pickup device such as a charge-coupled device or a photodiode array, it corresponds to one bit of the photo element. The white level holding circuit 3 receives the image signal A from the non-inverting amplifier 1.
The peak value of the white level is held, and the peak value is divided by two constant ratios by the voltage dividing circuit 4 and provided to the comparator 596 as a reference voltage VRef19VRef2. The image signal A from the non-inverting amplifier 1 is converted to a reference voltage VRef. which follows the white level peak value in the comparator 6. It is compared with , and is binarized to become a digital signal. The reference voltage VRCr2 is set to the optimum value for binarizing the image signal by the voltage dividing circuit 4, and the digital signal from the comparator 6 is compensated for information loss by the information loss correction circuit 7. That is, the image signal from the non-inverting amplifier 1 is compared with the reference voltage VRefl that follows the white level peak value in the comparator 5, and is binarized, and the reference voltage V
Refl is higher than the reference voltage VRef2 by the voltage dividing circuit 4, that is, as shown in FIG. 2, it is closer to the white level than the reference voltage Rerl. Set to an appropriate value. delay circuit 8
10 performs a delay operation by applying a clock pulse, and the delay delay line 8 delays the output signal C1 of the coparator 5 by 1 bit, and the delay circuit 9 delays the output signal C of the delay circuit 8 by 1 bit. Signal C2 is obtained. Further, the black level holding circuit 11 holds the peak value of the black level of the image signal from the inverting amplifier 2, and the peak value is divided by the voltage dividing circuit 12 and applied to the comparator 13 as a reference voltage VRef3. The comparator 13 compares the image signal from the inverting amplifier 2 with the reference voltage VRef3 and performs binarization.
In this case, the comparator 13 binarizes the image signal inverted by the inverting amplifier 2 using the reference voltage VRe, which is higher than the reference voltage VRe of the comparator 6, but the comparator 6 Reference voltage Ref
Reference voltage VRef3 lower than 2 (closer to the black level side)
It is also possible to convert it into a value and invert it. In other words, the image signal is the reference voltage VRe of comparator 6, a reference voltage VR higher than 2.
efl, comparator 5,1 with low reference voltage VRef3
It will be binarized by 3. Delay circuits 14, 15
A clock pulse is applied to perform a delay operation, and the delay circuit 14 delays the output signal E1 of the comparator 13 by one bit, and the delay circuit 15 delays the output signal E of the delay circuit 14 by one bit to obtain the signal E2. ing. By the way, in areas where image signal information is dense, the signals before and after white information with a line density close to the desired line density Uc are often at a lower level than the white information; conversely, in areas where information is sparse, Since the signals before and after the black information are often at a higher level than the black information, comparator 5 is used to determine the white information and black information as white and black, respectively.
, 13, high-density white information and black information can be determined based on the signals that are one bit ahead or behind the digital signals from the digital signals. This judgment condition is expressed as a logical expression. ! ．． Outside? Yohikimi naru. Based on this logical formula (1), the output signal C of the delay circuit 14 is inverted by the inverter 16, and the inverted signal n, the output signal E1 of the comparator 13, and the output signal E2 of the delay circuit 15 are
White information is obtained by the AND circuit 17, and black information is placed around 1 bit of white information in areas where information is dense)G
is taken out.

Further, the output signal C1 of the comparator 5 and the output signal C2 of the delay circuit 9 are NANDed by a NAND circuit 18, and the output signal and the output signal of the delay circuit 8 are ORed by an OR circuit 19, so that the information is sparse. The black information (black information in which the area around 1 bit is white information) F is extracted. The delay circuit 10 converts the digital signal from the comparator 6 into a signal F.
, G is delayed by 1 bit. The digital signal D from the delay circuit 10 is ANDed with black information F in an AND circuit 21 to compensate for black spots, that is, missing information such as thin lines, and further ORed with white information G in an OR circuit 22. White spots are compensated for, resulting in a digital signal H with compensated information omissions. Note that in the above embodiment, the reference voltages VRefl and VRef3 are made to follow the white level, and the reference voltage VRef3 is made to follow the black level, but the present invention is not limited to this, and the reference voltages VRefl to VRef3 are made to follow the white level. Alternatively, it may be made to follow either the black level.

For example, as shown in FIG. 4, the reference voltage R. fl~VRem
You can also make it follow the white level. In this case, the voltage dividing circuit 12 converts the output of the white level holding circuit 3 into the reference voltage Re,
The comparator 13 divides the output signal of the non-inverting amplifier 1 into a reference voltage Re,3'' lower than
3″ and performs binarization. Then, comparator 13
The NOR circuit 23 takes the NOR between the output signal E″1 of the output signal E″1 and the output signal E″2 of the delay circuit 15, and the AND circuit 24 takes the AND between the output signal and the output signal E″ of the delay circuit 14. White information G is extracted, that is, NOR circuit 23
A logical operation is performed by the AND circuit 24, and the white information G of the area where the information is concentrated is extracted.

As described above, according to the digital signal correction method of the present invention, the image signal from the scanning device is binarized using the first reference voltage that follows the white level or black level of the image signal to obtain the first binarized signal. , a second reference voltage that follows the white level or black level of the image signal on the white level side of the first reference voltage;
The image signal is binarized using a reference voltage of 2 to obtain a second binarized signal, and this second binarized signal is delayed by 1 bit in a first delay circuit, and further in a second delay circuit. Delay by 1 bit, and determine that the output signal of the first delay circuit is white information, and the second binary signal delayed by 1 bit and the output signal of the second delay circuit are black information. By doing so, the white information in the information-dense area is determined, and the image signal is 2. digitize to obtain a third binarized signal, and convert this third binarized signal into a third binarized signal.
The output signal of the third delay circuit is delayed by one bit in the delay circuit, and further delayed by one bit in the fourth delay circuit, and the output signal of the third delay circuit is the black information, and the third binary signal is delayed by one bit before and after the black information. By determining that the output signal of the fourth delay circuit is white information, the black information of the sparse portion of the status information is determined, and this black information and the white information of the information dense portion are transferred to the first delay circuit. Since the information loss is compensated for in addition to the binarized signal, it is possible to compensate for the information loss when the image signal is binarized, and it can be implemented using an extremely simple circuit.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a circuit used in one embodiment of the present invention, FIGS. 2 and 3 are timing charts of the same embodiment, and FIG. 4 is a circuit diagram showing a circuit used in another embodiment of the present invention. FIG. 1... Non-inverting amplifier, 2... Inverting amplifier, 3... White level holding circuit, 4... Voltage dividing circuit, 5... Comparator, 8, 9...
...Delay circuit, 11...Black level holding circuit, 1
2... Voltage divider circuit, 13... Comparator J, 14, 15... Delay circuit, 16...
Inverter, 17...AND circuit, 18...
...NOR circuit, 19...OR circuit, 21...
...AND circuit, 22...OR circuit, 23...
...NOR circuit, 24...AND circuit.

Claims (1)

[Claims] 1. In a method of obtaining a first binary signal by binarizing an image signal from a scanning device using a first reference voltage that follows its white level or black level, The image signal is binarized using a second reference voltage that follows the white level or black level of the image signal to obtain a second binarized signal, and this second binarized signal is sent to the first delay circuit. The output signal of the first delay circuit is white information and is delayed by one bit in the second delay circuit.
Determining white information in an information-dense portion by determining that the second binary signal whose bits are different and the output signal of the second delay circuit are black information; and The image signal is binarized using a third reference voltage that follows the white level or black level of the image signal on the black level side of the voltage to obtain a third binarized signal, and this third binarized signal is delayed by 1 bit in the third delay circuit, and further delayed by 1 bit in the fourth delay circuit, and the output signal of the third delay circuit is the black information, which is the third binary value that is around 1 bit before and after the black information. By determining that the output signal of the fourth delay circuit and the output signal of the fourth delay circuit are white information, the black information of the sparse information portion is determined, and this black information and the white information of the information dense portion are A digital signal correction method characterized by compensating for information omissions in addition to the first binary signal.