JPS6052463B2 - Common bus protection method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a common bus protection method for processing equipment using a common bus, and in particular, when a device connected to the common bus fails, the failed equipment is automatically protected from the common bus. This invention relates to a common bus protection system that is separated from the bus.

A data processing device has a central processing unit and various input/output devices, and performs various data processing.

However, as devices become larger and more complex, the number of input/output devices increases, and the interface between the central processing unit and the input/output devices, especially the increase in the number of wires from a hardware perspective, has become a major problem. . Furthermore, there are now many ways to use not just one central processing unit, but multiple central processing units in a multiprocessing format. Furthermore, there are also cases where the former and the latter are used in combination. Even in such a case, problems arise such as an increase in the number of wires between central processing units and an increase in the number of wires between the central processing unit and input/output devices. A common bus system has been proposed to reduce the number of wires in the various cases described above. This system uses a high-speed signal transmission line as a bus and sends signals in and out from multiple points on the bus, and the transmission line and the devices connected to it are connected via respective control circuits. The case where this common bus method is used as an interface for input/output devices will be described below.

The common bus system can be roughly divided into a complete common bus system shown in FIG. 1 and a relay common bus system shown in FIG. 2. The complete common bus system shown in FIG. 1 has a common bus 1, a bus control device 2 that manages the common bus 1, and an input/output device control device 3a that controls a plurality of input/output devices 4 and the common bus 1. The connection is made through the

As is clear from the figure, the input/output control device 3a and the input/output device 4 do not necessarily have a one-to-one correspondence. Second
In the relay common bus system shown in the figure, the common bus 1 uses the input/output device control device 3b as a relay point.

In this system, the input/output device control device 3b must have the function of relaying the bus 1, as a matter of course. The busbar system shown in Figure 1 does not include repeaters or logic circuits in the transmission path like the relay system, so it has the characteristic of inherently high system reliability. Compared to the busbar system, the complete common bus system shown in Figure 1 is more often adopted.

Various coupling methods have been considered for this bus method, but in the case of a TTL level such as inside an electronic computer, a circuit as shown in FIG. 3 is used. Figure 3 shows one of the busbars selected for transmission from the input/output device out of a plurality of busbars, and each input/output device 4
is determined by the transmission gate 6 in the input/output device control device 3a,
A signal is placed on the common bus 1, and the signal is transferred to the bus control device 2.
This shows a bus system in which reception is performed by the five receiving gates 5. Here, when no transmitting gate is emitting a signal, the potential of the common transmission line 1 becomes a positive potential obtained by subtracting the voltage drop caused by the resistor 7 from +Vcc due to the positive potential 10 Vcc power supply in the receiving gate 5. There are four. Hereinafter, this state will be referred to as the "HIGH" state. If any one of the transmission gates is 0N, the potential of the common transmission line 1 will be close to the GD voltage (hereinafter, this state will be referred to as the "LOW" state). It's starting to become. As a result, the bus control device 2 senses this LOW state through the reception gate 5 and receives the signal. However, in the case of the commonly used common bus system, (1) Since multiple input/output devices are connected to one bus, it is difficult to control any one input/output device or its control. Even if the bus line is erroneously brought to the LOW state due to a failure or malfunction of the unit, there is no means to determine which input/output device or control unit is the cause.

(2) If the bus stays in the LOW state due to the previous item (1), data transmission using this bus is impossible unless it recovers, and if the signal on this bus
If it is a control signal that manages input/output devices, a major drawback is that a malfunction in one bus bar will stop input/output processing for all input/output devices connected to the bus bar, causing the entire data transmission system to go down. There is.

When data transmission becomes impossible as described above, conventionally the I/O devices were disconnected one by one from the common bus and the status of the bus was sequentially checked to find the failure location. It took a lot of time to complete the process, and there was a lot of system downtime. This problem similarly occurs in common bus systems other than the common bus system for input/output devices. Although system down time must be kept as short as possible, there is no prior art that has solved the above problems. The present invention solves the above-mentioned drawbacks and provides a common bus protection system that uses a simple mechanism to immediately disconnect devices such as failed input/output devices upon failure.

The gist of the present invention is to apply a specific current or voltage to the failed location when a failure occurs, and to automatically disconnect the failed input/output device connected to the common bus using the current or voltage. It is something.

Hereinafter, the present invention will be explained in detail with reference to the drawings. FIG. 4 is a diagram showing an embodiment of the present invention.

This embodiment is applied when a failure occurs in the transmission gate. In the figure, the newly provided parts are a current fusing element 11 connected in series to the output of the transmission gate 6 and a transmission gate cutting circuit 15. The current fusing element 11 is an element that is instantaneously fused by a specific current when it flows. The specific current referred to here means that even if the specific current flows into various semiconductors and electrical elements (resistors, etc.) connected to the common bus 1 and working normally, it will not destroy them and will not cause the current to melt. This term is used to mean that only the element 11 itself is cut. However, under these conditions, as is clear from the figure, when looking at the configuration in which a current fusing element 11 is provided on the output side for each transmission gate, it is impossible to distinguish between a failed transmission gate and a non-faulty transmission gate. As a result, even transmitting gates that do not fail must be separated from the common bus. This problem can be solved by paying attention to the internal structure of the transmission gate and how data is handled in the overall system. I will discuss this below. The transmission gate 6 - consists of, for example, a transistor.

Among the failures of the transmission gate 6, failures of transistors, which are gate elements, account for a large proportion of failures. There are two types of transistor failures; one is that the transistor becomes completely conductive, and the other is that it becomes completely non-conductive. Generally, a circuit is designed such that a transistor is non-conductive when there is no input signal and becomes conductive only when an input signal is input. This is done to reduce power consumption. Therefore, the former failure mode means that the output signal continues to be generated despite the failure, and the latter failure mode means that the output signal does not always occur. Considering the effects of these two failure modes on the system, the latter means that the transmission gate is effectively disconnected, and has little negative impact on the entire system. On the other hand, in the former case, since the output signal continues to be generated, the signal is applied to the control device 2 through the common bus 1, which causes an obvious malfunction. Therefore, among the failure modes of the transmission gate, the former case is the one to be most careful of. This embodiment is applied to the former case. That is, in a transmission gate that has failed to become fully conductive, when viewed from the fusing element, the transmission gate has low impedance (effectively grounded). Therefore, for this transmission gate, the fusing element 1
As a result, the fusing element 11 itself is fused by the current. For a normal transmission gate, when the transmission gate is viewed from the fusing element 11, it is in a high impedance state, so no current flows through the fusing element 11 itself, and therefore the fusing element 11 itself is not fused. The fusing element 1 also has high impedance for the transmission gate in the latter failure mode.
1 is not fused. The current fusing element 11 may be one that automatically blows out with a relatively small amount of current, and therefore is suitable for small capacity fuses such as electronic circuit fuses rather than large capacity fuses such as power fuses. Hughes is suitable.

Furthermore, when the input/output device control device 3a itself is integrated, a portion that automatically blows out when a specific current flows to the output side of the transmission gate is provided on the integrated circuit, and this portion is used as a current blowing element. It is also possible to use it as Furthermore, the above-mentioned instantaneous blowout means a blowout within a time range in which the transmission gate fails and the failure does not affect the management of the entire system.

This is also the time before the system goes down.
The transmission gate disconnection circuit 15 includes a detection circuit 20 for detecting a failure appearing on the common bus 1, and a power supply 14 for transmitting gate fusing.
, a switch 20 that is turned on when a failure is detected in the detection circuit 20, and a backflow blocking diode 13. The detection circuit 20 may perform failure detection all the time, but as described above, since it detects a state in which the transmission gate 6 is always conductive in the failure mode, it cannot detect the failure under the control of the control device 2. It is best to perform failure detection.
In this case, the control device 2 has two modes: an interval for data transmission through the common bus 1 and an interval for detecting a failure mode, and the detection circuit is activated in the failure mode detection interval. 20 operations may be started. However, the above two sections may be regularized or may have a random relationship. According to the above configuration, if any of the transmitting gates 6 causes a failure such that it becomes constantly conductive for some reason, the failure causes the detection circuit 2 to
As a result, the switch 12 closes, and the power supply 1 is connected to the common bus 1 through the switch 12 and the diode 13.
Current flows from 4.

As a result, current flows into the current fusing element 11 connected to the output side of the failed transmission gate 6, causing the element 11 to melt. This causes the failed transmission gate 6 to be disconnected from the common bus 1. Although the above configuration is an example of disconnecting a faulty gate from one common bus 1, there are actually a plurality of common buses.

That is, it is composed of data lines and control lines. Furthermore, since the single data line itself transmits data in parallel, a data line corresponding to the data length is required. There is not just one control line, but the number of control lines, such as transmission commands, reception commands, and answer backs, depends on the scale of the system. For example, if the data length is 16 bits and the address is 16 bits, one wire is required for data transmission and 16 wires are required for address transmission. In addition, the various control lines mentioned above are added, and the total number of common bus lines is 40X. ~50X. reach. In these cases,
If all the common buses are configured as in the above embodiment, automatic disconnection will be possible in the event of a failure in all transmission gates. Of course, some of these common buses are not coupled through transmission gates. In such a case, a similar configuration may be adopted for the gate corresponding to the output stage. Furthermore, among the common buses, there are some that do not lead to system failure. For example, part of the control line corresponds to this. In such a case, it is sufficient to remove them so that they can be separated. Note that instead of providing a transmission gate disconnection circuit for each transmission gate, one transmission gate disconnection circuit may be provided to take in signals from all common bus lines in parallel. In this case, the number of circuit points can be significantly reduced. Next, another embodiment of the present invention will be described.

The above-mentioned example was an example of disconnecting the input/output device and the control device from the bus bar due to the detection of a failure in the transmission gate 6, but it is also possible to disconnect the entire input side of the transmission gate or a part of the input side. As a practical matter, this also accounts for a large proportion of failures.
Here is an example that deals with such cases. It is shown in FIG. Fifth
The structural feature of the embodiment shown in the figure is that it attempts to detect a failure on the input side of the transmitting gate, including the transmitting gate.

In order for a transmission gate to detect a failure on its input side, the transmission gate must be in a state where it can detect the failure. The optimal and efficient way to achieve this state is to send a reset signal to the common bus to force the various input/output devices and input/output device control devices connected to the common bus to enter the reset state. That's true. Fortunately, in the common bus system, a forced set section is provided for timing purposes. This forced set section is designed to occur for periodic inspection of failures or when an abnormality in data transmission is detected. In the former case, the central processing unit (CP) selects a point in time when the common bus is not in use and forcibly applies the set, so it is not a periodic inspection in the full sense of the word. The latter is a forced set that occurs when an abnormality in data transmission is detected by the bus control device 2 that controls the common bus. In either case, it is performed through a dedicated reset line. Let us explain the configuration and operation of FIG. 5 based on the preconditions.

The transmission gate disconnection circuit 15 includes a switch 22 and a delay circuit 2.
3, Noah Gate 24, Inverter 25, Noah Gate 26
, transistor 27, ″28, reverse current blocking diode 1
Consists of 3. The Noah gate 24 has two common bus lines 1a,
The signal on 1b is input. Delay circuit 2
The delay time No. 3 is set to the delay time from when the resetting signal is sent to the input/output device and the control device until the internal circuits of those devices complete resetting. The signal line is a signal line exclusively used for resetting. As described above, the signal lines 1a and 1b indicate two signal lines among the plurality of common bus lines.

Therefore, in reality, signals from two or more signal lines are input to the NOR gate 24, and in order to simplify the drawing, two or more signals are input to the NOR gate 24.
The meaning is simply represented by the examples in the book. Further, the logic is negative logic on the common bus and positive logic on the input side of the transmission gate. Therefore, the reset signal itself is also at negative logic. However, this logic is based on the relationship with the gate configuration, and there may be various forms in practice. Now, when the forced reset is applied, the switch 22 is closed, and the reset signal is sent to the delay circuit 23 and the reset signal line 21 through the switch 22.

The reset signal is sent to the controller 3 on the reset signal line 21.
a and an input/output device 4 (not shown) via this device.
is sent to force a set on the internal circuitry within the device. After a delay time in response to this forced set, the internal circuit completely enters the forced set state. The result of this forced reset appears at the output of the transmitting gates 6a, 6b.

If various internal circuits are out of order, the input signal of the transmitting gate 6a or 6b becomes "1", and as a result, the output of the corresponding transmitting gate becomes "0", that is, a low level state. Since it is a negative logic, a signal of ゜゜1゛ will appear at the output. This clearly means that a failure has occurred. The above process was an example of a failure in the internal circuit other than the transmission gate. , the transmission gate itself is broken,
In particular, even in the case of a failure mode of constant conduction (the same as in the embodiment shown in FIG. 4), negative logic ゛゜1゛ appears at the output of the transmission gate. In any of these cases, the failure result can be detected by the NOR gate 24 and becomes an input signal to the NOR gate 26 via the inverter 25. On the other hand, after the delay time, a reset signal appears at the output of the delay circuit 23 and is applied to the input of the NOR gate 26. As a result, the NOR gate 26 is turned on, the transistors 27 and 28 are turned on, and current flows through the diode 13 to the common bus lines 1a and 1b, and flows into the fusing elements 11a and 11b. As a result, only the fusing element connected to the transmission gate outputting ゛゜1゛ is blown out, and the transmission gate is separated from the common bus. According to the embodiments described above, since the faulty part is isolated by using the forced setting time when an abnormality is detected, it is possible to completely eliminate any negative influence on the system.

Incidentally, the timing to apply the forced set is not necessarily limited to only when an abnormality occurs, but can also be performed during periodic inspection. At this time, the faulty part can be isolated regardless of system abnormality. Next, a case will be described in which a fuse resistance element is used as an example of a current fusing element. This fuse resistance element is not a power fuse resistance element as described above, but an electronic circuit fuse resistance element. The characteristics of this resistance element are shown in FIG. The horizontal axis shows applied power P, and the vertical axis shows fusing time T. The shaded area in the figure shows the fusing characteristics. As is clear from this shaded area, when low power is applied (approximately 4P0 or less), the fusing time also increases linearly, and when the power is above calm power, the fusing time remains almost constant.
Assume that a fuse resistance element with a resistance value of 10Ω and a rated power of 0.1W is used. Furthermore, a standard TTL gate is used as the transmission gate, the termination resistor 7 of the control device 2 is 300Ω, and the power supply voltage Vcc is +5.
Assume that V is used. The circuit configuration at this time is shown in Figure 7, A and A. The diagram A shows how the current flows into the transmission gate 6 during normal times, and the diagram at the front shows how the current flows into the transmission gate 6 during abnormal times. In both cases, it is assumed that the transmission gate 6 is in the ON state, that is, the output level is in the LOW state (negative logic "1"). 11 becomes.

This current 11 is actually less than 16 wL,A since the conduction resistance of the transmission gate 6 when it is on is ignored.
On the other hand, as shown in the diagram, if the power supply voltage when the switch 12 is on is +5V, the current 12 flowing into the transmission gate 6 at this time is assumed to be.

However, since the resistance in the on state of the diode 13 and the transmission gate 6 is ignored, the actual value is 0.1 A or less. B. Power consumption Pl, P of fuse resistor 11 in the diagram
2 becomes.

Therefore, if you choose a fuse resistance element that gives 4P0 x 2.5 (W) among the fuse resistance elements shown in Fig. 6,
The fuse resistance element is blown out at time TO.

This time T. Some are measured in seconds, while others are measured in seconds. In this practical example, the latter is optimal, but the former can also be used. FIG. 8 shows an embodiment in which a fusing element is formed in a part of the transmission gate using an integrated technology. All transmission gates 6 are integrated, 32 is a multi-emitter type transistor, 33 is its base resistance, 3-5,
37 is a transistor, and 34 and 36 are resistors. Element 3
Reference numeral 1 denotes a fusing element, such as a bonding wire or a PN junction. This element 31 can be disconnected by overcurrent. In addition, although the various embodiments described above utilize fusing by electric current, a voltage application type may also be used. For example, read-only memory (R
When storing data in the OM), an element (conductor wire) that is cut by voltage application is used. Even with this technique, it is possible to isolate the failed part. Note that the devices connected to the common bus line are not limited to input/output devices, but may also be central processing units or the like.

Further, although the transmission gate is used as a connection part, other circuits may be used, and this is not limited. According to the common bus protection system according to the present invention, the following effects were achieved.

(1) Since the configuration is simple, maintainability of the common bus can be economically improved.

(2) By cleverly utilizing the fact that current only flows through the faulty location, abnormality location detection and isolation can be performed at the same time, and maintainability is greatly improved compared to conventional technology.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of a complete common bus system, Fig. 2 is a block diagram of a relay common bus system, Fig. 3 is a specific example of a complete common bus system, Fig. 4 is an embodiment of the present invention, and Fig. 5 is a block diagram of a complete common bus system. The figure shows another embodiment of the present invention, Figure 6 is a characteristic diagram of a fuse resistor element, Figure 7 shows a current comparison diagram when using a fuse resistor element, and Figure 8 shows a current flowing through a part of the transmission gate. It is a diagram showing an example of a configuration in which a fusing element is added. 1, 1a, 1b... Common bus line, 2... Bus control device, 3, 3a... Input/output device control device, 4... Input/output device, 6 ......Transmission gate, 11, 11a, 11b...Current fusing element, 1
5...Transmission gate disconnection circuit.

Claims (1)

[Scope of Claims] 1. A digital device comprising a plurality of digital devices and one or more common busbars, wherein each of the devices is selectively connected to the one or more common busbars through a connecting portion of each device. so that the connected devices, each selected and connected, have the said one or more common busbars exclusively, and the connections of each of the devices are specified in case of failure of its own device or connection. A disconnection section is provided that disconnects with a current or voltage of A common bus protection system that automatically disconnects devices or connecting parts from the common bus by cutting the disconnecting part of the connection. 2. A device comprising a plurality of digital devices and one or more common busses, each of the devices being selectively connected to the one or more common busses through a connecting portion of each device, and each of the devices being selectively connected to the one or more common busses, The devices connected to each other use the one or more common busbars exclusively, and the connections of each of the devices are provided with a specified current or voltage in the event of a failure of its own device or connection. When a failure is detected or checked in a device or connection part, each digital device is forcibly reset by a reset signal, and the content of the signal that appears on the common bus line at the time of reset is provided. Perform fault detection according to
Upon this fault detection, the specific current or voltage is applied to the common bus, and the faulty device or connection is automatically disconnected from the common bus by cutting the disconnection part of the connection. Busbar protection method.