JPS6052027A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS6052027A JPS6052027A JP15981283A JP15981283A JPS6052027A JP S6052027 A JPS6052027 A JP S6052027A JP 15981283 A JP15981283 A JP 15981283A JP 15981283 A JP15981283 A JP 15981283A JP S6052027 A JPS6052027 A JP S6052027A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor
- insulator
- superlattice
- film
- lattice constant
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 46
- 239000012212 insulator Substances 0.000 claims abstract description 26
- 230000001747 exhibiting effect Effects 0.000 claims 1
- 239000010408 film Substances 0.000 abstract description 26
- 239000000758 substrate Substances 0.000 abstract description 17
- 229910001218 Gallium arsenide Inorganic materials 0.000 abstract description 8
- 239000010409 thin film Substances 0.000 abstract description 5
- 238000000034 method Methods 0.000 abstract description 3
- 229910001632 barium fluoride Inorganic materials 0.000 abstract description 2
- WUKWITHWXAAZEY-UHFFFAOYSA-L calcium difluoride Chemical compound [F-].[F-].[Ca+2] WUKWITHWXAAZEY-UHFFFAOYSA-L 0.000 abstract description 2
- 229910001634 calcium fluoride Inorganic materials 0.000 abstract description 2
- 238000010030 laminating Methods 0.000 abstract 2
- 239000000126 substance Substances 0.000 abstract 2
- 239000013078 crystal Substances 0.000 description 6
- 239000002184 metal Substances 0.000 description 5
- 229910052751 metal Inorganic materials 0.000 description 5
- 150000001875 compounds Chemical class 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 238000001451 molecular beam epitaxy Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 229910052596 spinel Inorganic materials 0.000 description 2
- 239000011029 spinel Substances 0.000 description 2
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- -1 e InP Chemical class 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 230000006641 stabilisation Effects 0.000 description 1
- 238000011105 stabilization Methods 0.000 description 1
- 238000007738 vacuum evaporation Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Formation Of Insulating Films (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は界面準位の少ない良好な特性を示す半導体装置
に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device that exhibits good characteristics with few interface states.
半導体表面への絶縁膜形成技術は、絶縁ゲート屋電界効
果トランジスタ（ＭＩ ８ＦｌａＴ ）や、半導体装置
の表面安定化にとってきわめて重要であり、半導体自体
の酸化膜を形成する方法（熱酸化法、陽極酸化法、プラ
ズマ酸化法）や被着法によって絶縁膜を形成する方法（
化学気相成長法、スパッタリング法などＫよる酸化ケイ
素膜、窒化ケイ素Ｍ、酸化アルクニウム膜の形成）が試
みられてきた。これらの中で低界面単位密度が得られて
いる良好なＭＩａ系はシリコン（ｓｌ）の熱酸化によっ
て形成された二酸化ケイ素（８ｉ０２）−シリコン系の
みであった。とくにＩ−Ｖ化合物半導体では、材料のも
つ不安定性のため、良好なＭＩＳ特性祉得られるに至り
ていない。The technology for forming an insulating film on the surface of a semiconductor is extremely important for the surface stabilization of insulated gate field effect transistors (MI8FlaT) and semiconductor devices. method, plasma oxidation method) or deposition method (
Attempts have been made to form silicon oxide films using K, silicon nitride M, and alkium oxide films, such as chemical vapor deposition and sputtering methods. Among these, the only good MIa system with a low interfacial unit density was the silicon dioxide (8i02)-silicon system formed by thermal oxidation of silicon (sl). In particular, IV compound semiconductors have not been able to provide good MIS characteristics due to the instability of the material.
上記の従来の方法で形成される絶縁膜は非晶質のもので
あり走が、最近、これを単結晶化し、しかも基板となる
半導体と格子整合のとれた絶縁膜を半導体表面上に被着
する仁とが試みられている。The insulating film formed by the conventional method described above is amorphous, but recently it has been made into a single crystal, and an insulating film that is lattice-matched to the semiconductor that serves as the substrate is deposited on the semiconductor surface. An attempt is being made to do this.
仁のような単結晶の絶縁膜を用い次場合には、半導体と
絶縁膜の格子整合を正確にとらなければ、低界面密度が
得られない。このため、これらの試みは未だ成功してい
ない。When using a single-crystal insulating film such as nickel, a low interfacial density cannot be obtained unless the lattice matching between the semiconductor and the insulating film is accurately achieved. For this reason, these attempts have not yet been successful.
本発明は、単結晶絶縁膜のかゎりに超格子絶縁膜を用い
ることにより、従来存在した単結晶絶縁膜と半導体間の
格子不整合にもとすく歪みを超格子内に吸収させ、ＭＩ
８構造に限らず一般に半導体上に絶縁体が形成された半
導体装置において良好な低界面密度の構造を得ようとす
るものである。By using a superlattice insulating film in place of a single crystal insulating film, the present invention can easily absorb strain in the superlattice due to the lattice mismatch between the conventional single crystal insulating film and the semiconductor, and the MI
The purpose of this invention is to obtain a structure with a good low interface density not only in the 8 structure but also in general in a semiconductor device in which an insulator is formed on a semiconductor.
以下、本発明の実施例を図面にもとづいて説明する。Embodiments of the present invention will be described below based on the drawings.
第１図は本発明の第１の実施例であるＭＩＳ装置の断面
を示す。半導体基板１の表面に第１の絶縁体２と第２の
絶縁体３が交互に積層された構造をもつ超格子絶縁膜４
が被着され、さらにその上に金属薄膜５が被着されてい
る。ここで半導体基板１としては例えばｐ型ＧａＡｓを
用いた場合には第１の絶縁層はＣａｒｔを、第２の絶縁
層としてはＢａＦ２を選びそれぞれ１５Ａおよび６Ａづ
つ分子線エピタキシ法で全体の厚さが２１０ＯＡになる
まで交互に被着する。金属薄膜５としてはＡＩを厚さ３
０００ Ａだけ真空蒸着法で被着した。このＭＩＳ装置
の界面密度はＩ Ｘ １０’ ” ｃｍ−”ときわめて
低い値が得られた。半導体基板１としてｐ型ＩｎＰを用
いた場合には、ＣａＦｊ２ として１５ Ａｈ ＢａＦ
ｔ として１７Ａの積層からなる超格子絶縁膜を用いる
と低界面密度が得られる。絶縁物としてＣａＦ２とＢａ
Ｆ２以外にスピネル（ＭｇＡＪ、 Ｏ，）とＭｇＯの組
みあわせも有効である。この場合、スピネルおよびＭｇ
Ｏは下地半導体基板の格子常数とほぼ整数比を示す格子
常数をもつため、その積層による超格子薄膜も容易に半
導体基板上に単結晶化して成長する。FIG. 1 shows a cross section of an MIS device that is a first embodiment of the present invention. A superlattice insulating film 4 having a structure in which first insulators 2 and second insulators 3 are alternately stacked on the surface of a semiconductor substrate 1.
is deposited, and a metal thin film 5 is further deposited thereon. Here, when p-type GaAs is used as the semiconductor substrate 1, for example, Cart is selected as the first insulating layer, and BaF2 is selected as the second insulating layer, and the total thickness is reduced to 15A and 6A by molecular beam epitaxy, respectively. are alternately deposited until 210OA is reached. The metal thin film 5 is made of AI with a thickness of 3
000 A was deposited by vacuum evaporation. The interfacial density of this MIS device was as low as I x 10' cm-. When p-type InP is used as the semiconductor substrate 1, 15 Ah BaF as CaFj2
When a superlattice insulating film consisting of a 17A stack is used as t, a low interfacial density can be obtained. CaF2 and Ba as insulators
In addition to F2, a combination of spinel (MgAJ, O,) and MgO is also effective. In this case, spinel and Mg
Since O has a lattice constant that is approximately an integer ratio with the lattice constant of the underlying semiconductor substrate, a superlattice thin film formed by stacking O is also easily grown as a single crystal on the semiconductor substrate.
第２図は本発明の第２の実施例であるＮＩＢ装置の断面
を示す。半導体基板１の表面に第１の絶縁体２と第２の
半導体３１が交互に積層された構造をもつ超格子絶縁膜
４１が被着され、さらにその上に金属薄膜５が被着され
ている。半導体基板１としてｐ型ＧａＡｓを用いた場合
には第１の絶縁体としてけＢａ６．ｔ６ＣａＯ，１４Ｆ
２が、第２の半導体３１としては不純物をドープしてい
ないＧ ａ Ａ ｓもしくはＡｌＡｓが分子線エピタキ
シ法によって被着される。FIG. 2 shows a cross section of an NIB device which is a second embodiment of the present invention. A superlattice insulating film 41 having a structure in which a first insulator 2 and a second semiconductor 31 are alternately laminated is deposited on the surface of a semiconductor substrate 1, and a metal thin film 5 is further deposited thereon. . When p-type GaAs is used as the semiconductor substrate 1, Ba6. t6CaO, 14F
2, GaAs or AlAs not doped with impurities is deposited as the second semiconductor 31 by molecular beam epitaxy.
ＢａＯ，！６ＣａＯＪ４Ｆ２の厚さは３０ Ａｈ Ｇａ
ＡａもしくはＡ Ｉ Ａ ｓの厚さは６人が適当である
。第２の半導体としてＧ ａ Ａ ｓを選んだ場合にお
いてもその厚さは充分薄いので、超格子の価電子帯と伝
導帯間のエネルギーギャップは２．４ｅＶ以上になり、
ＧａＡｓに不純物をドープしない場合には、超格子層は
絶縁体特性を示す。この場合の界面準位密度は５Ｘ１０
”６Ｒ−２ときわめて低い値を示した。第１の絶縁体と
しては１３ａｏ、ｔｓ Ｃａｂ、？４ Ｆｔ以外にＧａ
Ａｓの格子定数と整数比の格子定数をもつ絶縁物であれ
ば、他のものでもよく例えばＭｇＯ１ＭｇＡｈＯ４等が
用いられる。半導体基板１としてＩｎＰを用いた場合に
は、第１の絶縁体としてＦｉＢａｏ、１ｓｃａｏ、ａｓ
Ｐｔが最適であり、第２の半導体としてはＩｎＰ ＊
Ｉｎ６．５２ＡＩ６．４＠ Ａｓ等が用いられる。BaO,! The thickness of 6CaOJ4F2 is 30 Ah Ga
The appropriate thickness for Aa or AIAs is 6 people. Even when Ga As is selected as the second semiconductor, its thickness is sufficiently thin, so the energy gap between the valence band and conduction band of the superlattice is 2.4 eV or more,
When GaAs is not doped with impurities, the superlattice layer exhibits insulating properties. In this case, the interface state density is 5X10
``It showed an extremely low value of 6R-2.As the first insulator, in addition to 13ao, ts Cab, and ?4Ft, Ga
Any other insulator may be used as long as it has a lattice constant that is an integer ratio to the lattice constant of As, such as MgO1MgAhO4. When InP is used as the semiconductor substrate 1, FiBao, 1scao, as
Pt is optimal, and InP* as the second semiconductor
In6.52AI6.4@As etc. are used.
本発明による半導体装置は、従来良好な界面特性が得ら
れなかったＩ−Ｖ化合物、 ＩＩ−Ｖｌ化合物に対して
もきわめて低い界面密度を与える。この結果、ＧａＡｓ
ｅ ＩｎＰ等のｉ−ｖ化合物に対しても、良好な特性
のｎチャンネルもしくはｐチャンネル絶縁ゲート型電界
効果トランジスタ、及び良好な特性のフィールド領域を
含む半導体装置が提供できる。The semiconductor device according to the present invention provides extremely low interfacial density even for IV compounds and II-Vl compounds, for which good interfacial properties have not conventionally been obtained. As a result, GaAs
Even for i-v compounds such as e InP, it is possible to provide an n-channel or p-channel insulated gate field effect transistor with good characteristics and a semiconductor device including a field region with good characteristics.
５一
本発明の特徴は、絶縁体として基板半導体の格子常数と
整数比の格子常数をもつ物質の積層による超格子膜を用
いて構成された半導体装置である。51 A feature of the present invention is a semiconductor device constructed using, as an insulator, a superlattice film formed by stacking materials having a lattice constant in an integer ratio with the lattice constant of a substrate semiconductor.
その低界面密度特性は半導体と絶縁膜間の歪みを超格子
膜内に吸収することＫよって得られている。Its low interface density property is obtained by absorbing strain between the semiconductor and the insulating film into the superlattice film.
したがって本発明の実施例で示した材料の組あわせ以外
に対しても有効であることは云うまでもない。例えば半
導体基板としては、ｐ型ＩｎＧａＡｓ 。Therefore, it goes without saying that the present invention is effective for combinations of materials other than those shown in the examples. For example, the semiconductor substrate is p-type InGaAs.
Ｉ ｎ ＧａＡｓ Ｐ混晶等が用いられる。In GaAs P mixed crystal etc. are used.
また前記実施例ではＭＩ８装置を用いて本発明を説明し
たが、別にこれに限る必要はなく、一般に半導体上に低
い界面準位密度で絶縁体を形成したいとき本発明は有効
である。Furthermore, although the present invention has been explained using an MI8 device in the above embodiment, there is no need to limit it to this, and the present invention is generally effective when it is desired to form an insulator with a low interface state density on a semiconductor.
また上記整数比については５整数の値祉なるべく５を超
えない方がよい。（例えば３：５．２：５など）整数比
からのずれも１０％以内であることが望ましい。Regarding the above integer ratio, it is preferable that the value of 5 integers does not exceed 5 if possible. (For example, 3:5.2:5, etc.) It is desirable that the deviation from the integer ratio is also within 10%.
また絶縁膜上に被着される金属膜のかわりに低抵抗の半
導体膜を用いてもよい。Furthermore, a low-resistance semiconductor film may be used instead of the metal film deposited on the insulating film.
６一61
第１図、第２図はそれぞれ本発明の実施例であるＭＩ８
装置の断面を示す図であり、１は第１の半導体からなる
基板、２は第１の絶縁体、３は第２の絶縁体、３１は第
２の半導体、４，４１は超格子絶縁体膜、５は金属膜で
ある。
代理人弁理士内 原 晋
７−
第１図
第２図
工〕
入２
−（−１
１４９−
４１
ＩFIG. 1 and FIG. 2 each show an MI8 which is an embodiment of the present invention.
It is a diagram showing a cross section of the device, in which 1 is a substrate made of a first semiconductor, 2 is a first insulator, 3 is a second insulator, 31 is a second semiconductor, and 4 and 41 are superlattice insulators. The film 5 is a metal film. Representative Patent Attorney Susumu Hara 7- Figure 1, Figure 2] Iri 2-(-1 149- 41 I
Claims (1)
装置において、該絶縁体が第１の絶縁体と第２の絶縁体
、もしくは第１の絶縁体と第２の半導体が交互に積層さ
れた超格子構造をもち、かつ第１の絶縁体と第２の絶縁
体もしくは第１の絶縁体と第２の半導体の格子定数が、
第１の半導体の格子定数とそれぞれほぼ！！数比を示す
ことを特徴とする半導体装置。In a semiconductor device in which at least an insulating film is deposited on a first semiconductor, the insulator is a first insulator and a second insulator, or a first insulator and a second semiconductor are alternately stacked. has a superlattice structure, and the lattice constants of the first insulator and the second insulator or the first insulator and the second semiconductor are
The lattice constant of the first semiconductor and each approximately! ! A semiconductor device characterized by exhibiting a numerical ratio.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15981283A JPS6052027A (en) | 1983-08-31 | 1983-08-31 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15981283A JPS6052027A (en) | 1983-08-31 | 1983-08-31 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6052027A true JPS6052027A (en) | 1985-03-23 |
Family
ID=15701787
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15981283A Pending JPS6052027A (en) | 1983-08-31 | 1983-08-31 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6052027A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0398135A2 (en) * | 1989-05-13 | 1990-11-22 | Forschungszentrum Jülich Gmbh | Optoelectronic device |
-
1983
- 1983-08-31 JP JP15981283A patent/JPS6052027A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0398135A2 (en) * | 1989-05-13 | 1990-11-22 | Forschungszentrum Jülich Gmbh | Optoelectronic device |
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