JPS6051723B2 - Sequence controller with input/output address changing function - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention selects input/output elements connected to a plurality of input/output terminals of an input/output circuit based on data in an input/output address section of a sequence program read from a program memory. The purpose is to quickly modify sequence programs caused by reconnecting input/output elements connected to a given input/output terminal to other input/output terminals. Even if an input/output terminal becomes unusable due to a partial failure of the input/output circuit, the input/output elements connected to the unusable input/output terminal can be connected to other unused input/output terminals. The purpose is to allow operation to resume in a short time by simply changing the connection to the output terminal.

In general, stored program type sequence controllers have all circuits made of semiconductors and are highly reliable.
Since a higher voltage is applied to the input/output circuits to which limit switches and relays are connected than to logic circuits, failures may occur due to abnormalities in the voltage drop capacitors or output switching elements in the input/output circuits. It happens rarely.

When such a failure occurs, a particular one of the input/output terminals provided in the many input/output units that make up the input/output circuit becomes unusable, and if that particular terminal is an input terminal, the input element Conventionally, when such a failure occurs, the input/output unit in which the failure has occurred is disconnected from the open/close signal, and if it is an output terminal, the output element cannot be turned on or off, making it impossible to perform sequence control normally. I replaced it with a good quality input/output unit and restarted the operation.

However, general input/output units have 8 to m
Since there are 1 input/output terminals, in order to replace the input/output unit, you must disconnect all other input/output terminals unrelated to the failure and replace the input/output unit. When a failure occurs in the input/output circuit, it is difficult to restart operation in a short period of time, which has a significant impact on production.

On the other hand, another method for re-establishing operation in the event of a failure as described above is to reconnect the input/output element that is unusable and connected to the input/output terminal to another input/output terminal that is not in use. There is also a method, which not only does not require replacing the input/output unit, but also eliminates the need to disconnect terminals that are not related to the failure, so wiring can be removed and installed in a short time. However, with this method, the positions of the input/output terminals connected to specific input/output elements change, so
The sequence program had to be modified, and even if this method was used, it was difficult to restart the operation in a short time.

In other words, when a specific input/output element is connected to a different input/output terminal, the operand part of the sequence program whose operand part is the input/output address data of the input/output terminal to which the input/output element was previously connected is changed. All of them need to be corrected, but in order to make such corrections, it is necessary to refer to the program sheet etc. and find out where in the sequence memory the sequence program to be corrected is stored, otherwise the sequence program will not be rewritten. This is because the sequence program cannot be corrected in a short period of time.

The present invention enables this program to be modified in a short period of time, thereby resolving input/output terminals that have become unusable. This was done based on the fact that operation could be resumed in a short time simply by reconnecting the connected input/output elements, and after reconnecting the input/output element to be reconnected with the address of the input/output terminal before reconnecting. Set the address of the input/output terminal of , and rewrite from outside. This system is characterized in that the sequence program can be modified simply by supplying a command signal.

Embodiments of the present invention will be described below with reference to the drawings.

In FIG. 1, 10 is a program memory for storing sequence programs, 11 is a program counter,
The output of the program counter 11 is the program memory 10
is applied to the address terminal ADD of the program memory 1.
0 address specification. This program memory 10 is a core memory, and has a data output terminal DO, a data input terminal DI, and a command terminal RC. WO is provided. Since the core memory is destructively readable, it is necessary to write the read data again after reading the data. In this embodiment, among a series of control clocks CLl to CL6 output from the control clock generation circuit 15, the control clock CL
1 is applied to the read command terminal IRC to read the sequence program, and the control clock CL3 is applied to the write command terminal W.
I am trying to rewrite it by giving it to C. Further, the program counter 11 is incremented at the timing of the control clock CL6. Note that the program memory 10 has a built-in latch circuit, and the same data is output from the data output terminal DO until the next sequence program is read. The data read from the program memory 10 is output to the data bus DB via the gate G1, and among the 16 bits of sequence program data, the upper 5 bits of data indicating the instruction word directly indicate the input/output address. The data at the lower position 1 bit is applied to the data input terminal DI of the program memory 10 via the gate G2, and the data at the lower position 1 bit representing the input/output address is also applied to the comparator 23, which will be described later. It's becoming like that.

Reference numeral 12 denotes an address decoder, which is an input unit to which input elements such as a limit switch LSLO are connected according to the upper 8 bits of the input/output address data of the lower 1 bit of the sequence program data outputted to the data bus DB. One of the output units 0U1 to 0Un to which an output element such as IUl to IUn or relay CRlO is connected is selected.

Input units IUl to IUnl and output unit 0U
Eight input/output terminals are provided for each of 1 to 0Un, and eight input elements or output elements are connected to each unit. These input/output units IUl~0U
A selector is provided inside n for selecting one of the input/output elements connected to the eight input/output terminals by the lower three bits of address data LAD supplied from the data bus DB. The on/off state of the selected input/output element is output to the signal line IOB. Further, 13 is an instruction decoder that decodes data in the upper 5 bits of the instruction part of the sequence program data output to the data bus DB, and this instruction decoder 13 outputs a command signal according to the decoded instruction for testing. The signal is applied to the flag circuit 14.

This test flag circuit 14 receives an on/off signal of a specific input/output element selected by the input/output address data of the program outputted to the signal line IOB according to a command from the instruction decoder 13, and performs a logical operation on it. Tsutari,
A signal corresponding to the result of a logical operation is output to the signal line SLO to energize or de-energize a specific output element, and the control clock C output from the control clock generation circuit 15
It is designed to operate at the timing of L4. on the other hand,
The rewrite command circuit 20, first and second address setters 21 and 22 consisting of digital switches, etc., and the comparator 23 include an AND gate AGl, a NAND gate NGl, and gates G1 to G.
3. Together with the inverter IN■, it constitutes a circuit that rewrites the input/output address, and the data of the input/output address before being connected to the first address setting device 21 is set, and the data of the input/output address is set before being connected to the second address setting device 22. The data for the later input/output address is set.

The input/output address data set in the first address setter 21 is compared by the comparator 23 with the data in the input/output address part of the sequence program data read from the program memory 10, and the data match. In this case, a match signal EQS is output from the comparator 23. This match signal EQS is sent to the gate G via the AND gate AGl.
3 and G via Nandocate NGl
2, and the AND gate AGl
When the NAND gate NGl is closed, a high level signal is applied to the gate G2, the gate G2 is opened, and the data in the input/output address portion of the sequence program read from the program memory 10 is transferred to the data input terminal DI. Given, AND gate AGl, NAND gate N
If Gl is open, a match signal E is output from the comparator 23.
When QS is output, gate G3 replaces gate G2.
A high level signal is given to the gate G3, which opens the gate G3.
Data at the input/output address set in the second address setter 22 is applied to the data input terminal DI. Further, the rewriting command circuit 20 generates a rewriting command signal RWC,
It is composed of a one-shot multi-pipe letter, etc., and when the push button switch SWlO for rewriting command is pressed,
The rewrite command signal RWC is designed to have a longer time width than when the sequence program stored in the program memory 10 is read out once.

This rewriting command signal RWC is applied to the AND gate AGl and the NAND gate NGl, and is also applied to the gate G1 via the inverter INV, and the opening and closing of these gates is controlled by the rewriting command signal RWC. . That is, the push button switch SWl for rewriting command
When O is not pressed and the rewrite command signal RWC is not output, gates G1 and G2 are opened, and the program memory 1
Data of the sequence program read from 0 at the timing of the control clock CLl is output onto the data bus DB, and is also applied as is to the data input terminal DI of the program memory 10.

Therefore, when the rewriting command pushbutton switch SWlO is not pressed, control based on the read sequence program is executed, and the read sequence program data is directly stored in the program memory 10 at the timing of the control clock CL3. This prevents the sequence program data from being written again and disappearing from the program memory 10. On the other hand, when the rewrite command pushbutton switch SWlO is pressed and the rewrite command signal RWC is output, the gate G1 is closed, so the sequence program is not executed and only the program is modified.

That is, the control clock CL is input from the program memory 10.
When the sequence program is read out at timing 1, the data in the input/output address part of the sequence program data is compared with the address data set in the first address setter 21 by the comparator 23, and both are matched. Only when they match, a match signal EQS is output from the comparator 23, and gate G3 is opened instead of gate G2.
As a result, the data input terminal D of the program memory 10
I is given the data of the input/output address set in the second address setter 22, and this data is written together with the data of the instruction part read from the program memory 10 at the timing of the control clock CL3. By repeating these operations, a sequence program whose operand part is the input/output address data set in the first address setter 21 is searched, and the data of the operand part of the searched sequence program is The address data is rewritten to the address data set in the second address setter.

Therefore, the input/output address data before being connected to the first address setter 21 is set, and the second address setter 2
By setting the input/output address data after reconnecting to 2 and operating the pushbutton switch SWlO, the program correction caused by reconnecting the input/output elements will be automatically performed. Since the rewrite command signal RWC output from the rewrite command circuit 20 is sent out for a longer time than it takes for the sequence program to be read once from the program memory 10, it is difficult to determine where the sequence program to be corrected is stored. Corrections will be made even if the now,
Due to a failure in the output unit 0U, the output terminal at input/output address 57 cannot be used, and the output terminal at input/output address 57
When the output element connected to the address is reconnected to the output terminal of address 107, which remains unused, data representing 57 is set in the first address setter 21,
It is sufficient to set data representing 107 in the second address setter 22 and press the pushbutton switch SWlO.

As a result, among the sequence program data shown in FIG. 2a, the operand part of the sequence program whose operand part data is 57 is all rewritten to 107 as shown in FIG. 2b, and the program is corrected. be exposed. In the above embodiment, the sequence program is not executed while the rewriting operation is performed, so the sequence control operation is temporarily stopped. However, if the gate G1 is not provided, the sequence control cannot be stopped. If a single sequence controller is controlling multiple machines, the program can be modified while continuing to control machines unrelated to the failure. Can be done.

In addition, if the sequence program has a jump instruction, or if these setting values and current values are stored in the address following the timer or counter instruction, the setting values and current values of the timer or counter will be rewritten. or the jump destination address may be rewritten,
In such a sequence controller, data in the instruction part of the sequence program read from the program memory 10 is decoded, and if the read sequence program has a jump instruction, rewriting is stopped in that cycle, and the timer and counter are If it is a command, rewriting in the next cycle may be canceled.

Furthermore, in the above embodiment, a one-shot pipe regulator is used so that when the pushbutton switch SWlO is pressed once, a rewrite command signal with a longer duration than when the sequence program is read out once is output. However, since the time required for a sequence program to be read once is approximately several tens of nanoseconds, the pushbutton switch S
The rewrite command signal may be sent while WIO is being pressed.

As described above, in the sequence controller of the present invention, connections can be changed by simply setting the input/output address before connection change and the input/output address after connection change and operating a command switch such as a pushbutton switch. This eliminates the need to refer to a program sheet or the like to find where in memory the sequence program to be rewritten is stored, as was the case in the past. Even if there are many sequence programs to be rewritten, all sequence programs can be modified in one operation, and programs caused by reconnecting input/output elements can be modified in a short time.

Therefore, if a specific input/output terminal becomes unusable due to a failure in the input/output circuit, operation can be resumed in a short time by simply reconnecting the specific input/output element, which will have a negative impact on production. The impact can be kept to a minimum.

[Brief explanation of drawings]

The drawings show an embodiment of the present invention, and FIG. 1 is a block diagram showing the configuration of a sequence controller. FIGS. 2A and 2B are diagrams showing a sequence program before and after rewriting, respectively. 10...Program memory, 11...
Program counter, 12...Address decoder, 13...Instruction decoder, 14...Test flag circuit, 20...Rewrite command circuit, 21
...First address setter, 22...Second
Address setter, 23... Comparator, AGl...
...and gate, G1-G3 gate, INV...
...Inverter, IUl~IUn...Input unit, NGl...NAND gate, 0U1~
0Un... Output unit, SWlO...
・Push button switch.

Claims (1)

[Claims] 1. In a sequence controller that stores a series of sequence programs in a rewritable program memory, first address data representing the input/output address of an input/output terminal that is no longer used due to a failure of the input/output circuit, etc. and second address data representing an input/output address of an input/output terminal used in place of an input/output terminal that is no longer used; and a sequence program stored in the program memory in order. a reading means; a determining means for comparing data in the input/output address section of the sequence program read by the reading means with the first address data to determine whether the two match; If the determining means determines that the two data match, the data in the input/output address section of the read sequence program is changed to the second address data and written to the original storage address. an input/output address changing function characterized by comprising: a writing means; and a control circuit that operates the determining means and the writing means according to an external command while at least one reading of the sequence program is performed. A sequence controller with