JPS605160B2 - How to control a pulse motor - Google Patents

Description

[Detailed description of the invention] The present invention relates to a method for controlling a pulse motor.

A pulse motor is a motor that rotates by a fixed angle in response to one input shift pulse, and therefore the rotation angle is proportional to the number of input shift pulses, and is also referred to as a step motor or step motor.

In recent years, with the progress and spread of integrated circuits, control using digital processing has become widespread, and the importance of pulse motors as output devices has rapidly increased. The present invention provides a control method that can control a pulse motor over a wide range of functions, including starting, stopping, constant speed, and high-speed operation, as well as accurate positioning and synchronized operation with external equipment.

Hereinafter, an embodiment in which the present invention is applied to a pulse motor for conveying a passbook and a pulse motor for moving a print head in a bookkeeping machine such as an automatic teller machine or a payment machine will be described in detail.

1 and 2 show a passbook conveying machine and a printing mechanism in a bookkeeping machine.

The conveyance mechanism includes a large number of conveyance rollers 5 arranged vertically.
1 and a conveyor belt 52 hooked around these rollers 51, and along the conveyance path, a passbook position detection switch 53, a print line detection sensor 54, a page count sensor 56, etc. are arranged. The printing mechanism includes a print head 55 provided at a suitable location on the conveyance path. The conveyance roller 51 is driven by a passbook conveyance pulse motor 87 (see FIG. 6), which will be described later.
After 0 is positioned at a predetermined position, the print head is moved by the drive of a pulse motor 88 (see FIG. 6) to print numbers and the like on predetermined print lines of the passbook.
The printing paper of the passbook 50 is provided with columns for printing the date, refund amount, deposit amount, and balance, and a bar code or Arabic numeral 57 representing the page number is printed in a designated margin. There is. The printed line detection sensor 54 is located at the date column of the bankbook 50 when the bankbook 50 is conveyed, and the sensor 56 is located at a position where the number 57 representing the number of pages passes. For example, reflective photoelectric detectors are used as these sensors 54 and 56, and the previous printed line is detected based on a change in the amount of light reflected from the date column.
Furthermore, as these sensors 54 and 56, image pickup devices such as charge coupled devices CCDs can also be used. When the passbook 50 with the required page opened is inserted into the bookkeeping machine, this is detected by a passbook insertion detection switch (not shown),
The passbook conveyance motor 87 is started, and the passbook 50G is conveyed downward while being sandwiched between the belts 52.

Then, when the bottom line of the date field on the printing paper of the passbook 50 is exactly facing the sensor 54, the detection switch 53
(See Figure 2a). From this point on, the sensor 54 starts negotiating the date column. The bank book 50 continues to be transported downward, and as the bankbook 50 is transported, the sensor 54 scans the date column of the bankbook 50 from the bottom to the top. Then, since the amount of reflected light input to the sensor 54 when the previous printed line faced the sensor 64 decreases, a detection signal is output from the sensor 54 (FIG. 2b). Thereafter, the passbook 50 is conveyed downward by a certain distance LO, and when the line to be printed this time, which is the next line of the previous print line, reaches a position facing the print head 55, the passbook conveying pulse motor 8
7 stops, and the passbook 50 is positioned at that position.
Feeding amount L of the passbook 50 from when the detection signal is output from the detection switch 53 until the sensor 54 detects the previous printed line
I varies depending on the position of the previous printed line, but the sensor 54
The feed amount LO from when detecting the previous printed line until the current printed line reaches the position facing the print head 55 is always constant. When the passbook 50 is positioned at a position where the current print line faces the print head 55, the print head movement pulse motor 88 is then driven to move the print head 55 laterally, and the date, refund amount, Predetermined characters are printed in a predetermined column of the deposit amount and balance balance columns according to a command from a central processing unit (hereinafter referred to as CPU). FIG. 3 shows the shift pulse SP of the pulse motor and the excitation current waveforms of each phase A and B of the stator armature winding in the case of the two-phase simultaneous excitation method. A and B indicate reverse currents of each phase A and B. The excitation phase is switched from AB to AB to AB to AB for each shift pulse SP. If this is considered normal rotation, then for reverse rotation, the excitation phase is switched from AB to AB to AB to AB for each shift pulse SP. It can be switched to Permanent magnet PM type pulse motor rotation speed n r
．． p. m. is the frequency of the shift pulse SP SHZ,
If the number of teeth of the rotor is N, then n=6 eaves/small, which is proportional to the frequency S of the shift pulse SP.

FIG. 4 shows how the pulse motor 87 is controlled after the passbook 50 is inserted into the bookkeeping machine until the passbook 50 is positioned so that the current print line faces the print head 55 and stopped.

During the starting period TI of the pulse motor 87, the shift
The pulse SP interval is large, from tl to t2, t3, t4,
It starts at t5 and decreases to 4. The pulse motor 87 is gradually accelerated. During the constant speed period T2, the shift pulse SP interval is constant t5, and the pulse motor 87
is operated at a constant speed. During the stop period T3 before stopping, the shift pulse SP intervals are from t5 to t6, t7, t
It starts at 8, t9, increases in speed, and comes to a stop while being decelerated. In this example, tl, t2, t3, t4 are 6, 5, 4, 3 s, respectively, t5 is 2ms, t6,
t7, t8, and t9 are set to s of 3, 4, 5, and 10, respectively. After inserting the passbook 50, when it is detected,
As will be described later, a start pulse SS is output, the pulse motor voltage is switched from the holding voltage (for example 4V) to the operating voltage (for example IW or 24V), and the pulse
Motor 87 is started.

Then, when the bankbook 50 is inserted to the position of the conveyor belt 52, conveyance of the bankbook 50 starts. As the bankbook 50 is being conveyed, when the lower end reaches the position of the switch 53, this is detected by the switch 53, and when the previous printed line is detected by the sensor 54, the bankbook 50 is conveyed a certain distance LO from this point onwards. After that, it is positioned at the printing position as described above. When the passbook 50 has just reached the printing position, the pulse motor voltage drops to the holding voltage and the pulse motor 87 stops. Now, sensor 54
Since the detection of the previous printed line by the pulse motor 87
The feed amount of the bankbook 50 until it is stopped is a constant value LO. On the other hand, the rotational speed n of the pulse motor 87 is
It is determined by the frequency of pulse SP. Therefore, if the number and pulse interval of shift pulses SP to be sent to the pulse motor 87 from the point in time when the sensor 54 detects the previous printed line is determined in advance, the pulse motor 87 is can be stopped exactly. Such output control of the shift pulse SP is executed based on a control code stored in advance in the storage device.

This control code consists of 8 bits as shown in FIG.
CD3, CD4, CD5, CD6, CD7, etc. The lower 5 bits CDO to CD4 are allocated to time information TI, and the upper 3 bits CD5 to CD7 are allocated to control information CI. The time information TI represents the shift pulse SP interval tl to t9, and the arbitrary shift pulse interval t is t=[CD4×〆10CD3×10CD2×〆10CDIx+CDO×〆11] It is given by s of ×0.1.

For example, if the time information TI is 11111'', this represents s with t=3.2, and ``11011'' is 2.
It represents 8ms.

The control bit CD5 of the control information CI is a buffer shift control bit (proposal control bit), and is used to enable or disable shift of the FIF○ (F ship t-ln-F ship t-○ mountain) buffer register 60, which will be described later. Indicates prohibition. When CD5 is 1", shifting is permitted, and this is called a variable mode. When CD5 is 0", shifting is prohibited, and this is called fixed mode. The variable mode is used in the case of a pulse motor starting period T1, stopping period T3, and fixed-dimension feeding in which the motor is fed by a distance LO after a detection signal is output from the sensor 54. The fixed mode is used when the pulse motor is simply operated at a constant speed (for example, during a constant speed period T2) or when the operating state is changed based on a detection signal from the sensor 54, that is, when synchronizing with an external synchronization signal. Control bit CD6 is a control bit for shift pulse SP, and is used to enable or disable output SPO when shift pulse output SPO is output from timer 62, which will be described later. As mentioned above, the maximum value of the shift pulse interval given by the time information TI is 3.2 s, so with 5 bits of time information, tl, t2, t
It is not possible to represent a shift pulse interval of 3.3 s or more, such as 7, t8, or t9, and a control code of two or more words is required for a shift pulse interval of 3.3 s or more. Therefore, when the time information TI spans two or more words, CD6 is expressed as 0''.
Pulse SP generation is prohibited). When CD6 is 1'', the shift pulse interval t can be expressed by one word of time information TI, and this is set as the normal mode (shift pulse SP generation is permitted). , control bit CD6 is used to control the operation according to the previous stage control code. In this embodiment, control bit CD7 is used to control an AND gate 73, which will be described later, and when CD7 is 0'', the AND gate 73 is is closed, and when CD7 is "1", AND gate 73 is opened.

CD7 is used in combination with CD6, and in particular, the combination of CD7 = 1'' and CD6 = 0'' indicates a pulse motor stop (end code). Control bit CD7 is also used for other controls as will become clear later. For the control shown in FIG. 4, control codes shown in the following code table are prepared in advance and stored in the storage device.

In the code table shown in FIG. 6, the FIFO buffer register 60 temporarily stores control codes sent from the storage device via the data bus. Codes will be sent out on a first-come, first-served basis.

Of the control codes output from the FIFO register 60, time information TI is sent to the timer 62, and control information CI is sent to the control circuit 64. This FIFO register 60 has a capacity of 8 bits x 64 stages and 6 bits. The buffer control circuit 61 controls the transfer of control codes to the FIFO register 60, and outputs a transfer request signal to the CPU and monitors the status of the FIFO register 60, such as whether the FIFO register 60 is full or empty. is notified to the CPU. Cook pulse C from CPU
P is input to a frequency divider 63, and is divided into an appropriate frequency by this frequency divider 63. The timer 62 is specifically a preset counter that counts the pulses from the frequency divider 63, and when the counted value reaches the preset value represented by the time information TI from the FIFO register 60, Output SPO for pulse-shaped shift pulse S and time
The up signal TU is generated simultaneously. The shift pulse output SPO is sent to a shift pulse control AND gate 66, and the time up signal TU is sent to a control circuit 64. The control circuit 64 uses the start pulse SS and time up signal TU as input signals to determine the reference timing.
OR circuit 71 that outputs pulse TR, control bit CD5 output of control information CI, and IJ start control circuit 68
An AND gate 73 that uses the inverted signal of the control bit CD6 output, the control signal, and the control bit CD7 output as input signals to detect the end code, and a pulse motor. flip-flop 74, variable mode indicating that is being driven;
It consists of a ◯ flip-flop 75 for fixed mode switching and a D flip-flop 76 for stopping the pulse motor.

The reference timing pulse TR of the OR circuit 71 is sent to the shift and load pulse generation circuit 65, and is also input to the set input resistor S of the flip-flop 74 and the trigger input terminal T of the D flip-flops 75 and 76. do. The output of the OR circuit 72 and the AND gate 73 is D
The data is input to data input terminals D of flip-flops 75 and 76, respectively. The D flip-flops 75 and 76 check the state of the signal input to their input terminal D at the timing of the pulse TR, and if the input signal is "H", the output of the positive output terminal Q is set to "H". If the input signal is low, the output of the inverting output terminal Q is high.

Since the output of the OR circuit 72, that is, the control bit CD5 output or the restart signal RS, is input to the data input terminal of the D flip-flop 75, the control bit CD
5 is 1'' (that is, the CD5 output is ``H'') or the restart signal RS is ``H'', these are read when the reference timing pulse TR is input to the terminal T, and the output Q is ``H''. The output Q is the variable mode signal KA. Conversely, the control bit CD5 is set to 0'' (that is, the CD
5 output is ``L'') and the restart signal RS is ``L'', the timing output Q of the pulse TR is , L'', Q
becomes “H”. Let the output Q be the fixed mode signal KO.
The variable mode signal KA is sent to an AND gate 67 for buffer shift pulse control, and the fixed mode signal KO is sent to a restart control circuit 68. The output of the AND gate 73 is the control bit CD6 0'' (CD6 output LOW).
'') and the control bit CD7 is 1'' (CD7 output is H''), it becomes H'' only.

Since the output of the AND gate 73 is input to the data input terminal D of the D flip-flop 76, the AND gate 7
Only when the output of D flip-flop 76 becomes H'', the output Q of the D flip-flop 76 becomes H'' at the input timing of the reference timing pulse TR. The output of the D flip-flop 76 is used as the motor stop signal MS. This signal MS is sent to the reset input terminal R of flip-flop 74 and is read by the CPU. The flip-flop 74 is set by the start pulse SS inputted through the OR circuit 71, and thereafter remains set until the motor stop signal MS becomes H''.

That is, the flip-flop 74 continues to be held in the set state while the pulse motor is driven, and continues to output the high-level output Q. The output Q of the flip-flop 74 is sent to the timer 62 and as a reset release signal. It is sent to the shift and load pulse generation circuit 65, and both circuits 62
, 65 continue to operate while this output Q is high. When the reference timing pulse TR is input, the shift and load pulse generation circuit 65 lags slightly (time ta) behind the reference timing pulse TR. At this point in time, the buffer load pulse BL is outputted, and a buffer shift pulse spot is outputted which is delayed even slightly (time scale) from this pulse BL (see FIG. 7).

Buffer load pulse BL is sent to timer 62. The buffer shift pulse spot is sent to the AND gate 67 and passes through the gate 67 to the FIF only when the variable mode signal KA is high and the AND gate 67 is open.
O register 601 is sent. AND gate 66 has
Control bit CD6 output is input. control bit cd
6 is 1'' (CD6 output is H''), the AND gate 66 is opened, and if the pulse SPO is output from the timer 62 at this time, this pulse SPO is output from the gate 66.
is sent out as a shift pulse SP. When control bit CD6 is 0'' (CD6 output is low) and AND gate 66 is closed, even if timer 62 outputs pulse SPO, this pulse SPO does not pass through gate 66. Among the control codes stored in the first stage (output side) of the FIFO register 60, the control information CI remains 1'' from the time it is shifted to the first stage until the control code of the next stage is shifted to the first stage. or
,0'', the OR circuit 72 of the control circuit 64, the AND gate 73,
and is input to AND gate 66.

Furthermore, time information TI among the control codes stored in the first stage of the Fm○ register 60 is input to the timer 62 as preset data when the load pulse BL is sent to the timer 62. Now, the timer 62 reads the time information 1111 in the control code DI of the code table mentioned above.
1". At this time, the control code D2 is at the forefront of the FIFO register 60. Since CD6 is 0" among the control information of the control code D2, A
ND gate 66 is closed. Also, among the control information of the control code DI, at the time when CD5 is 1'' and the start pulse SS is sent, the D flip-flop 7
The AND gate 67 is open because the variable mode signal KA of No. 5 is already at H''. The timer 62 is 3.2.
When the time-up signal TU and the shift pulse output SPO are output by measuring the time s of・It is sent to the terminal T of the flop 75 (the operation of the flip-flops 74 and 76 is not considered here), and the output SP
O is sent to AND gate 66. Control bit CD5 of control code D2 is 1'', and is output as an H'' signal.
Since the pulse TR is input to the terminal D of the flip-flop 75 via the R circuit 72, this H'' signal is read when the pulse TR is input to the terminal T, and the output Q of the flip-flop 75, that is, the variable mode signal KA. YesH'' continues to be held, and gate 67 also continues to be opened. On the other hand, the control bit 06 of the control code ○2 is 0'' and the AND gate 66 is closed as described above, so even if the output SPO is sent to the AND gate 66, no shift pulse SP is generated. As a result, the load pulse BL is output a little (time ta) after the reference timing pulse TR is input to the pulse generation circuit 65, and as a result, the FIFO register 6
The time information 11011'' of the control code D2 stored in the first stage of 0 is input to the timer 62, and the timer 62 starts timing operation again.Load pulse BL
A little later (time tb) after the output of the shift pulse BS, the shift pulse BS is output from the generation circuit 65, and the shift pulse BS is output from the gate 67.
is open, so this pulse mother is FIFO register 60
1 is sent, and the control code D3 is shifted to the front stage of the FIFO register 60. Shift pulse BS is load/
Since it is output a little later than the pulse BL, after the time information TI of the control code D2 is loaded into the timer 62, the control code 03 is shifted to the front stage of the FIFO register 60. Also, control bit CD of control code D2
51, the AND gate 67 is controlled to open and close, and the shift pulse BS is output later than the pulse TR, so the control bit CD5 sends the shift pulse BS to the F0 register 601 and to the FIFO register 60. It will be appreciated that a decision is made as to whether to shift the contents of . Furthermore, the shift pulse BS is the output SP
At the time when the output SPO, which is generated by timing the time information of the control code DI and is output later than O, is output, the AND gate 66 is controlled by the control bit CD6 of the control code D2, and the output SPO is generated by timing the time information of the control code DI. Whether or not to generate the shift pulse SP is determined by the control code D2, that is, the control bit CD of the next stage control code.
It will be understood that it is determined by 6. Furthermore, in FIG. 6, the restart control circuit 68 receives an external synchronization signal from the sensor 54 or the CPU and satisfies a predetermined condition when the pulse motor is driven in the fixed mode (CD5 ``0''). The system switches to variable mode drive when the

This restart condition is stored in latch circuit 69 from the CPU via the data bus. For example, sensor 5
When a command to change to variable mode is sent to the latch circuit 69 when there is a detection signal from the sensor 4, if there is a detection signal from the sensor 54, the restart control circuit 68
is the fixed mode signal KO from flip-flop 75
is “H” and send the restart signal RS,
, H''. Since this signal H'' is input to the terminal D of the flip-flop 75 via the OR circuit 72, the output Q of the flip-flop 75 is changed at the timing of the pulse TR.
That is, variable mode signal KA becomes "H". Restart processing is the process of changing a pulse motor from being driven in a fixed mode to a variable mode using an external synchronization signal or the like. This restart process is performed by sensor 5.
In the case where the passbook 50 is conveyed by a distance LO and stopped after detecting the previous printed line in step 4, or as described at the end, the control bit CD7 is set to 1'' after the external synchronization signal is input and a predetermined number of shift pulses are output. AND gates 81 and 8 are used for the two pulse motors, the passbook transport pulse motor 87 and the print head movement pulse motor 88, respectively.
2. Phase generation circuits 83, 84 and drive circuits 85, 86
A power supply circuit 89 is provided.

The latch circuit 80 includes two pulse motors 87 and 88.
Motor selection commands for which motor to drive, rotation direction commands for forward or reverse rotation, start and stop commands, etc. are sent from the CPU via the data bus. AND gate 81, 8
2 is controlled by a motor selection command, and the gate corresponding to the selected pulse motor is opened. AND gate 6
The shift pulse SP from 6 is sent through an opened gate 81 or 82 to a phase generation circuit 83 or 84.
The phase generation circuits 83 and 84 generate the phases A, A, B, and B shown in FIG. 3 based on the shift pulse SP, and switch the excitation phases described above in response to the rotation direction command. It will be done. The drive circuits 85 and 86 are, for example, power/
Based on the signals of each phase from the phase generation circuits 83 and 84 including transistors, etc., the excitation phase current is sent to the pulse motor 87.
, 88. The drive circuits 85 and 86 include a power supply circuit 8.
Drive power is supplied from 9. The power supply circuit 89 supplies electric power from the time when a start command is received until a stop command is received, and also supplies electric power, such as a pulse signal, in response to a motor selection command.
The operating voltage is selected and outputted, such as 24V for the motor 87 and 12V for the pulse motor 88. Referring to FIG. 8, the drive of the passbook conveying pulse motor 87 is controlled by the control code DI~ which is stored in the storage device.
Transfer D26 to Fm○ register 60 (step 1)
It starts from that.

The control code reading and writing to the F'0 register 60 in step 1 are performed one word, that is, one byte at a time, and it is determined for each write whether or not all control codes have been transferred (step 2). In this example, since we know in advance that the number of words in the control code DI~○26 is 26, we preset the number of words to 26 in the data counter inside the CPU and write each word to the F○ register 60. Each time the transfer is completed, the inside of this data counter is decremented by 1 (step 4 to be described later), and when the contents of the data counter reach 0, the transfer of all control codes is completed. In the case of completion, the process moves to step 5, and if the content of the data counter is not yet 0, the process moves to step 3. In step 3, F
Determine whether IFO register 3 is full.
As mentioned above, Fm○ register 3 has a capacity of 6 bits, so in this example, the FIFO register is not filled with written control codes, but the total failed control codes are 6 bits. This step 3 is necessary because the size is more than a small amount. The status of the FIFO register 60 is detected by the buffer control circuit 61 and a CPU status signal (for example, a READY signal, which will be described later) is sent to the CPU. Based on this signal, the judgment in step 3 is made. If YES, the process proceeds to step 5. If the answer is NO, proceed to step 4. In step 4, control code FIFO register 6
Each time a write to 0 is made, the contents of the data counter are decremented by 1, and the contents of the memory address counter are decremented by 1. The control codes are stored in the storage device in consecutive addresses starting from a specific address. In step 1, if the first address is set in the address counter when the first control code DI is output, the next control code is output by incrementing the contents of the address counter by 11 after issuing each control code. The address of the control code to be output is specified by the address counter. After executing the processing in step 4, the process returns to step 1, where the control code of the address specified by the address counter is written to the FIFO register 6. Steps 1-4
After returning the required number of lines, it becomes HYES in step 2 or 3, so the process moves to step 5, and the latch circuit 8 sets the driving conditions of the pulse motor, that is, the selection of the pulse motor 87 and the rotation direction (for example, forward rotation). Output and set the output. Next, a restart condition, that is, a signal specifying the sensor 54 in this example, is sent to the latch circuit 69 and set (step 6). After setting each of the above conditions, a start pulse SS is generated and a start command (start pulse SS) is output from the latch circuit 8 (
Step 7). When this start command is received, the pulse motor 87 is operated according to the sequence of the code table above by the operation of the circuit shown in FIG. 6, as will be described later.
As the pulse motor 87 operates, the control codes stored in the FIFO register 60 are sequentially read out starting from the first one, so the FIFO register 60'
These control codes must be added sequentially.

After the pulse motor 87 is started, the control code is written to the F+ register 60 according to the chart shown in FIG. Of course, here the total control code is 64
I'm thinking of more than just words. It is determined whether the READY flip-flop in the CPU is set (step 11). The state of the FIFO register 60 is read by a control circuit 61, and if the FIFO register 60' is empty, a READY signal is sent from the control circuit 61 and a READY flip-flop is set. If the READY flip-flop is not set, the CP will continue until this flip-flop is set.
U continues in WA1r state. If the determination in step 11 is YES, the process moves to step 12, and at the same time as in step 1, one word of the control code is retrieved from the storage device and written into the FIFO register 60. Then, it is determined from the contents of the data counter whether the control code has been completed, and if NO, the process moves to step 14 to discuss the status of the F'0 register 60, and if there is still space in the FIFO register 60, the process proceeds to step 14. In step 15, the contents of the data counter are decremented by 1, the contents of the memory address counter are decremented by 1, and the process returns to step 12. If it is determined in step 13 that the control code has ended or that the FIFO register 60 is filled in step 14, the CPU enters the WMT state.
The stopping operation of the pulse motor 87 starts from the time when the output of the end code D26 is read by the flip-flop 76, as will be described later, and is executed according to the flow chart shown in FIG.

First, in step 21, it is determined whether the control code has ended based on the contents of the data counter. If there is a control code that has not yet been transferred from the storage device to the FIFO register 60, the end code will not be output from the FIFO register 60, so the CPU waits. If YES in step 21, it is determined whether the motor stop signal MS is output from the flip-flop 76. Flip
If the flip-flop 76 is not set, the CPU similarly enters the WA1r state, and if the flip-flop 76 is set, a motor stop signal is sent to the latch circuit 801 (
Step 23). As a result, the operating voltage of the power supply circuit 89 drops to the holding voltage, and the pulse motor 87 stops. Referring to the above code table, FIG. 4, FIG. 6, and FIG. 7, the FIFO
Since the control code has already been stored in register 6 (Step 1 in Figure 8), the output of 1001'' is stored in FIFO register 6 as the control information of the first control code DI.
0 to the control circuit 64.

Since the output signal H'' of the control bit CD5 in the first control code DI is input to the OR circuit 72, when the start pulse SS is sent, the output signal Q of the flip-flop 75 becomes H''. Then, the variable mode signal KA becomes H''
Then, the AND gate 67 is opened. control bit cd
Since the output signal of the flip-flop 76 is low, the AND gate 73 is not opened, and the input signal of the data input terminal D of the flip-flop 76 is low, and the output Q of the flip-flop 76, that is, the motor stop signal MS, is also low. From now on,
Control bit CD until end code D26 is output.
7 is or, and the motor stop signal MS continues to be held in the state of L^. Only in the first control code DI, the control bit CD6 has no meaning. The start pulse SS passes through the OR circuit 71 and becomes the reference timing pulse TR.
When inputted to the set input terminal S of the flip-flop 74 and the shift/load pulse generation circuit 65 as
Since the flip-flop 74 is set and its set output is sent to the timer 62 and pulse generation circuit 65, both circuits 62 and 65 become operational, and after a time delay, the buffer load pulse BL is output from the pulse generation circuit 65. is sent to the timer 62, and the first control code D
The time information TI of I is input to the timer 62, and the timer 62 starts timing operation. Also, since the gate 67 is already open, the buffer shift pulse mother is sent from the generation circuit 65 to the FIFO register 60' with a delay of time tb from the pulse BL, so that the second control code ○2 becomes Fm ○ Shifted to the first stage of the register 60. After the flip-flop 74 is set by the start pulse SS, it continues to be held in the set state until the motor stop signal MS becomes H''.The second control code D2
Since the control information of is oor, the output by control bit CD6 is L.
'' is input to the AND gate 66, and the AND gate 66 is held closed.

Also, the output H'' by control bit CD5 flips.
It is input to the data input terminal D of the flop 75. When the timer 62 measures the time of 3.2 s represented by the first time information "11111", the timer 62 outputs an output SPO and a time up signal TU.
However, since the AND gate 66 is closed, the shift
Pulse SP is not output. Also, since the input terminal D of the flip-flop 75 is at a high level, the time
At the time when the up signal TU is output, this H'' signal is taken and the output of the flip-flop 75, that is, the variable mode signal KA continues to be held at "H". Then, the load pulse BL is outputted after a certain period of time as a timing pulse TR, and the time information "11011" of the second control code ○2 is inputted to the timer 62, and the timer 62 starts timing operation again. Further, when a shift pulse spot occurs after the time rule b, the AND gate 67 remains open, so this pulse BS passes through the gate 67 and becomes F.
``The third control code D3 is sent to the 0 register 60.
is shifted to the front stage. Since the control bit CD6 of the third control code D3 is "1", the AND gate 66 is opened by its output "H".

Further, since the control bit CD5 is also 1'', the variable mode signal KA continues to be held at H'', and the AND gate 6
7 will also remain open. Therefore, the timer 62
A time of 2.8 seconds represented by the time information TI of the second control code D2 is counted, and when an output SPO is output, this output SPO is outputted as a shift pulse SP via an AND gate 66. Since the time tb is a negligible time with respect to the shift pulse interval, this shift pulse SP will be output 6.0 seconds after the start pulse SS is output.

After measuring the time of 2.8 s, the circuit 65 generates a load pulse BL and a shift pulse SIG to the above-mentioned aircraft based on the time-up signal TU' output from the timer 62.
The time information T of the third control code ○3 is output from
I is accepted by the timer 62, and the fourth control code D4 is shifted to the front stage of the F'0 register 60.

It is easy to understand that the shift pulse SP is outputted every 5 s, 4 skin s, 3 ms, 2 kite s, 2 s, and 2 ms with the following control codes D3 to DIOI in the same manner. .

Here, when the time of 3.2 s represented by the time information TI of the control codes D3 and D5 is measured, the AND gate 66 is closed because the control bit CD6 of the control codes D4 and D6 is 0''. , shift pulse SP is not output.Then, 1.8 s, 0.8 m represented by time information TI of control codes D4 and D6
A shift pulse SP is output when the timing of s is completed, thereby making the shift pulse interval 5.0 kites, 4.
0 skin s is obtained respectively.

Control code ○7~D Kamegawa: After measuring the time determined by each time information TI, shift 'pulse S'
P is output. Now, the control code for the lqth crab ○IO
When the timer 62 measures the time information TI of
The 11th control code DI I is stored in the first stage of the FIFO register 60, and the control information CI is 01 and the control bit CD5 is o, so the signal "L" is D flip. .

It is input to the data input terminal D of the flop 75. Therefore, the timer 62 is 2.0 s represented by the time information 10011r of the first control code DIO.
When the time up signal TU is output after counting the time, the above signal "L" is taken by the flip-flop 75, so that the variable mode signal KA becomes "L" and the fixed mode signal KO becomes "H". After the time-up signal TU is output, the time information TI of the 11th control code DI is generated by the load pulse BL output from the generation circuit 65.
is input to the timer 62, and the timer 62 starts a timing operation. Even if the variable mode signal KA is “L”, the gate 67
is closed, so even if the shift pulse BS is output from the generation circuit 65 after that (after the time ratio), this pulse spot does not pass through the gate 67 and is not sent to the FIFO register 601, and the 11th control Code DII is still FIF
It continues to be stored in the front row of O Regis 60. timer 6
2 is the time information of the 11th control code DII 100
Even at the time when the 2.0 ms time represented by 11" is counted, the data input of the flip-flop 75 ○Yes L
'', the AND gate 67 continues to be closed, and the shift pulse output from the generation circuit 65 is F.
MO register 601 is not sent. Control code DII
Since the control bit CD6 is "1", the AND gate 6
6 is open, and the output SPO outputted every time 2.0 skin s is counted by the timer 62 is outputted as a shift pulse SP. Therefore, the 11th control code 011
The shift pulse SP continues to be output every 2.0 seconds while being held at the front stage of the FIFO register 60. This is fixed mode operation. Escape from the fixed mode operation is effected by the restart signal RS.

The fixed mode ends with a 2.0 s shift Q/Vless SP.

As a result of the motor continuing to operate at a constant speed, the bankbook 58 is conveyed downward, and finally a previously printed line detection signal is output from the sensor 64, and this signal is sent to the restart control control circuit 68.
When the command is sent to the latch circuit 69, a command specifying the sensor 54 has already been sent to the latch circuit 69.
The control circuit 68 confirms that the fixed mode signal KO is H'' and sets the restart signal RS to H''. Then, at the time when the time-up signal TU is output from the timer 62, the variable mode signal KA of the flip-flop 75 becomes H'' and returns to the variable mode again.As a result, the variable mode signal KA becomes H'', and as a result, the AND gate 67 was opened,
Since the shift pulse BS outputted thereafter is sent to six FIFO registers via the gate 67, the control code D12 of the 12th row is shifted to the front stage. Since the control codes CD5 of the control codes D12 to D25 are all 1'', the control codes DI to DIO are processed in exactly the same way, and the shift pulse is generated at the time interval specified by each control code or control code paper. SP is output,
Pulse motor 87 is operated according to control codes D12-D25.

Then, the time information TI of the control code D25 is sent to the timer 62.
When is measuring time, end code D26 is FIFO
It is located at the front stage of the register 60, and since the control bit CD7 of this code D26 is 1, and CD6 is 1.0'', the data input terminal D of the D flip-flop 76 is input to the data input terminal D.
” signal is input.

When the time-up signal TU is output for the time represented by the time information TI of the 25th control code D26, at this timing the output Q of the D flip-flop 76, that is, the motor stop signal MS becomes H''. , the pulse motor 87 is stopped. Since the control bit CD6 of the end code D26 is "0", the gate 66 is closed and the shift pulse SP is not output.Control code D
From 12 to D25, the number and pulse interval of shift pulses SP to rotate the pulse motor 87 by the amount of rotation necessary to convey the passbook 50 by the distance LO are determined, and the pulse interval is determined by the shift pulse SP detected by the sensor 54 for the previous printed line. The passbook 50' is transported exactly a distance LO from the start and then stopped. Each control code shown in the above code table is just one model for convenience of explanation, and it goes without saying that many more control codes are prepared in advance in actual pulse motor driving.

Also, in the above example, the pulse motor is accelerated after starting, operated at a constant speed at the required speed, and then decelerated to stop the pulse motor, but after constant speed operation, it is further accelerated. The pulse motor operates in a sequence in which it operates at a constant speed at high speed, rotates at a high speed for the required amount of rotation, then decelerates to a certain constant speed, operates at this constant speed for a while, then decelerates further and stops. It is also possible to control

In acceleration and deceleration control in this sequence, control bit CP5 is set to 1'' to operate in variable mode.
During constant speed operation, regardless of whether it is low speed or high speed, the control bit CD
It can be controlled in a fixed mode by setting 5 to 0''.
Furthermore, in the above example, the time unit represented by the time information TI is 0.1 ms, and the time information TI is composed of 5 bits, so when representing a time of 3.3 seconds or more, two bits are used. The above control code is required and the control bit CD6 has been devised for this purpose, but the unit time is 0.
When coarse settings are made such as 0.2 s and 0.3 ms instead of 1 s, or when the time information TI is configured with a larger number of bits instead of 5 bits, the control code CD6
becomes unnecessary.

When the time information TI is composed of 5 bits or more, the control code will be composed of 8 bits or more. control bit cd
Although 7 only represents motor stop in conjunction with control bit CD6 in the above example, it has many other uses. For example, it can be used to set the timing at which the page number reading sensor 56 starts reading the page number 57. When starting the pulse motor 87, it operates in variable mode (CD5 = 1), and then in fixed mode (CD5 = 1).
= 0) and drive the pulse motor at a constant speed. Passbook 5
When the lower end of 0 is detected by the detection switch 53, the detection signal of this detection switch 53 is sent to the restart control circuit 6.
8, and the variable mode is restarted by the high glue start signal RS from the restart control circuit 68. After the switch 53 detects, when the passbook 50 is conveyed by a distance L2, the sensor 56 reaches a position facing the page number 57 (
(See Figure 2). This distance L2 can be determined in advance from the control code in the variable mode.
After detecting the lower end of the passbook 50 by the switch 53, the passbook 50
has been transported exactly the distance L2, the control bit CD7
If the control code which is 1" is shifted to the front stage of the FIFO register 60, when the sensor 56 faces the page number 57, the control bit C which is 1" will be shifted to the first stage of the FIFO register 60.
D7 generates an output H''. This signal H'' is
When inputted to the data input terminal of a separately provided flip-flop similar to flip-flop 76, a signal for starting the discussion of sensor 56 is obtained from this flip-flop. Then, in response to this argument start signal, the sensor 56
All you have to do is open the discussion gate. In this reading start control, it is preferable to set the control bit CD6 to 1'' to prevent mixing with the end code.The control bit CD7 is used for various controls on external devices in cooperation with restart processing. It will be understood that this control bit CD7 can be
It can also be used to generate interrupt signals to the CPU. The restart processing is effective when synchronizing the drive of the pulse motor with the operation of external equipment, such as restarting by a signal from the sensor 54 or restarting by a signal from the detection switch 53, as described above. Many restart processes are possible other than the example, but it can also be used to change to the fixed mode based on commands from the program, such as when a passbook is returned, an abnormal check is detected, or driving irregularities are detected.

Many of the circuits shown in FIG. 6 can be replaced by software processing by the CPU if the CPU operates at high speed.

FIG. 11 schematically shows the operation of the control circuit, shift and load pulse generation circuit 65, and AND gate 67 when executed by program processing. After a start command (step 7, see FIG. 8), a buffer load pulse BL is output to preset time information TI of the first control code DI in the timer 62 (step 31). The timer 62 starts timing operation from this point. Next, output the buffer shift pulse BS and
The second control code ○2 is shifted to the first stage of the register 60 (step 32). It is determined whether the timer 32 has finished counting the time represented by the time information TI of the control code (step 33), and if the time is up, the control bits CD6, Look at CD7 (Step 34)
, if CD6=0 or CD7=1, go to step 35; if CD6=0 and CD7=1, go to step 4
2 generates a motor stop command. In step 35, C
Determine whether D6=1, and if YES, open the gate 66 to pass the output SPO of the timer 62 and output the motor shift pulse SP (step 36).
. If NO, step 36 is skipped and the shift pulse SP is not output. After that, the load pulse BL is output to preset the time information TI of the control code at the front stage of the FIFO register 60 in the timer 62 (step 3).
7). From this point on, the timer 62 starts counting again. Furthermore, it is determined whether the control bit CD5 of the control code at the front stage of the FIFO register 60 is 1'' (step 38), and if CD5=1, a shift pulse BS is generated (step 38). 39), FIFO
The contents of register 60 are shifted by one stage. If CD5=0, it is determined whether the restart signal RS is H'' (step 40), and if RS=day, step 39 is performed.
A shift pulse BS is generated in the same manner as (step 41). After outputting the shift pulse unevenness in steps 39 and 41, and if RS=L in step 40, the process returns to step 33. In the circuit shown in FIG. 6, a FIFO buffer register 601 temporarily stores a control code, controls an AND gate 66 using control information in the first stage, and inputs this control information to a control circuit 64 to perform an AND gate. Since the gate 67 and the like are controlled, the configuration of the circuit shown in FIG. 6 is extremely simple.

In order to control the AND gates 66, 67, etc. using the control information at the frontmost stage, a buffer register having a storage capacity of at least 1 byte (corresponding to one control code) is sufficient. Further, if the control code is immediately retrieved from the storage device, the buffer register becomes unnecessary. Many more variations can be given.

For example, in addition to the above-mentioned control bits CD5 to CD7, the control information of the control code may include one or more pulse motor control bits representing pulse motor selection, normal saddle, reverse rotation, etc. , control bit CD
5 to CD7 may be represented by 2 or more bits instead of 1 bit. In the above example, the pulse motor 87 for conveying the bankbook is described in detail, but it goes without saying that the same machine can also be used even if the pulse motor 88' for moving the print head is difficult to use.

Further, the present invention can be applied not only to a bookkeeping machine but also to any pulse motor built into other devices. As described above in detail, according to the present invention, it is possible to perform desired control such as starting, stopping, and constant speed operation of a pulse motor according to a predetermined sequence, and also to carry out transportation or movement. It enables a wide range of control of pulse motors, including accurate positioning of objects and synchronized operation with external equipment.

Moreover, in the case of constant speed operation, control can be performed in a fixed mode, which has the advantage of requiring less memory capacity. Further, by using the shift pulse control bits, time information representing one shift pulse interval can be set across two or more control codes, allowing for a wide range of control over the shift pulse interval.

[Brief explanation of the drawing]

Figure 1 is a side view of the passbook conveyance path provided inside the bookkeeping machine.
Figure 2 is a front view of the same, Figure 3 is a waveform diagram showing the relationship between the motor shift pulse and each excitation phase, Figure 4 is a time chart showing the control of the pulse motor from start to stop, and Figure 5 is a time chart showing the control of the pulse motor from start to stop. Figure 6 is a diagram showing the control code, Figure 6 is a block diagram showing the control circuit, and Figure 7 is a time diagram showing the operation of the circuit in Figure 6.
8 to 11 are flow charts showing the outline of programs executed by the CPU. 50... Passbook, 60... FIFO buffer register, 62... Timer (timekeeping device)
, 64... Control circuit, 65... Shift, load pulse generation circuit, 68... Restart control circuit, 8
3, 84... Phase generation circuit, 87, 88... Pulse.
motor. Figure 1 Figure 3 Figure N Vertical Figure 4 Figure 5 Figure 8 Figure ○ Fuji Figure Boat Figure 9 Figure 10 Figure 11

Claims (1)

[Claims] 1. A large number of control codes including time information representing the pulse interval of shift pulses of a pulse motor are stored in advance in a certain order in a storage device, and these control codes are sequentially read out. In a control method in which the time information is preset in a clock device and the shift pulse is generated based on the output generated after the clock device measures the time represented by the time information, the time information is set in each control code. In addition, a read control bit indicating read permission or prohibition is included, and the read control bit is determined every time each control code is read, and if the read control bit is read permission, the next control code is output after the output of the timing device is generated. and presets the time information in the timing device, and also determines the read control bit. If the read control bit prohibits reading, reading of the next control code is prohibited and control by that control code is transferred to an external device. A pulse motor control method that repeats until the read prohibition of the next control code is canceled by a signal. 2. The control information includes, in addition to the readout control bit, a bit for controlling an external device, etc., which starts or stops the operation of the external device, etc., and controls the pulse motor according to claim 1. Method. 3 In addition to the read control bits, the control information contains pulses and
3. The method of controlling a pulse motor according to claim 1, further comprising a pulse motor control bit indicating motor selection, forward rotation, reverse rotation, etc. 4. The pulse motor control method according to any one of claims 1 to 3, wherein the control code includes an end code indicating that the pulse motor is stopped. 5 At least one of the many control codes in the storage device
2. The method of controlling a pulse motor as claimed in claim 1, wherein the pulse motor is transferred to a buffer register, and reading from the buffer register is controlled by a read control bit. 6. A method for controlling a pulse motor according to claim 1, wherein the control code is read directly from a storage device. 7 A large number of control codes including time information representing the pulse interval of shift pulses of the pulse motor are stored in a storage device in a certain order in advance, and these control codes are sequentially read out and the time information is transmitted to the clock device. In the control method, the shift pulse is generated based on the output generated after the clock device measures the time represented by the time information, and each control code includes a read permission or a read permission in addition to the time information. A read control bit indicating prohibition and a shift pulse control bit indicating permission or prohibition of shift pulse generation are included, and the read control bit and shift pulse control bit are determined each time each control code is read. When reading is permitted, the next control code is read after the output of the timing device is generated, the time information is preset in the timing device, the read control bit and shift pulse control bit are determined, and the read control bit is If reading is prohibited,
The above clocking device inhibits the reading of the next control code and repeats the control using that control code until the reading prohibition of the next control code is canceled by an external signal. A pulse motor that generates a shift pulse based on the output of the timing device and, if the shift pulse control bit prohibits generation, prohibits generation of the shift pulse based on the output even if an output is generated from the timing device. control method. 8. In addition to the read control bit and the shift/pulse control bit, the control information includes a bit for controlling an external device, etc., and the operation of the external device, etc. is started or stopped by this bit, as described in claim 7. How to control a pulse motor. 9. Claim 7, wherein the control information includes, in addition to readout control bits and shift pulse control bits, pulse motor control bits that indicate pulse motor selection, forward rotation, reverse rotation, etc. Method of controlling a pulse motor described in Section 1. 10. The pulse motor control method according to claim 7, wherein the control code includes an end code indicating that the pulse motor is stopped. 11. The pulse motor of claim 7, wherein at least one of the plurality of control codes in the storage device is transferred to a buffer register, and readout from the buffer register is controlled by a readout control bit. Control method. 12. The method for controlling a pulse motor according to claim 7, wherein the control code is read directly from a storage device.