JPS627561B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a sequence control method that sequentially supplies control signals to a plurality of control objects.

When an object is moved along a predetermined conveyance path and subjected to scheduled processing, processing, etc. in sequence at a scheduled position, it is necessary to use appropriate means to confirm that the object has arrived at the scheduled position. Sequence control methods are widely used in which a microcomputer makes a determination, generates necessary commands and controls based on the determination, and performs scheduled processing, machining, etc. FIG. 1 is a block diagram for explaining the outline thereof, and for convenience of explanation, a copying machine is taken as an example. When you press the start button, the signal is sent to the CPU via the 1/0 port and system bus line SB, where it is decoded and the required instructions are read from the ROM to start and control each component. In response to this, the reference pulse generator 10 generates a reference pulse with a period inversely proportional to the traveling speed of the copy paper on the conveyance path. As is well known in the art, the pulse generator 10 may be constructed of a slit disk, a phototube, etc. connected to a driving part of a machine and rotated in synchronization therewith. The reference pulse is the interrupt control circuit 11,
Once transmitted to the CPU via bus line SB, execution of the instruction is caused to jump to the counting routine. In this counting routine, as shown in Figure 2, the content of the RAM at a certain address previously allocated for the counter is programmed to be incremented by 1, so the reference pulse is
Counted by a counter configured in RAM.
When this counter reaches a predetermined number of counts
The CPU generated control signals to create the necessary timing, such as driving a developer latch. By the way, in a normal copying machine, the control target is generally operated in synchronization with the leading edge of the copy paper, so the reference point is when the paper feed clutch starts to drive, so in the case of continuous copying of multiple sheets, the paper feed clutch The counter is reset each time the idle clutch starts to be driven. Therefore, in order to create timing after a long time has elapsed since the start of the paper feed clutch, such as the timing for jam check, for example,
If the maximum number N of counters allocated in the RAM is insufficient for time, one more counter must be allocated in the RAM. In other words, in the layout example shown in Figure 2, when the counter RAM (I-1) is counted up to its maximum count, the other continuous counter RAMs are
(I-2) is selected and incremented as the reference pulse is generated. On the other hand, if the interval at which the paper feed clutch is driven, that is, the time interval between the first and second sheets of copy paper, the second and third sheets, etc. After the counter RAM at the feed time is cleared and counting starts, the next paper feed will be performed before the maximum count is reached, and the counter RAM will be reset. In such a case, the second counter RAM () is set to a count value with an allowance for the minimum time interval between a certain paper feed time and the subsequent paper feed time.
The memory RAM for the first counter must be prepared for the subsequent paper feed by selecting and incrementing it with a reference pulse to continue counting with respect to the previous paper feed time. Therefore, multiple counters are required,
The disadvantage is that it takes up a lot of RAM space. Furthermore, in this case, the counter RAM selection and incrementing operations are shown in FIG. 3, but as can be seen, the steps or programs required to control the selection and incrementing operations are quite complex; The disadvantage is that it requires more ROM.

In the present invention, only one RAM is provided for the counter, and the count number when a reference event for starting counting (for example, the above-mentioned start of paper feed clutch drive) occurs is stored in the RAM, and the count number is stored in the RAM when the reference event occurs. By adding the number corresponding to the delay time to the count number when the reference event occurs and using the addition result as the basis for timing,
The RAM used as a counter is saved to the minimum necessary. Furthermore, since there is only one counter, the program for controlling the counter can be simplified, thereby saving RAM.

FIG. 4 is a schematic diagram showing RAM allocation in one embodiment of the present invention. For one counter
A RAM 21 is provided, and when a reference pulse is generated, interrupt control is performed to increment its contents by 1, as in the conventional example. for the counter in this case
RAM specification and increment operation are performed by the fifth
The result will be as shown in the figure. As is clear from a comparison with FIG. 3, the counter RAM selection and increment operation are greatly simplified compared to the conventional example. Also, as shown in Figure 4, for the reference event
RAMs 22 and 23 are provided, and the contents of the counter RAM 21 when a reference event occurs are stored in the reference event RAM. RAM for this reference event
Based on the contents of , a number corresponding to the delay time required for each type of control is added each time, and the addition result is used as the basis for timing. The contents of the standard event RAM must be saved until the timing that requires the longest delay time is processed, so the contents of the standard event RAM must be saved depending on the relationship between the interval at which the standard event occurs and the longest delay time. Provide an appropriate number of areas, two or more.

The operation of the present invention will be described below with reference to FIGS. 1, 6 and 7, taking the case of a copying machine as an example. For convenience of explanation, it is assumed here that two reference event RAMs are provided as shown in FIG. 4, and that the reference event RAM and counter RAM are both 8-bit. Of course, it is not limited. When the start button is pressed at time T0, processing A such as starting the main motor, energizing the counter and reference pulse generators, starting the counting operation, and driving the scan clutch are sequentially executed according to instructions from the CPU. . At time T1, the paper feed clutch is turned on and the first sheet of recording paper is fed, and at the same time, the first reference event RAM 22 is designated and the count value N1 of the counting RAM 21 at that time is stored there. . Assuming that the paper path switch I is stepped on, for example, 120 counts after the paper feed clutch is opened during normal operation, 120 is added to the content N1 of the first reference event RAM 22, and the sum (N1 + 120 ) is stored in the appropriate register. Thereafter, as processing B (for example, paper feed clutch OFF, etc.) progresses under the control of the CPU, the contents of the counter change to the contents of the register, that is, (N1
+120) is checked. When the two become equal, it is checked whether or not the paper pass switch I is being depressed at that time, and processing H (for example, jam determination processing, etc.) is performed according to that state. If the two are not equal, the process H is omitted and the process jumps to the next step. Next, close the paper feed clutch (time
Assuming that the paper pass switch is expected to be pressed after 300 counts from T1), the previously stored content N1 of the first reference RAM 22 will be
300 is added and the sum (N1+300) is stored in the appropriate register. Continue with the CPU as above.
Predetermined processing is performed under the control of the register, and the contents of the counter and the contents of the register are compared. Under the assumption of this embodiment, at time T2 before the first sheet of recording paper is ejected, the count value of the counter is 250.
When this happens, the paper feed clutch is activated again to feed the second sheet of recording paper. 2
The second reference RAM 23 is designated for controlling the second sheet of recording paper, and the counter content N2 at the time the paper feed clutch is energized again (T2) is stored therein. Then, 120 is added to the content, the result (N2+120) is stored in an appropriate register, and the same process as process B regarding the first sheet of recording paper is performed. When the count value of the counter becomes equal to (N1+300), the state of the paper pass switch is detected, and processing S (for example, jam judgment processing, etc.) is performed according to the result.
is proceeded, and the processing for the first sheet of recording paper is completed. Thereafter, at time T3, the paper feed clutch operates three times to feed the third recording paper, but at that time, the first reference event RAM 22 is
Since N1 stored in 2 is no longer needed, the counter content N3 at this time is stored in the first reference event RAM 22, and from then on, the same processing as described above for the first recording sheet is performed. will be carried out.
In this way, a plurality of objects to be controlled can be sequentially controlled according to the count value of the counter.

The above-described sequence control can be extremely easily programmed using a combination of standard instruction sets provided in ordinary microcomputers.

In addition, the above example describes an example in which a counter is set in the RAM area, but when using a microcomputer with a built-in counter in the IC chip, it is of course not necessary to provide a counter in the RAM area, and interrupts to the program can be avoided. This further simplifies the program, as it is no longer necessary to run the counting routine or control the counter.
This has the advantage of saving ROM. Note that, as is clear from the above explanation, the number of reference event RAMs specified in the RAM needs to be equal to or greater than the number of recording sheets that can exist on the transport path at the same time.

As is clear from the above, according to the present invention, the following effects are achieved.

(b) Even if the number of objects that temporarily exist on the transport path, in other words, the number of control channels becomes multiple, there is no need to create multiple counters accordingly, so the area occupied in RAM does not increase. .

(b) It is possible to prevent the program for selecting RAM for the counter and controlling the increment operation from becoming complicated.

(c) Since the reference pulse is a function of the moving speed of the object, even if the moving speed changes due to load fluctuations, it will not affect the control operation at all.

[Brief explanation of the drawing]

Fig. 1 is a schematic diagram for explaining a normal sequence control method, Figs. 2 and 4 are diagrams showing examples of RAM allocation in the conventional method and the present invention, and Fig. 3 and 5 are counts by program interrupts in the conventional method and the present invention. FIG. 6 is a flow chart of the routine, and FIG. 7 is a flow chart of one embodiment of the present invention, and FIG. 7 is a time chart. 10... Reference pulse generator, 11... Interrupt control circuit, 21... Counter RAM, 22, 23
...RAM for reference event.

Claims (1)

[Claims] 1. A controlled device according to whether or not a plurality of objects moving along a predetermined conveyance path and at a predetermined interval from each other arrive at a predetermined position. A sequence control method using a microcomputer for causing a robot to perform a scheduled operation, comprising a device that generates a reference pulse with a period inversely proportional to the moving speed of a moving object, and a counter that counts the reference pulse, When a scheduled reference event occurs, the contents of the counter at that time are stored in the reference event memory, and the value to be counted by the counter corresponding to the delay time from when the scheduled action is to be performed is stored in the reference event memory. Add it to the content stored in the memory, store the sum in an appropriate register, and when the count value of the counter and the sum stored in the register become equal, cause the controlled device to perform the scheduled operation. A sequence control method using a microcomputer that is characterized by: 2. A sequence control system using a microcomputer according to claim 1, characterized in that a memory for reference events is specified that is not less than the maximum number of moving objects that can exist on the conveyance path at the same time. 3. The aforementioned patent characterized in that one counter RAM is specified in the RAM, program interrupt control is performed every time a reference pulse occurs, and the content stored in the counter RAM is incremented by one. A sequence control system using a microcomputer according to claim 1 or 2. 4. A sequence control system using a microcomputer according to any one of claims 1 to 3, wherein the moving object is recording paper and the controlled device is a copying machine. 5. A sequence control system using a microcomputer according to claim 4, wherein the reference event is activation of the paper feed mechanism.