JPH05146196A - Step motor driving circuit - Google Patents

Abstract

PURPOSE:To rotary drive a step motor at high speed by means of a conventional CPU without requiring any special CPU. CONSTITUTION:A set data (f) is outputted from a control section (CPU) 11 and stored in a FIFO memory 12 which subsequently outputs the set data to a row double down counter 13. When a count value being set by the set data is counted, the row double counter 13 delivers a carry signal (i) to a phase control circuit 14 and the carry signal is also read into a FIFO memory 12.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a stepping motor drive circuit capable of high speed rotation drive.

[0002]

2. Description of the Related Art FIG. 10 shows a conventional drive control circuit for a stepping motor. The control unit 1 controls the operation of each unit C
ROM (read o together with PU (central processor unit)
It is composed of an nly memory (not shown) and I / O (input / output). Setting data (8) for controlling the speed of a stepping motor (not shown) is supplied from the control unit 1.
Bit data) signal a is output together with write signal b,
The data is input to the data latch circuit 2. The setting data transmitted by the data signal a from the control section 1 is stored and held (latched) in the data latch circuit 2 by the write signal b, and the stored and held setting data is stored in the loadable down counter 3. It was supposed to be input to.

A clock signal c output from the control section 1 is input to the loadable down counter 3, and a count value set by the setting data input from the data latch circuit 2 is input. Is down-counted by the input clock signal, and when the count value becomes "0", to the phase control circuit 4 for controlling the energization of the A phase, the inverted A phase, the B phase, and the inverted B phase of the stepping motor. The carry signal d is output. This phase control circuit 4
Performs energization control for each phase of the stepping motor on the basis of the advance clock obtained from the carry signal d and the rotation direction signal e input from the control unit 1.

The carry signal d is further input to the load terminal R of the loadable down counter 3, and
An interrupt signal d is input to the control unit 1, and the control unit 1 sends a data signal a for transmitting the next setting data to the data latch circuit 2 together with a write signal b based on the interrupt signal d. The loadable down counter 3 outputs the set data from the data latch circuit 2 by the carry signal d input to the load terminal R. FIG. 11 shows a flow chart of processing performed by the control unit (CPU) 1 when the carry (interrupt) signal d is input.

When an interrupt is generated by the carry signal d from the loadable down counter 3, it is judged whether or not an interrupt (carry) signal is input, and a standby state is entered until the interrupt signal is input. When the interrupt signal is input, the next setting data is calculated, and the calculated setting data is output as the write signal b and stored in the data latch circuit 2 by the data signal a. When the storage and holding of the setting data is completed, the system waits until the next interrupt by the carry signal d occurs.

As described above, at the timing at which the setting data is output from the control unit 1, the setting data is output to the data latch circuit 2 after the occurrence of an interrupt due to the carry signal d from the loadable down counter 3. It is designed to output.

[0007]

In the conventional stepping motor drive circuit, the data latch circuit 2 is used, the carry signal from the loadable down counter 3 is used as an interrupt signal, and the following setting is made by the control unit (CPU) 1. Since the data output process is performed, in the high-speed rotation driving of the stepping motor, while the control unit 1 is performing the output process of the next setting data, the stepping motor has already driven by the next setting data. The situation of entering will occur. That is, there is a problem that the output processing of the setting data by the control unit 1 cannot follow the stepping motor that is driven to rotate at high speed. In order to solve this problem, a CPU having a high processing speed may be used for the control unit 1, but such a high-speed CPU is used.
Has the problem of high cost.

Therefore, an object of the present invention is to provide a stepping motor drive circuit which can drive a stepping motor to rotate at high speed by using a conventional CPU without using an especially high speed CPU.

[0009]

The invention according to claim 1 is
Control means for setting the speed and rotation direction of the stepping motor and outputting a reference clock, setting data and rotation direction signal, and setting data output from this control means are sequentially input and stored and output in the input order. Fast in fast out mem
ory, first-in first-out type memory) and the set data output from this fast-in fast-out memory in order, and then outputs the carry signal after counting the set time by the reference clock and the fast-in fast-out by the carry signal. A counter that reads the next setting data from the memory and the phase of each phase of the stepping motor is determined by the rotation direction signal output from the control means, and a drive pulse is output to each phase of the stepping motor by the carry signal output from the counter. Drive pulse output means for outputting in a phase determined by the above.

According to a second aspect of the invention, in the first aspect of the invention, the reference clock is input from the control means, the period of the reference clock is multiplied by 2 and output to the counter. The counter is divided by 1.

In the invention according to claim 3, in the invention according to claim 2, the counter is irrelevant to the most significant bit of the setting data input from the fast-in fast-out memory to the counter, The data is fixed at 1.

[0012]

In the present invention having such a structure, the speed and the rotation direction of the stepping motor are set by the control means, and the reference clock, the setting data and the rotation direction signal are output. By the fast-in fast-out memory, the output setting data is sequentially input and stored, and is output in the input order.

Based on the setting data output from the fast-in / fast-out memory, the counter counts the set time by the reference clock output from the control means and outputs a carry signal, and the carry-in signal causes the fast-in operation. Read the next setting data from the fast-out memory.

The drive pulse output means determines the phase of each phase of the stepping motor according to the rotation direction signal output from the control means, and the drive pulse is determined for each phase of the stepping motor according to the carry signal output from the counter. Is output at the specified phase.

Further, the reference clock output from the control means is output to the counter after the period of the reference clock is multiplied by 2 to the nth power by the 1-division counter for 2 n.

Further, the data of the most significant bit in the counter is fixed to 1 regardless of the data of the most significant bit of the setting data (a plurality of bits of data) output from the fast-in fast-out memory.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described below with reference to the drawings.

In FIG. 1, reference numeral 11 denotes a control unit having a CPU (central processor unit) for controlling the operation of each unit. Data for controlling the drive of the stepping motor (not shown) is supplied from the control unit 11 according to the input confirmation of the writable signal g output from the 9-bit FIFO memory (fast in fast out memory) 12. The 9-bit data) signal f is output together with the write signal h and input to the FIFO memory 12. The setting data transmitted by the data signal f from the control unit 11 is sequentially stored and held in the FIFO memory 12 by the write signal h, and the stored and held setting data is the 8-bit loadable down counter 13.
The carry signal i output from the above is input to the 9-bit FIFO memory 12 as a read signal so that the carry signal i is input to the loadable down counter 13 in the order of being stored and held.

The loadable down counter 13 has
The clock signal j output from the control unit 11 is input, and the count value set by the setting data input from the FIFO memory 12 is down-counted by the input clock signal j. When the count value becomes "0", the carry signal i is output to the movement control circuit 14 that controls the energization of the A phase, the inverted A phase, the B phase, and the inverted B phase of the stepping motor. The phase control circuit 14 controls the carry signal i and the control unit 11
Energization control is performed for each phase of the stepping motor based on the rotation direction signal k input from.

The carry signal i is further input to the load terminal R of the loadable down counter 13, and the loadable down counter 13 reads the setting data from the FIFO memory 12 by the carry signal i input to the load terminal. It is like this.

FIG. 2 shows the loadable down counter 1 described above.
The carry signal i is output from the FIFO memory 12 to the FIFO memory 12 so that when the writable signal g is input from the FIFO memory 12, the control unit (CPU) 11
The flowchart of the process which is performed is shown.

When the carry signal i from the loadable down counter 13 is input to the FIFO memory 12, the FIFO memory 12 receives the carry signal i.
The setting data is output from the O memory 12 to the loadable down counter 13 in the order stored and held, and the writable signal g is generated from the FIFO memory 12.

First, it is determined whether or not the generated writable signal g has been input, and a standby state is entered until the writable signal g is input. When the writable signal g is input, the next setting data is calculated, and the setting data obtained by the calculation is output by the data signal f together with the writing signal h to obtain the FI.
The FO memory 12 is stored and held. When the storage and holding of the setting data is completed, it is determined whether the writable signal g is still output, and if the writable signal g is still output, the next setting data is calculated again. To return to.

If the writable signal g is not output, the process returns to the standby state until the writable signal g by the carry signal i from the loadable down counter 13 is generated again. Is becoming In the present embodiment having such a configuration, the write signal h from the control unit 11 is sent.
At the same time, the setting data is output to the FIFO memory 12 by the data signal f.

FIG. 3 shows the timing of each signal in the FIFO memory 12 at this time. FIG. 3A shows the data signal f input to the FIFO memory 12, and FIG.
The write signal h input to the FIFO memory 12 in FIG.
FIG. 3C shows a data signal (data signal f) output from the FIFO memory 12 to the loadable down counter 13.
A read signal (carry signal i) input to the FIFO memory 12 is shown in (d).

As shown in FIG. 3, the setting data is sequentially input to the FIFO memory 12 by the data signal f together with the write signal h. Of these, only the first setting data (data 1) is stored and held, and simultaneously output to the loadable down counter 13. Then, the next setting data (data 2) of the first setting data (data 1) is output by the input (down edge input) of the read signal (carry signal i) at time point C. The subsequent setting data is also output by the input of the read signal. However, if the next setting data is not input, even if the read signal is input, the setting data being output at that time is continuously output.

FIG. 4 shows the timing of each signal in the loadable down counter 13 at this time. FIG. 4A shows the clock signal j input to the loadable down counter 13, and FIG. 4B shows the loadable down counter 1.
Carry signal i output from 3 to phase control circuit 14, loadable down counter 13 to FIFO in FIG.
A read signal (carry signal i) output to the memory 12, a data signal (data signal f) input to the loadable down counter 13 from the FIFO memory 12 in FIG.
FIG. 4E shows a count data signal in the loadable down counter 13.

As shown in FIG. 4, when the input setting data is the count value "8", the previous setting data is being counted, and the count data signal set by the previous setting data is the clock. When the signal j is down-counted to "0", the carry signal i and the read signal are output as shown at time D, the count data signal is set by the input setting data, and the FIFO memory 12 The output setting data becomes the next setting data. The next setting data is
In the example of FIG. 4, the count value is "9".

When the count data signal set to "8" by the setting data of the count value "8" is counted down by the clock signal j and becomes "0", the carry signal i and the read signal are read again as shown at the time point E. The signal is output. Then, the count data signal is set to "9" by the setting data (count value "9") set at that time, and the countdown is started by the clock signal j.

The circuit control circuit 14 determines the forward rotation or the reverse rotation based on the direction rotation signal e output from the control section 11, and the phase advance obtained from the carry signal i output from the loadable down counter 13. Depending on the clock (CLK), A phase and B at the time of forward rotation (CW) shown in FIG.
Phase energization timing or reverse rotation (CC
The stepping motor is energized and driven based on the energization timings of the A phase and the B phase at the time of W).

As described above, according to this embodiment, the FIFO memory 12 is used, and the carry signal i from the loadable down counter 13 is input to the FIFO memory 12 as a read signal. Is
The setting data of the stepping motor is stored in the FIFO memory 12
Since it suffices to write the setting data into the FIFO memory 12 according to the capacity of, the timing of reading the setting data of the loadable down counter 13 is controlled by the carry signal i. Therefore, it is possible to drive the stepping motor to rotate at a high speed at a low cost as compared with a high-speed CPU without using a special high-speed CPU. Also,
FIG. 6 shows a second embodiment of the present invention.

In this embodiment, the line of the clock signal j to the control unit 11 and the loadable down counter 13 in the first embodiment described above is passed through the 1-division counter 15 for 2 to the nth power, A clock signal j output from the control unit 11 in a divide-by-1 counter 15 for 2 to the nth power.
Is converted into a clock signal (clock signal n times 2 to the nth power) of which the cycle is multiplied by the nth power of 2 and output to the loadable down counter 13.

The data signal p output from the control section 11 to the FIFO memory 12 together with the write signal h includes data for setting the frequency division value of the 1 frequency division counter 15 for the nth power of 2. Has been. That is, the high-order 2 bits of the data signal p are the 1-division counter 15 for the nth power of 2.
Is used for (division value data signal r) for setting the division value (0, 1, 2), and the lower 7 bits are used for (count data signal s) for the count value of the loadable down counter 13. Has been done.

From the FIFO memory 12,
The divided value data signal r is output to the 1-division counter 15 for the nth power of 2, and the loadable down counter 1
3, the count data signal s is output to 3, and the most significant bit of the count data signal input part of the loadable down counter 13 is fixed to "1".

FIG. 7 shows the loadable down counter 1 described above.
The carry signal i is output from the FIFO memory 12 to the FIFO memory 12 so that when the writable signal g is input from the FIFO memory 12, the control unit (CPU) 11
The flowchart of the process which is performed is shown.

When the carry signal i is input from the loadable down counter 13 to the FIFO memory 12, the FIFO
The setting data is output from the O memory 12 to the loadable down counter 13 in the order stored and held, and the writable signal g is generated from the FIFO memory 12.

First, it is determined whether or not the generated writable signal g is input, and a standby state is entered until the writable signal g is input. When the writable signal g is input, the next setting data and the data of the frequency division value of the n-th power of 2 of the frequency division counter 15 are calculated, and the calculated setting data and frequency division value data are obtained. Together with the write signal h and the data signal p
To be stored and held in the FIFO memory 12.
When the storage and holding of the setting data is completed, it is determined whether the writable signal g is still output, and if the writable signal g is still output, the next setting data is calculated again. To return to.

If the writable signal g is not output, the process returns to the standby state until the writable signal g by the carry signal i from the loadable down counter 13 is generated again. Is becoming

In this embodiment having such a configuration, the upper 2 bits of data of the clock signal j and the 9-bit data signal p output from the control unit 11 are divided by the nth power of 2 through the FIFO memory 12. 8 is input to the 1-divide counter 15, the clock signal n is not divided as shown in FIG. 8 (a) when the numerical value of the upper 2 bits is "0", and is shown in FIG. 8 (b) when it is "1". 8) when the clock signal n is divided by 1/2 and is "2" as shown in FIG.
A clock signal n divided by 1/4 as shown in (c), and a clock signal n divided by 1/8 as shown in FIG. It is output to the down counter 13. In this embodiment, 1/8 frequency division is not used.

Further, since the most significant bit of the loadable down counter 13 is fixed at "1", the control unit 1
The data of the lower 7 bits of the data signal output from 1 can take a numerical value from 128 to 255 depending on the data input to the loadable down counter 13 via the FIFO memory 12.

Also in this embodiment, similarly to the above-mentioned embodiment, the FIFO memory 12 shown in FIGS.
The loadable down counter 13 and the phase control circuit 14 are controlled according to the energization timing of each signal.

Therefore, as shown in FIG. 9, the 7-bit count data signal s and the frequency-dividing counter 1 for the nth power of 2 are used.
2 to the n-th power clock signal n from 5 to 1/128 to 1/255 to 1/5 with respect to the speed K of the clock signal j
It is possible to obtain a clock signal n that is a power of 2 to the n-th power of clock speeds L to M to N up to 12. Therefore, the loadable down counter 13 outputs the carry signal d based on the n-th power clock signal n of 2.
Carry signal d with clock speeds up to 1/512
The phase control circuit 14
Outputs the energization timing pulse of each phase of the stepping motor, so that the slow-up control of the stepping motor can be performed with high accuracy. In the embodiment, a clock speed of 1/512 to 1/1020 can be further generated as the carry signal d, but it is not shown in FIG.

As described above, in this embodiment, the FIFO memory 1
By using 2, it is possible to obtain the effect that the stepping motor similar to that of the above-described embodiment can be driven to rotate at high speed, and it is possible to obtain the maximum data input of the 1-division counter 15 and the loadable down counter 13 for 2 n. By fixing the upper bit to “1”, the slow-up control required for driving the stepping motor to rotate at high speed can be performed with higher accuracy.

[0044]

As described in detail above, according to the present invention,
It is possible to provide a stepping motor drive circuit capable of driving a stepping motor to rotate at high speed by using a conventional CPU without using a specially fast CPU.

[Brief description of drawings]

FIG. 1 is a block diagram showing a circuit configuration of essential parts of a first embodiment of the present invention.

FIG. 2 is a diagram showing a flow of processing performed by a control unit (CPU) of the embodiment.

FIG. 3 is a diagram showing the timing of each signal of the FIFO memory of the same embodiment.

FIG. 4 is a diagram showing the timing of each signal of the loadable down counter of the embodiment.

FIG. 5 is a view showing the energization timing of each phase of the stepping motor during forward rotation and reverse rotation of the embodiment.

FIG. 6 is a block diagram showing a circuit configuration of essential parts of a second embodiment of the present invention.

FIG. 7 is a diagram showing a flow of processing performed by a control unit (CPU) of the embodiment.

FIG. 8 is a diagram showing a clock signal frequency-divided by a 1-division counter for 2 to the nth power of the embodiment.

FIG. 9 is a diagram showing a speed curve when the stepping motor of the embodiment is started.

FIG. 10 is a block diagram showing a circuit configuration of a main part of a conventional example.

FIG. 11 is a diagram showing a flow of processing performed by a control unit (CPU) of a conventional example.

[Explanation of symbols]

11 ... Control unit (CPU), 12 ... FIFO memory, 13
… Loadable down counter, 14… Phase control circuit, f
... data signal, i ... carry signal.

Claims (3)

[Claims] 1. A control means for setting a speed and a rotation direction of a stepping motor to output a reference clock, setting data and a rotation direction signal, and setting data output from the control means are sequentially input and stored. Based on the fast-in / fast-out memory that outputs in the order of input and the setting data that is sequentially output from the fast-in / fast-out memory, the set time is counted by the reference clock, and then the carry signal is output and the carry signal is output. A counter that reads the next setting data from the fast-in fast-out memory by a signal, and the phase of each phase of the stepping motor is determined by the rotation direction signal output from the control means, and by the carry signal output from the counter. Drive pulse for each phase of the stepping motor A stepping motor drive circuit, characterized in that a drive pulse output means for outputting a phase determined to the stepping motor is provided. 2. A frequency dividing counter for dividing to the nth power of 2 for inputting the reference clock output from the control means and multiplying the period of this reference clock by the nth power of 2 to output to the counter. The stepping motor drive circuit according to claim 1. 3. The counter fixes the data of the most significant bit to 1 regardless of the data of the most significant bit of the setting data input from the fast in fast out memory to the counter. The stepping motor drive circuit according to claim 2.